src/experiment/cscore.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18
  19 class Scoreboard(Elaboratable):
  20     def __init__(self, rwid, n_regs):
  21         """ Inputs:
  22
  23             * :rwid:   bit width of register file(s) - both FP and INT
  24             * :n_regs: depth of register file(s) - number of FP and INT regs
  25         """
  26         self.rwid = rwid
  27         self.n_regs = n_regs
  28
  29         # Register Files
  30         self.intregs = RegFileArray(rwid, n_regs)
  31         self.fpregs = RegFileArray(rwid, n_regs)
  32
  33         # inputs
  34         self.int_store_i = Signal(reset_less=True) # instruction is a store
  35         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  36         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  37         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  38
  39         self.issue_o = Signal(reset_less=True) # instruction was accepted
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43
  44         m.submodules.intregs = self.intregs
  45         m.submodules.fpregs = self.fpregs
  46
  47         # register ports
  48         int_dest = self.intregs.write_port("dest")
  49         int_src1 = self.intregs.read_port("src1")
  50         int_src2 = self.intregs.read_port("src2")
  51
  52         fp_dest = self.fpregs.write_port("dest")
  53         fp_src1 = self.fpregs.read_port("src1")
  54         fp_src2 = self.fpregs.read_port("src2")
  55
  56         # Int ALUs
  57         add = ALU(self.rwid)
  58         sub = ALU(self.rwid)
  59         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  60         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  61         int_alus = [comp1, comp2]
  62
  63         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  64         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  65
  66         # Int FUs
  67         il = []
  68         int_src1_pend_v = []
  69         int_src2_pend_v = []
  70         int_rd_pend_v = []
  71         int_wr_pend_v = []
  72         for i, a in enumerate(int_alus):
  73             # set up Integer Function Unit, add to module (and python list)
  74             fu = IntFnUnit(self.n_regs, shadow_wid=0)
  75             setattr(m.submodules, "intfu%d" % i, fu)
  76             il.append(fu)
  77             # collate the read/write pending vectors (to go into global pending)
  78             int_src1_pend_v.append(fu.src1_pend_o)
  79             int_src2_pend_v.append(fu.src2_pend_o)
  80             int_rd_pend_v.append(fu.int_rd_pend_o)
  81             int_wr_pend_v.append(fu.int_wr_pend_o)
  82         int_fus = Array(il)
  83
  84         # Count of number of FUs
  85         n_int_fus = len(il)
  86         n_fp_fus = 0 # for now
  87
  88         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  89
  90         # XXX replaced by array of FUs? *FnUnit
  91         # # Integer FU-FU Dep Matrix
  92         # m.submodules.intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  93         # Integer FU-Reg Dep Matrix
  94         # intregdeps = FURegDepMatrix(self.n_regs, n_int_fus)
  95         # m.submodules.intregdeps = intregdeps
  96
  97         # Integer Priority Picker 1: Adder + Subtractor
  98         intpick1 = GroupPicker(2) # picks between add and sub
  99         m.submodules.intpick1 = intpick1
 100
 101         # Global Pending Vectors (INT and FP)
 102         # NOTE: number of vectors is NOT same as number of FUs.
 103         g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
 104         g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
 105         g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
 106         g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
 107         m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
 108         m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
 109         m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
 110         m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
 111
 112         # INT/FP Issue Unit
 113         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
 114         m.submodules.issueunit = issueunit
 115
 116         #---------
 117         # ok start wiring things together...
 118         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 119         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 120         #---------
 121
 122         #---------
 123         # Issue Unit is where it starts.  set up some in/outs for this module
 124         #---------
 125         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 126                      issueunit.i.dest_i.eq(self.int_dest_i),
 127                      issueunit.i.src1_i.eq(self.int_src1_i),
 128                      issueunit.i.src2_i.eq(self.int_src2_i),
 129                      self.issue_o.eq(issueunit.issue_o)
 130                     ]
 131         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 132
 133         # connect global rd/wr pending vectors
 134         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 135         # TODO: issueunit.f (FP)
 136
 137         # and int function issue / busy arrays, and dest/src1/src2
 138         fn_issue_l = []
 139         fn_busy_l = []
 140         for i, fu in enumerate(il):
 141             fn_issue_l.append(fu.issue_i)
 142             fn_busy_l.append(fu.busy_o)
 143             m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
 144             m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
 145             m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
 146             m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
 147             # XXX sync, so as to stop a simulation infinite loop
 148             m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
 149
 150         #---------
 151         # connect Function Units
 152         #---------
 153
 154         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 155         m.d.comb += il[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
 156         m.d.comb += il[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
 157
 158         m.d.comb += il[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
 159         m.d.comb += il[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
 160
 161         # Connect INT Fn Unit global wr/rd pending
 162         for fu in il:
 163             m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 164             m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 165
 166         # Connect Picker
 167         #---------
 168         # XXX sync, again to avoid an infinite loop.  is it the right thing???
 169         m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
 170         m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
 171         m.d.sync += intpick1.readable_i[0].eq(il[0].int_readable_o) # add rdable
 172         m.d.comb += intpick1.writable_i[0].eq(il[0].int_writable_o) # add rdable
 173         m.d.sync += intpick1.readable_i[1].eq(il[1].int_readable_o) # sub rdable
 174         m.d.comb += intpick1.writable_i[1].eq(il[1].int_writable_o) # sub rdable
 175
 176         #---------
 177         # Connect Register File(s)
 178         #---------
 179         m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
 180         m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
 181         m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
 182
 183         # merge (OR) all integer FU / ALU outputs to a single value
 184         # bit of a hack: treereduce needs a list with an item named "dest_o"
 185         dest_o = treereduce(int_alus)
 186         m.d.comb += int_dest.data_i.eq(dest_o)
 187
 188         # connect ALUs
 189         for i, alu in enumerate(int_alus):
 190             m.d.comb += alu.go_rd_i.eq(il[i].go_rd_i) # chained from intpick
 191             m.d.comb += alu.go_wr_i.eq(il[i].go_wr_i) # chained from intpick
 192             m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 193             #m.d.comb += fn_busy_l[i].eq(alu.busy_o)  # XXX ignore, use fnissue
 194             m.d.comb += alu.src1_i.eq(int_src1.data_o)
 195             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 196             m.d.comb += il[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
 197
 198         return m
 199
 200
 201     def __iter__(self):
 202         yield from self.intregs
 203         yield from self.fpregs
 204         yield self.int_store_i
 205         yield self.int_dest_i
 206         yield self.int_src1_i
 207         yield self.int_src2_i
 208         yield self.issue_o
 209         #yield from self.int_src1
 210         #yield from self.int_dest
 211         #yield from self.int_src1
 212         #yield from self.int_src2
 213         #yield from self.fp_dest
 214         #yield from self.fp_src1
 215         #yield from self.fp_src2
 216
 217     def ports(self):
 218         return list(self)
 219
 220 IADD = 0
 221 ISUB = 1
 222
 223 def int_instr(dut, op, src1, src2, dest):
 224     for i in range(len(dut.int_insn_i)):
 225         yield dut.int_insn_i[i].eq(0)
 226     yield dut.int_dest_i.eq(dest)
 227     yield dut.int_src1_i.eq(src1)
 228     yield dut.int_src2_i.eq(src2)
 229     yield dut.int_insn_i[op].eq(1)
 230
 231 def print_reg(dut, rnums):
 232     rs = []
 233     for rnum in rnums:
 234         reg = yield dut.intregs.regs[rnum].reg
 235         rs.append("%x" % reg)
 236     rnums = map(str, rnums)
 237     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 238
 239 def scoreboard_sim(dut):
 240     for i in range(1, dut.n_regs):
 241         yield dut.intregs.regs[i].reg.eq(i)
 242     yield
 243     yield from int_instr(dut, IADD, 4, 3, 5)
 244     yield from print_reg(dut, [3,4,5])
 245     yield
 246     yield from int_instr(dut, IADD, 5, 2, 5)
 247     yield from print_reg(dut, [3,4,5])
 248     yield
 249     yield from int_instr(dut, ISUB, 5, 2, 3)
 250     yield from print_reg(dut, [3,4,5])
 251     yield
 252     yield from print_reg(dut, [3,4,5])
 253     yield
 254     yield from print_reg(dut, [3,4,5])
 255     yield
 256     yield from print_reg(dut, [3,4,5])
 257     yield
 258
 259
 260 def test_scoreboard():
 261     dut = Scoreboard(32, 8)
 262     vl = rtlil.convert(dut, ports=dut.ports())
 263     with open("test_scoreboard.il", "w") as f:
 264         f.write(vl)
 265
 266     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 267
 268
 269 if __name__ == '__main__':
 270     test_scoreboard()