src/experiment/cscore.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18 from random import randint
  19
  20
  21 class Scoreboard(Elaboratable):
  22     def __init__(self, rwid, n_regs):
  23         """ Inputs:
  24
  25             * :rwid:   bit width of register file(s) - both FP and INT
  26             * :n_regs: depth of register file(s) - number of FP and INT regs
  27         """
  28         self.rwid = rwid
  29         self.n_regs = n_regs
  30
  31         # Register Files
  32         self.intregs = RegFileArray(rwid, n_regs)
  33         self.fpregs = RegFileArray(rwid, n_regs)
  34
  35         # inputs
  36         self.int_store_i = Signal(reset_less=True) # instruction is a store
  37         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  38         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  39         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  40
  41         self.issue_o = Signal(reset_less=True) # instruction was accepted
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45
  46         m.submodules.intregs = self.intregs
  47         m.submodules.fpregs = self.fpregs
  48
  49         # register ports
  50         int_dest = self.intregs.write_port("dest")
  51         int_src1 = self.intregs.read_port("src1")
  52         int_src2 = self.intregs.read_port("src2")
  53
  54         fp_dest = self.fpregs.write_port("dest")
  55         fp_src1 = self.fpregs.read_port("src1")
  56         fp_src2 = self.fpregs.read_port("src2")
  57
  58         # Int ALUs
  59         add = ALU(self.rwid)
  60         sub = ALU(self.rwid)
  61         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  62         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  63         int_alus = [comp1, comp2]
  64
  65         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  66         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  67
  68         # Int FUs
  69         if_l = []
  70         int_src1_pend_v = []
  71         int_src2_pend_v = []
  72         int_rd_pend_v = []
  73         int_wr_pend_v = []
  74         for i, a in enumerate(int_alus):
  75             # set up Integer Function Unit, add to module (and python list)
  76             fu = IntFnUnit(self.n_regs, shadow_wid=0)
  77             setattr(m.submodules, "intfu%d" % i, fu)
  78             if_l.append(fu)
  79             # collate the read/write pending vectors (to go into global pending)
  80             int_src1_pend_v.append(fu.src1_pend_o)
  81             int_src2_pend_v.append(fu.src2_pend_o)
  82             int_rd_pend_v.append(fu.int_rd_pend_o)
  83             int_wr_pend_v.append(fu.int_wr_pend_o)
  84         int_fus = Array(if_l)
  85
  86         # Count of number of FUs
  87         n_int_fus = len(if_l)
  88         n_fp_fus = 0 # for now
  89
  90         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  91
  92         # XXX replaced by array of FUs? *FnUnit
  93         # # Integer FU-FU Dep Matrix
  94         # m.submodules.intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  95         # Integer FU-Reg Dep Matrix
  96         # intregdeps = FURegDepMatrix(self.n_regs, n_int_fus)
  97         # m.submodules.intregdeps = intregdeps
  98
  99         # Integer Priority Picker 1: Adder + Subtractor
 100         intpick1 = GroupPicker(2) # picks between add and sub
 101         m.submodules.intpick1 = intpick1
 102
 103         # Global Pending Vectors (INT and FP)
 104         # NOTE: number of vectors is NOT same as number of FUs.
 105         g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
 106         g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
 107         g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
 108         g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
 109         m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
 110         m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
 111         m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
 112         m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
 113
 114         # INT/FP Issue Unit
 115         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
 116         m.submodules.issueunit = issueunit
 117
 118         #---------
 119         # ok start wiring things together...
 120         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 121         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 122         #---------
 123
 124         #---------
 125         # Issue Unit is where it starts.  set up some in/outs for this module
 126         #---------
 127         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 128                      issueunit.i.dest_i.eq(self.int_dest_i),
 129                      issueunit.i.src1_i.eq(self.int_src1_i),
 130                      issueunit.i.src2_i.eq(self.int_src2_i),
 131                      self.issue_o.eq(issueunit.issue_o)
 132                     ]
 133         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 134
 135         # connect global rd/wr pending vectors
 136         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 137         # TODO: issueunit.f (FP)
 138
 139         # and int function issue / busy arrays, and dest/src1/src2
 140         fn_issue_l = []
 141         fn_busy_l = []
 142         for i, fu in enumerate(if_l):
 143             fn_issue_l.append(fu.issue_i)
 144             fn_busy_l.append(fu.busy_o)
 145             m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
 146             m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
 147             m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
 148             m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
 149             # XXX sync, so as to stop a simulation infinite loop
 150             m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
 151
 152         #---------
 153         # connect Function Units
 154         #---------
 155
 156         # XXX sync, again to avoid an infinite loop.  is it the right thing???
 157
 158         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 159         m.d.sync += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
 160         m.d.comb += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
 161
 162         m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
 163         m.d.comb += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
 164
 165         # Connect INT Fn Unit global wr/rd pending
 166         for fu in if_l:
 167             m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 168             m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 169
 170         # Connect Picker
 171         #---------
 172         m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
 173         m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
 174         m.d.comb += intpick1.readable_i[0].eq(if_l[0].int_readable_o) # add rd
 175         m.d.comb += intpick1.writable_i[0].eq(if_l[0].int_writable_o) # add wr
 176         m.d.comb += intpick1.readable_i[1].eq(if_l[1].int_readable_o) # sub rd
 177         m.d.comb += intpick1.writable_i[1].eq(if_l[1].int_writable_o) # sub wr
 178
 179         #---------
 180         # Connect Register File(s)
 181         #---------
 182         m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
 183         m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
 184         m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
 185
 186         # merge (OR) all integer FU / ALU outputs to a single value
 187         # bit of a hack: treereduce needs a list with an item named "dest_o"
 188         dest_o = treereduce(int_alus)
 189         m.d.comb += int_dest.data_i.eq(dest_o)
 190
 191         # connect ALUs
 192         for i, alu in enumerate(int_alus):
 193             m.d.comb += alu.go_rd_i.eq(if_l[i].go_rd_i) # chained from intpick
 194             m.d.comb += alu.go_wr_i.eq(if_l[i].go_wr_i) # chained from intpick
 195             m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 196             #m.d.comb += fn_busy_l[i].eq(alu.busy_o)  # XXX ignore, use fnissue
 197             m.d.comb += alu.src1_i.eq(int_src1.data_o)
 198             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 199             m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
 200
 201         return m
 202
 203
 204     def __iter__(self):
 205         yield from self.intregs
 206         yield from self.fpregs
 207         yield self.int_store_i
 208         yield self.int_dest_i
 209         yield self.int_src1_i
 210         yield self.int_src2_i
 211         yield self.issue_o
 212         #yield from self.int_src1
 213         #yield from self.int_dest
 214         #yield from self.int_src1
 215         #yield from self.int_src2
 216         #yield from self.fp_dest
 217         #yield from self.fp_src1
 218         #yield from self.fp_src2
 219
 220     def ports(self):
 221         return list(self)
 222
 223 IADD = 0
 224 ISUB = 1
 225
 226 class RegSim:
 227     def __init__(self, rwidth, nregs):
 228         self.rwidth = rwidth
 229         self.regs = [0] * nregs
 230
 231     def op(self, op, src1, src2, dest):
 232         src1 = self.regs[src1]
 233         src2 = self.regs[src2]
 234         if op == IADD:
 235             val = (src1 + src2) & ((1<<(self.rwidth+1))-1)
 236         elif op == ISUB:
 237             val = (src1 - src2) & ((1<<(self.rwidth+1))-1)
 238         self.regs[dest] = val
 239
 240     def setval(self, dest, val):
 241         self.regs[dest] = val
 242
 243     def dump(self, dut):
 244         for i, val in enumerate(self.regs):
 245             reg = yield dut.intregs.regs[i].reg
 246             okstr = "OK" if reg == val else "!ok"
 247             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
 248
 249     def check(self, dut):
 250         for i, val in enumerate(self.regs):
 251             reg = yield dut.intregs.regs[i].reg
 252             if reg != val:
 253                 print("reg %d expected %x received %x\n" % (i, val, reg))
 254                 yield from self.dump(dut)
 255                 assert False
 256
 257 def int_instr(dut, alusim, op, src1, src2, dest):
 258     for i in range(len(dut.int_insn_i)):
 259         yield dut.int_insn_i[i].eq(0)
 260     yield dut.int_dest_i.eq(dest)
 261     yield dut.int_src1_i.eq(src1)
 262     yield dut.int_src2_i.eq(src2)
 263     yield dut.int_insn_i[op].eq(1)
 264     alusim.op(op, src1, src2, dest)
 265
 266
 267 def print_reg(dut, rnums):
 268     rs = []
 269     for rnum in rnums:
 270         reg = yield dut.intregs.regs[rnum].reg
 271         rs.append("%x" % reg)
 272     rnums = map(str, rnums)
 273     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 274
 275
 276 def scoreboard_sim(dut, alusim):
 277     for i in range(1, dut.n_regs):
 278         yield dut.intregs.regs[i].reg.eq(i)
 279         alusim.setval(i, i)
 280
 281     yield from int_instr(dut, alusim, IADD, 4, 3, 5)
 282     yield from print_reg(dut, [3,4,5])
 283     yield
 284     yield from int_instr(dut, alusim, IADD, 5, 2, 5)
 285     yield from print_reg(dut, [3,4,5])
 286     yield
 287     yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
 288     yield from print_reg(dut, [3,4,5])
 289     yield
 290     for i in range(len(dut.int_insn_i)):
 291         yield dut.int_insn_i[i].eq(0)
 292     yield from print_reg(dut, [3,4,5])
 293     yield
 294     yield from print_reg(dut, [3,4,5])
 295     yield
 296     yield from print_reg(dut, [3,4,5])
 297     yield
 298
 299     yield from alusim.check(dut)
 300
 301     for i in range(100):
 302         src1 = randint(0, dut.n_regs-1)
 303         src2 = randint(0, dut.n_regs-1)
 304         dest = randint(1, dut.n_regs-1)
 305         op = randint(0, 1)
 306         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
 307         yield from int_instr(dut, alusim, op, src1, src2, dest)
 308         yield
 309
 310     for i in range(len(dut.int_insn_i)):
 311         yield dut.int_insn_i[i].eq(0)
 312
 313     yield
 314     yield
 315     yield
 316     yield
 317     yield from alusim.check(dut)
 318
 319
 320 def test_scoreboard():
 321     dut = Scoreboard(32, 8)
 322     alusim = RegSim(32, 8)
 323     vl = rtlil.convert(dut, ports=dut.ports())
 324     with open("test_scoreboard.il", "w") as f:
 325         f.write(vl)
 326
 327     run_simulation(dut, scoreboard_sim(dut, alusim),
 328                         vcd_name='test_scoreboard.vcd')
 329
 330
 331 if __name__ == '__main__':
 332     test_scoreboard()