src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """ div/rem/sqrt/rsqrt pipeline. """
   4
   5 from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
   6                    DivPipeCoreInterstageData, DivPipeCoreOutputData)
   7 from ieee754.fpcommon.getop import FPPipeContext
   8
   9
  10 class DivPipeConfig:
  11     """ Configuration for the div/rem/sqrt/rsqrt pipeline.
  12
  13     :attribute pspec: FIXME: document
  14     :attribute core_config: the ``DivPipeCoreConfig`` instance.
  15     """
  16
  17     def __init__(self, pspec):
  18         """ Create a ``DivPipeConfig`` instance. """
  19         self.pspec = pspec
  20         # FIXME: get bit_width, fract_width, and log2_radix from pspec or pass
  21         # in as arguments
  22         self.core_config = DivPipeCoreConfig(bit_width,
  23                                              fract_width,
  24                                              log2_radix)
  25
  26
  27 class DivPipeBaseData:
  28     """ input data base type for ``DivPipe``.
  29
  30     :attribute out_do_z: FIXME: document
  31     :attribute oz: FIXME: document
  32     :attribute ctx: FIXME: document
  33     :attribute muxid:
  34         FIXME: document
  35         Alias of ``ctx.muxid``.
  36     :attribute config: the ``DivPipeConfig`` instance.
  37     """
  38
  39     def __init__(self, config):
  40         """ Create a ``DivPipeBaseData`` instance. """
  41         self.config = config
  42         width = config.pspec['width']
  43         self.out_do_z = Signal(reset_less=True)
  44         self.oz = Signal(width, reset_less=True)
  45
  46         self.ctx = FPPipeContext(config.pspec)  # context: muxid, operator etc.
  47         # FIXME: add proper muxid explanation somewhere and refer to it here
  48         self.muxid = self.ctx.muxid  # annoying. complicated.
  49
  50     def __iter__(self):
  51         """ Get member signals. """
  52         yield self.out_do_z
  53         yield self.oz
  54         yield from self.ctx
  55
  56     def eq(self, rhs):
  57         """ Assign member signals. """
  58         return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  59                 self.ctx.eq(i.ctx)]
  60
  61
  62 class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
  63     """ input data type for ``DivPipe``. """
  64
  65     def __init__(self, config):
  66         """ Create a ``DivPipeInputData`` instance. """
  67         DivPipeCoreInputData.__init__(self, config.core_config)
  68         DivPipeBaseData.__init__(self, config)
  69
  70     def __iter__(self):
  71         """ Get member signals. """
  72         yield from DivPipeCoreInputData.__iter__(self)
  73         yield from DivPipeBaseData.__iter__(self)
  74
  75     def eq(self, rhs):
  76         """ Assign member signals. """
  77         return DivPipeCoreInputData.eq(self, rhs) + \
  78             DivPipeBaseData.eq(self, rhs)
  79
  80
  81 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
  82     """ interstage data type for ``DivPipe``. """
  83
  84     def __init__(self, config):
  85         """ Create a ``DivPipeInterstageData`` instance. """
  86         DivPipeCoreInterstageData.__init__(self, config.core_config)
  87         DivPipeBaseData.__init__(self, config)
  88
  89     def __iter__(self):
  90         """ Get member signals. """
  91         yield from DivPipeCoreInterstageData.__iter__(self)
  92         yield from DivPipeBaseData.__iter__(self)
  93
  94     def eq(self, rhs):
  95         """ Assign member signals. """
  96         return DivPipeCoreInterstageData.eq(self, rhs) + \
  97             DivPipeBaseData.eq(self, rhs)
  98
  99
 100 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
 101     """ output data type for ``DivPipe``. """
 102
 103     def __init__(self, config):
 104         """ Create a ``DivPipeOutputData`` instance. """
 105         DivPipeCoreOutputData.__init__(self, config.core_config)
 106         DivPipeBaseData.__init__(self, config)
 107
 108     def __iter__(self):
 109         """ Get member signals. """
 110         yield from DivPipeCoreOutputData.__iter__(self)
 111         yield from DivPipeBaseData.__iter__(self)
 112
 113     def eq(self, rhs):
 114         """ Assign member signals. """
 115         return DivPipeCoreOutputData.eq(self, rhs) + \
 116             DivPipeBaseData.eq(self, rhs)
 117
 118
 119 class DivPipeBaseStage:
 120     """ Base Mix-in for DivPipe*Stage. """
 121
 122     def _elaborate(self, m, platform):
 123         m.d.comb += self.o.oz.eq(self.i.oz)
 124         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 125         m.d.comb += self.o.ctx.eq(self.i.ctx)
 126
 127 # FIXME: in DivPipeSetupStage.elaborate
 128 # DivPipeBaseStage._elaborate(self, m, platform)
 129
 130 # FIXME: in DivPipeCalculateStage.elaborate
 131 # DivPipeBaseStage._elaborate(self, m, platform)
 132
 133 # FIXME: in DivPipeFinalStage.elaborate
 134 # DivPipeBaseStage._elaborate(self, m, platform)