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[ieee754fpu.git] / src / ieee754 / fpadd / datastruct.py
1 """IEEE754 Floating Point Adder Pipeline
2
3 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4
5 """
6
7 from nmigen import Signal
8 from ieee754.fpcommon.fpbase import FPNumBaseRecord, FPRoundingMode
9 from ieee754.fpcommon.getop import FPPipeContext
10
11
12 class FPAddStage0Data:
13
14 def __init__(self, pspec):
15 width = pspec.width
16 self.z = FPNumBaseRecord(width, False)
17 self.out_do_z = Signal(reset_less=True)
18 self.oz = Signal(width, reset_less=True)
19 self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits
20 self.ctx = FPPipeContext(pspec)
21 self.muxid = self.ctx.muxid
22
23 self.rm = Signal(FPRoundingMode, reset=FPRoundingMode.DEFAULT)
24 """rounding mode"""
25
26 def eq(self, i):
27 return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
28 self.tot.eq(i.tot), self.ctx.eq(i.ctx), self.rm.eq(i.rm)]