src/ieee754/fpadd/test/test_add16.py

   1 # FIXME: This file is on the pytest ignore list in pyproject.toml because it has borked imports
   2 from operator import add
   3
   4 from nmigen import Module, Signal
   5 from nmigen.compat.sim import run_simulation
   6
   7 from nmigen_add_experiment import FPADD
   8
   9 from unit_test_half import (get_mantissa, get_exponent, get_sign, is_nan,
  10                                 is_inf, is_pos_inf, is_neg_inf,
  11                                 match, get_case, check_case, run_fpunit,
  12                                 run_edge_cases, run_corner_cases)
  13
  14 def testbench(dut):
  15     #yield from check_case(dut, 0x7800, 0xff6f, 0xff6f)
  16     #yield from check_case(dut, 0x0000, 0x7c32, 0x7e32)
  17     #yield from check_case(dut, 0x0000, 0x7da9, 0x7fa9)
  18     #yield from check_case(dut, 0x0000, 0x7ea0, 0x7ea0)
  19     #yield from check_case(dut, 0x7c9a, 0x8000, 0x7e9a)
  20     #yield from check_case(dut, 0x7d5e, 0x0000, 0x7f5e)
  21     #yield from check_case(dut, 0x8000, 0x7c8c, 0x7e8c)
  22     #yield from check_case(dut, 0x8000, 0xfc55, 0xfe55)
  23     #yield from check_case(dut, 0x8000, 0x7e1a, 0x7e1a)
  24
  25     #yield from check_case(dut, 0x8000, 0xfc01, 0x7e00)
  26     yield from check_case(dut, 0xfc00, 0x7c00, 0x7e00)
  27     yield from check_case(dut, 0x8000, 0, 0)
  28     yield from check_case(dut, 0, 0, 0)
  29
  30     count = 0
  31
  32     #regression tests
  33     stimulus_a = [ 0x8000, 0x8000 ]
  34     stimulus_b = [ 0x0000, 0xfc01 ]
  35     yield from run_fpunit(dut, stimulus_a, stimulus_b, add)
  36     count += len(stimulus_a)
  37     print (count, "vectors passed")
  38
  39     yield from run_corner_cases(dut, count, add)
  40     yield from run_edge_cases(dut, count, add)
  41
  42 if __name__ == '__main__':
  43     dut = FPADD(width=16, single_cycle=True)
  44     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")
  45