debug fpmul pipeline
[ieee754fpu.git] / src / ieee754 / fpmul / mulstages.py
1 # IEEE Floating Point Multiplier
2
3 from nmigen import Module
4 from nmigen.cli import main, verilog
5
6 from nmutil.singlepipe import (StageChain, SimpleHandshake)
7
8 from ieee754.fpcommon.fpbase import FPState
9 from ieee754.fpcommon.denorm import FPSCData
10 from ieee754.fpcommon.postcalc import FPAddStage1Data
11 from .mul0 import FPMulStage0Mod
12 from .mul1 import FPMulStage1Mod
13
14
15 class FPMulStages(FPState, SimpleHandshake):
16
17 def __init__(self, width, id_wid):
18 FPState.__init__(self, "align")
19 self.width = width
20 self.id_wid = id_wid
21 SimpleHandshake.__init__(self, self) # pipeline is its own stage
22 self.m1o = self.ospec()
23
24 def ispec(self):
25 return FPSCData(self.width, self.id_wid)
26
27 def ospec(self):
28 return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
29
30 def setup(self, m, i):
31 """ links module to inputs and outputs
32 """
33
34 # chain MulStage0 and MulStage1
35 m0mod = FPMulStage0Mod(self.width, self.id_wid)
36 m1mod = FPMulStage1Mod(self.width, self.id_wid)
37
38 chain = StageChain([m0mod, m1mod])
39 chain.setup(m, i)
40
41 self.o = m1mod.o
42
43 def process(self, i):
44 return self.o
45
46 def action(self, m):
47 m.d.sync += self.m1o.eq(self.process(None))
48 m.next = "normalise_1"
49
50