1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
6 import diplomacy.{LazyModule,LazyMultiIOModuleImp}
7 import rocketchip.{HasSystemNetworks}
8 import uncore.tilelink2.TLFragmenter
10 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
12 trait HasPeripheryI2C extends HasSystemNetworks {
13 val i2cParams = p(PeripheryI2CKey)
14 val i2c = i2cParams map { params =>
15 val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
16 i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
17 intBus.intnode := i2c.intnode
22 trait HasPeripheryI2CBundle {
23 val i2cs: Vec[I2CPort]
25 def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
26 val pins = Module(new I2CGPIOPort(syncStages))
32 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
33 val outer: HasPeripheryI2C
34 val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
36 (i2cs zip outer.i2c).foreach { case (io, device) =>
37 io <> device.module.io.port