1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import chisel3.experimental.{withClockAndReset}
6 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
8 class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) {
11 val dq = Vec(4, pingen())
12 val cs = Vec(c.csWidth, pingen())
15 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c)
17 object SPIPinsFromPort {
19 def apply[T <: Pin](pins: SPISignals[T], spi: SPIPortIO, clock: Clock, reset: Bool,
20 syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
22 withClockAndReset(clock, reset) {
23 pins.sck.outputPin(spi.sck, ds = driveStrength)
25 (pins.dq zip spi.dq).foreach {case (p, s) =>
26 p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
29 s.i := ShiftRegister(p.i.ival, syncStages)
32 (pins.cs zip spi.cs) foreach { case (c, s) =>
33 c.outputPin(s, ds = driveStrength)