src/openpower/decoder/isa/test_caller_svp64_crops.py

   1 """Implementation of FORTRAN MAXLOC SVP64
   2 Copyright (C) 2022,2023 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 Licensed under the LGPLv3+
   4 Funded by NLnet NGI-ASSURE under EU grant agreement No 957073.
   5 * https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA
   6 * https://bugs.libre-soc.org/show_bug.cgi?id=676
   7 * https://libre-soc.org/openpower/sv/cookbook/fortran_maxloc/
   8 """
   9
  10 import unittest
  11 from copy import deepcopy
  12
  13 from nmutil.formaltest import FHDLTestCase
  14 from openpower.decoder.isa.caller import SVP64State
  15 from openpower.decoder.isa.test_caller import run_tst
  16 from openpower.decoder.selectable_int import SelectableInt
  17 from openpower.simulator.program import Program
  18 from openpower.insndb.asm import SVP64Asm
  19 from openpower.util import log
  20 from openpower.decoder.isa.maxloc import m2
  21
  22
  23 class CRfield:
  24     def __init__(self, value=0):
  25         self.lt = (value>>3) & 0b1
  26         self.gt = (value>>2) & 0b1
  27         self.eq = (value>>1) & 0b1
  28     def __repr__(self):
  29         return "<lt %d gt %d eq %d>" % (self.lt, self.gt, self.eq)
  30     def __int__(self):
  31         return (self.lt<<3) | (self.gt<<2) | (self.eq<<1)
  32
  33
  34 class CR_Ops_TestCase(FHDLTestCase):
  35
  36     def _check_regs(self, sim, expected):
  37         for i in range(32):
  38             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  39
  40     def test_sv_creqv_1(self):
  41         self.sv_creqv([0b11,0b100])
  42
  43     def tst_sv_maxloc_2(self):
  44         self.sv_maxloc([3,4,1,5])
  45
  46     def tst_sv_maxloc_3(self):
  47         self.sv_maxloc([2,9,8,0])
  48
  49     def tst_sv_maxloc_4(self):
  50         self.sv_maxloc([2,1,3,0])
  51
  52     def sv_creqv(self, ra):
  53         """
  54         """
  55
  56         lst = SVP64Asm([
  57                 "sv.creqv *19,*16,*16",
  58                         ])
  59         lst = list(lst)
  60
  61         # SVSTATE
  62         svstate = SVP64State()
  63         vl = 2
  64         svstate.vl = vl  # VL
  65         svstate.maxvl = vl  # MAXVL
  66         print("SVSTATE", bin(svstate.asint()))
  67
  68         gprs = [0] * 32
  69
  70         crs = []
  71         cr_res = []
  72         cr = 0
  73         for idx, crf in enumerate(ra):
  74             crs .append(CRfield(crf))
  75             cr |= crf << ((7-idx)*4)
  76         res = deepcopy(gprs)
  77
  78         #expected_vl, expected_cr = sv_maxu(res, cr_res, vl, 10, 4, 4)
  79         #log("sv_maxu", expected_vl, cr_res)
  80
  81         with Program(lst, bigendian=False) as program:
  82             sim = self.run_tst_program(program, initial_regs=gprs,
  83                                        initial_cr=cr,
  84                                        svstate=svstate)
  85             for i in range(8):
  86                 crf = sim.crl[i].get_range().value
  87                 log("crf", i, bin(crf))
  88
  89             # confirm that the results are as expected
  90             return
  91
  92             for i, v in enumerate(cr_res[:vl]):
  93                 crf = sim.crl[i].get_range().value
  94                 log("crf", i, res[i], bin(crf), bin(int(v)))
  95                 self.assertEqual(crf, int(v))
  96
  97     def run_tst_program(self, prog, initial_regs=None,
  98                         svstate=None,
  99                         initial_mem=None,
 100                         initial_cr=None):
 101         if initial_regs is None:
 102             initial_regs = [0] * 32
 103         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 104                             initial_cr=initial_cr,
 105                             svstate=svstate)
 106
 107         print("GPRs")
 108         simulator.gpr.dump()
 109         print("FPRs")
 110         simulator.fpr.dump()
 111
 112         return simulator
 113
 114
 115 if __name__ == "__main__":
 116     unittest.main()