src/openpower/decoder/isa/test_caller_svp64_maxloc.py

   1 """Implementation of FORTRAN MAXLOC SVP64
   2 Copyright (C) 2022,2023 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 Licensed under the LGPLv3+
   4 Funded by NLnet NGI-ASSURE under EU grant agreement No 957073.
   5 * https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA
   6 * https://bugs.libre-soc.org/show_bug.cgi?id=676
   7 * https://libre-soc.org/openpower/sv/cookbook/fortran_maxloc/
   8 """
   9
  10 import unittest
  11 from copy import deepcopy
  12
  13 from nmutil.formaltest import FHDLTestCase
  14 from openpower.decoder.isa.caller import SVP64State
  15 from openpower.decoder.isa.test_caller import run_tst
  16 from openpower.decoder.selectable_int import SelectableInt
  17 from openpower.simulator.program import Program
  18 from openpower.insndb.asm import SVP64Asm
  19 from openpower.util import log
  20
  21
  22
  23 # example sv.cmpi/ff=lt 0, 1, *10, 5
  24 # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
  25 def sv_maxu(gpr, CR, vl, ra, rb, rt):
  26     i = 0
  27     while i < vl:
  28         CR[0] = cmpd(gpr[ra+i], gpr[rb])
  29         log("sv_maxss test", i, gpr[ra + i], gpr[rb], CR[0], int(CR[0]))
  30         gpr[rt] = gpr[ra+i] if CR[0].lt else gpr[rb]
  31         if not CR[0].gt:
  32             break
  33         i += 1
  34     return i # new VL
  35
  36
  37 class DDFFirstTestCase(FHDLTestCase):
  38
  39     def _check_regs(self, sim, expected):
  40         for i in range(32):
  41             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  42
  43     def test_sv_maxloc_1(self):
  44         self.sv_maxloc([1,2,3,4])
  45
  46     def tst_sv_maxloc_2(self):
  47         self.sv_maxloc([3,4,1,0])
  48
  49     def tst_sv_maxloc_3(self):
  50         self.sv_maxloc([2,9,8,0])
  51
  52     def tst_sv_maxloc_4(self):
  53         self.sv_maxloc([2,1,3,0])
  54
  55     def sv_maxloc(self, ra):
  56         lst = SVP64Asm(["sv.minmax./ff=le 4, *10, 4, 1" # scalar RB=RT
  57                         ])
  58         lst = list(lst)
  59
  60         # SVSTATE
  61         svstate = SVP64State()
  62         vl = len(ra)  # VL is length of array ra
  63         svstate.vl = vl  # VL
  64         svstate.maxvl = vl  # MAXVL
  65         print("SVSTATE", bin(svstate.asint()))
  66
  67         gprs = [0] * 32
  68         gprs[4] =  rb # (RT&RB) accumulator in r4
  69         for i, ra in enumerate(ra): # vector in ra starts at r10
  70             gprs[10+i] = ra
  71             log("maxu ddff", i, gprs[10+i])
  72
  73         cr_res = [0]*8
  74         res = deepcopy(gprs)
  75
  76         expected_vl = sv_maxu(res, cr_res, vl, 10, 4, 4)
  77         log("sv_maxu", expected_vl, cr_res)
  78
  79         with Program(lst, bigendian=False) as program:
  80             sim = self.run_tst_program(program, initial_regs=gprs,
  81                                        svstate=svstate)
  82             for i in range(4):
  83                 val = sim.gpr(i).value
  84                 res.append(val)
  85                 cr_res.append(0)
  86                 log("i", i, val)
  87             # confirm that the results are as expected
  88
  89             for i, v in enumerate(cr_res[:vl]):
  90                 crf = sim.crl[i].get_range().value
  91                 log("crf", i, res[i], bin(crf), bin(int(v)))
  92                 self.assertEqual(crf, int(v))
  93
  94             for i, v in enumerate(res):
  95                 self.assertEqual(v, res[i])
  96
  97             self.assertEqual(sim.svstate.vl, expected_vl)
  98             self.assertEqual(sim.svstate.maxvl, 4)
  99             self.assertEqual(sim.svstate.srcstep, 0)
 100             self.assertEqual(sim.svstate.dststep, 0)
 101
 102     def run_tst_program(self, prog, initial_regs=None,
 103                         svstate=None,
 104                         initial_mem=None,
 105                         initial_fprs=None):
 106         if initial_regs is None:
 107             initial_regs = [0] * 32
 108         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 109                             initial_fprs=initial_fprs,
 110                             svstate=svstate)
 111
 112         print("GPRs")
 113         simulator.gpr.dump()
 114         print("FPRs")
 115         simulator.fpr.dump()
 116
 117         return simulator
 118
 119
 120 if __name__ == "__main__":
 121     unittest.main()