1 import collections
as _collections
2 import contextlib
as _contextlib
4 import dataclasses
as _dataclasses
6 import functools
as _functools
7 import inspect
as _inspect
9 import operator
as _operator
10 import pathlib
as _pathlib
12 import types
as _types
13 import typing
as _typing
15 import mdis
.dispatcher
19 from functools
import cached_property
21 from cached_property
import cached_property
23 from openpower
.decoder
.power_enums
import (
24 Function
as _Function
,
31 CRIn2Sel
as _CRIn2Sel
,
32 CROutSel
as _CROutSel
,
34 LDSTMode
as _LDSTMode
,
39 SVMaskSrc
as _SVMaskSrc
,
46 SVP64SubVL
as _SVP64SubVL
,
47 SVP64Pred
as _SVP64Pred
,
48 SVP64PredMode
as _SVP64PredMode
,
49 SVP64Width
as _SVP64Width
,
51 from openpower
.decoder
.selectable_int
import (
52 SelectableInt
as _SelectableInt
,
53 selectconcat
as _selectconcat
,
55 from openpower
.decoder
.power_fields
import (
58 DecodeFields
as _DecodeFields
,
60 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
63 class DataclassMeta(type):
64 def __new__(metacls
, name
, bases
, ns
):
65 cls
= super().__new
__(metacls
, name
, bases
, ns
)
66 return _dataclasses
.dataclass(cls
, eq
=True, frozen
=True)
69 class Dataclass(metaclass
=DataclassMeta
):
73 @_functools.total_ordering
74 class Style(_enum
.Enum
):
78 VERBOSE
= _enum
.auto()
80 def __lt__(self
, other
):
81 if not isinstance(other
, self
.__class
__):
83 return (self
.value
< other
.value
)
86 def dataclass(cls
, record
, keymap
=None, typemap
=None):
90 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
92 def transform(key_value
):
93 (key
, value
) = key_value
94 key
= keymap
.get(key
, key
)
95 hook
= typemap
.get(key
, lambda value
: value
)
96 if hook
is bool and value
in ("", "0"):
102 record
= dict(map(transform
, record
.items()))
103 for key
in frozenset(record
.keys()):
104 if record
[key
] == "":
110 @_functools.total_ordering
113 def __new__(cls
, value
):
114 if isinstance(value
, str):
115 value
= int(value
, 0)
116 if not isinstance(value
, int):
117 raise ValueError(value
)
119 if value
.bit_length() > 64:
120 raise ValueError(value
)
122 return super().__new
__(cls
, value
)
125 return self
.__repr
__()
128 return f
"{self:0{self.bit_length()}b}"
130 def bit_length(self
):
131 if super().bit_length() > 32:
135 class Value(Integer
):
141 def __init__(self
, value
, mask
):
144 return super().__init
__()
154 def __lt__(self
, other
):
155 if not isinstance(other
, Opcode
):
156 return NotImplemented
157 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
160 return (self
.value
& self
.mask
)
163 return int(self
).__index
__()
166 def pattern(value
, mask
, bit_length
):
167 for bit
in range(bit_length
):
168 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
170 elif (value
& (1 << (bit_length
- bit
- 1))):
175 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
177 def match(self
, key
):
178 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
181 @_functools.total_ordering
182 class IntegerOpcode(Opcode
):
183 def __init__(self
, value
):
184 if value
.startswith("0b"):
185 mask
= int(("1" * len(value
[2:])), 2)
189 value
= Opcode
.Value(value
)
190 mask
= Opcode
.Mask(mask
)
192 return super().__init
__(value
=value
, mask
=mask
)
195 @_functools.total_ordering
196 class PatternOpcode(Opcode
):
197 def __init__(self
, pattern
):
198 if not isinstance(pattern
, str):
199 raise ValueError(pattern
)
201 (value
, mask
) = (0, 0)
202 for symbol
in pattern
:
203 if symbol
not in {"0", "1", "-"}:
204 raise ValueError(pattern
)
205 value |
= (symbol
== "1")
206 mask |
= (symbol
!= "-")
212 value
= Opcode
.Value(value
)
213 mask
= Opcode
.Mask(mask
)
215 return super().__init
__(value
=value
, mask
=mask
)
218 class PPCRecord(Dataclass
):
219 class FlagsMeta(type):
234 class Flags(tuple, metaclass
=FlagsMeta
):
235 def __new__(cls
, flags
=frozenset()):
236 flags
= frozenset(flags
)
237 diff
= (flags
- frozenset(cls
))
239 raise ValueError(flags
)
240 return super().__new
__(cls
, sorted(flags
))
244 flags
: Flags
= Flags()
246 function
: _Function
= _Function
.NONE
247 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
248 in1
: _In1Sel
= _In1Sel
.NONE
249 in2
: _In2Sel
= _In2Sel
.NONE
250 in3
: _In3Sel
= _In3Sel
.NONE
251 out
: _OutSel
= _OutSel
.NONE
252 cr_in
: _CRInSel
= _CRInSel
.NONE
253 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
254 cr_out
: _CROutSel
= _CROutSel
.NONE
255 cry_in
: _CryIn
= _CryIn
.ZERO
256 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
257 upd
: _LDSTMode
= _LDSTMode
.NONE
258 Rc
: _RCOE
= _RCOE
.NONE
259 form
: _Form
= _Form
.NONE
265 "internal op": "intop",
269 "ldst len": "ldst_len",
271 "CONDITIONS": "conditions",
274 def __lt__(self
, other
):
275 if not isinstance(other
, self
.__class
__):
276 return NotImplemented
277 lhs
= (self
.opcode
, self
.comment
)
278 rhs
= (other
.opcode
, other
.comment
)
282 def CSV(cls
, record
, opcode_cls
):
283 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
284 typemap
["opcode"] = opcode_cls
286 if record
["CR in"] == "BA_BB":
287 record
["cr_in"] = "BA"
288 record
["cr_in2"] = "BB"
292 for flag
in frozenset(PPCRecord
.Flags
):
293 if bool(record
.pop(flag
, "")):
295 record
["flags"] = PPCRecord
.Flags(flags
)
297 return dataclass(cls
, record
,
298 keymap
=PPCRecord
.__KEYMAP
,
303 return frozenset(self
.comment
.split("=")[-1].split("/"))
306 class PPCMultiRecord(tuple):
307 def __getattr__(self
, attr
):
310 raise AttributeError(attr
)
311 return getattr(self
[0], attr
)
314 class SVP64Record(Dataclass
):
315 class ExtraMap(tuple):
317 @_dataclasses.dataclass(eq
=True, frozen
=True)
319 seltype
: _SelType
= _SelType
.NONE
320 reg
: _Reg
= _Reg
.NONE
323 return f
"{self.seltype.value}:{self.reg.name}"
325 def __new__(cls
, value
="0"):
326 if isinstance(value
, str):
327 def transform(value
):
328 (seltype
, reg
) = value
.split(":")
329 seltype
= _SelType(seltype
)
331 return cls
.Entry(seltype
=seltype
, reg
=reg
)
336 value
= map(transform
, value
.split(";"))
338 return super().__new
__(cls
, value
)
341 return repr(list(self
))
343 def __new__(cls
, value
=tuple()):
347 return super().__new
__(cls
, map(cls
.Extra
, value
))
350 return repr({index
:self
[index
] for index
in range(0, 4)})
353 ptype
: _SVPType
= _SVPType
.NONE
354 etype
: _SVEType
= _SVEType
.NONE
355 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
356 in1
: _In1Sel
= _In1Sel
.NONE
357 in2
: _In2Sel
= _In2Sel
.NONE
358 in3
: _In3Sel
= _In3Sel
.NONE
359 out
: _OutSel
= _OutSel
.NONE
360 out2
: _OutSel
= _OutSel
.NONE
361 cr_in
: _CRInSel
= _CRInSel
.NONE
362 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
363 cr_out
: _CROutSel
= _CROutSel
.NONE
364 extra
: ExtraMap
= ExtraMap()
366 mode
: _SVMode
= _SVMode
.NORMAL
370 "CONDITIONS": "conditions",
379 def CSV(cls
, record
):
380 record
["insn"] = record
["insn"].split("=")[-1]
382 for key
in frozenset({
383 "in1", "in2", "in3", "CR in",
384 "out", "out2", "CR out",
390 if record
["CR in"] == "BA_BB":
391 record
["cr_in"] = "BA"
392 record
["cr_in2"] = "BB"
394 elif record
["CR in"] == "BFA_BFB_BF":
395 record
["cr_in"] = "BFA"
396 record
["cr_in2"] = "BFB"
397 #record["cr_out"] = "BF" # only use BFA_BFB_BF when BF is a dest
401 for idx
in range(0, 4):
402 extra
.append(record
.pop(f
"{idx}"))
404 record
["extra"] = cls
.ExtraMap(extra
)
406 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
411 "in1", "in2", "in3", "cr_in", "cr_in2",
412 "out", "out2", "cr_out",
427 for index
in range(0, 4):
428 for entry
in self
.extra
[index
]:
429 extras
[entry
.seltype
][entry
.reg
] = idxmap
[index
]
431 for (seltype
, regs
) in extras
.items():
432 idx
= regs
.get(reg
, _SVExtra
.NONE
)
433 if idx
is not _SVExtra
.NONE
:
434 yield (reg
, seltype
, idx
)
441 # has the word "in", it is a SelType.SRC "out" -> DST
442 # in1/2/3 and CR in are SRC, and must match only against "s:NN"
443 # out/out1 and CR out are DST, and must match only against "d:NN"
444 keytype
= _SelType
.SRC
if ("in" in key
) else _SelType
.DST
445 sel
= sels
[key
] = getattr(self
, key
)
446 reg
= regs
[key
] = _Reg(sel
)
447 seltypes
[key
] = _SelType
.NONE
448 idxs
[key
] = _SVExtra
.NONE
449 for (reg
, seltype
, idx
) in extra(reg
.alias
):
450 if keytype
!= seltype
: # only check SRC-to-SRC and DST-to-DST
452 if idx
!= idxs
[key
] and idxs
[key
] is not _SVExtra
.NONE
:
453 raise ValueError(idx
)
456 seltypes
[key
] = seltype
458 if sels
["cr_in"] is _CRInSel
.BA_BB
:
459 sels
["cr_in"] = _CRIn2Sel
.BA
460 sels
["cr_in2"] = _CRIn2Sel
.BB
461 idxs
["cr_in2"] = idxs
["cr_in"]
462 for key
in ("cr_in", "cr_in2"):
463 regs
[key
] = _Reg(sels
[key
])
464 seltype
[key
] = _SelType
.SRC
466 # should only be used when BF is also a destination
467 if sels
["cr_in"] is _CRInSel
.BFA_BFB_BF
:
468 sels
["cr_in"] = _CRIn2Sel
.BFA
469 sels
["cr_in2"] = _CRIn2Sel
.BFB
470 idxs
["cr_in2"] = idxs
["cr_in"]
471 for key
in ("cr_in", "cr_in2"):
472 regs
[key
] = _Reg(sels
[key
])
473 seltype
[key
] = _SelType
.SRC
480 "seltype": seltypes
[key
],
484 return _types
.MappingProxyType(records
)
486 extra_idx_in1
= property(lambda self
: self
.extras
["in1"]["idx"])
487 extra_idx_in2
= property(lambda self
: self
.extras
["in2"]["idx"])
488 extra_idx_in3
= property(lambda self
: self
.extras
["in3"]["idx"])
489 extra_idx_out
= property(lambda self
: self
.extras
["out"]["idx"])
490 extra_idx_out2
= property(lambda self
: self
.extras
["out2"]["idx"])
491 extra_idx_cr_in
= property(lambda self
: self
.extras
["cr_in"]["idx"])
492 extra_idx_cr_in2
= property(lambda self
: self
.extras
["cr_in2"]["idx"])
493 extra_idx_cr_out
= property(lambda self
: self
.extras
["cr_out"]["idx"])
498 for idx
in range(0, 4):
499 for entry
in self
.extra
[idx
]:
500 if entry
.seltype
is _SelType
.DST
:
501 if extra
is not None:
502 raise ValueError(self
.svp64
)
506 if _RegType(extra
.reg
) not in (_RegType
.CR_3BIT
, _RegType
.CR_5BIT
):
507 raise ValueError(self
.svp64
)
512 def extra_CR_3bit(self
):
513 return (_RegType(self
.extra_CR
.reg
) is _RegType
.CR_3BIT
)
516 class Section(Dataclass
):
517 class Path(type(_pathlib
.Path("."))):
521 def __init__(self
, value
=(0, 32)):
522 if isinstance(value
, str):
523 (start
, end
) = map(int, value
.split(":"))
526 if start
< 0 or end
< 0 or start
>= end
:
527 raise ValueError(value
)
532 return super().__init
__()
535 return (self
.__end
- self
.__start
+ 1)
538 return f
"[{self.__start}:{self.__end}]"
541 yield from range(self
.start
, (self
.end
+ 1))
543 def __reversed__(self
):
544 return tuple(reversed(tuple(self
)))
554 class Mode(_enum
.Enum
):
555 INTEGER
= _enum
.auto()
556 PATTERN
= _enum
.auto()
559 def _missing_(cls
, value
):
560 if isinstance(value
, str):
561 return cls
[value
.upper()]
562 return super()._missing
_(value
)
565 def __new__(cls
, value
=None):
566 if isinstance(value
, str):
567 if value
.upper() == "NONE":
570 value
= int(value
, 0)
574 return super().__new
__(cls
, value
)
580 return (bin(self
) if self
else "None")
582 class Opcode(IntegerOpcode
):
585 @_functools.total_ordering
586 class Priority(_enum
.Enum
):
592 def _missing_(cls
, value
):
593 if isinstance(value
, str):
594 value
= value
.upper()
598 return super()._missing
_(value
)
600 def __lt__(self
, other
):
601 if not isinstance(other
, self
.__class
__):
602 return NotImplemented
604 # NOTE: the order is inversed, LOW < NORMAL < HIGH
605 return (self
.value
> other
.value
)
611 opcode
: Opcode
= None
612 priority
: Priority
= Priority
.NORMAL
614 def __lt__(self
, other
):
615 if not isinstance(other
, self
.__class
__):
616 return NotImplemented
617 return (self
.priority
< other
.priority
)
620 def CSV(cls
, record
):
621 keymap
= {"path": "csv"}
622 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
623 if record
["opcode"] == "NONE":
624 typemap
["opcode"] = lambda _
: None
626 return dataclass(cls
, record
, typemap
=typemap
, keymap
=keymap
)
630 def __init__(self
, items
):
631 if isinstance(items
, dict):
632 items
= items
.items()
635 (name
, bitrange
) = item
636 return (name
, tuple(bitrange
.values()))
638 mapping
= dict(map(transform
, items
))
640 return super().__init
__(mapping
)
643 return hash(tuple(sorted(self
.items())))
646 yield from self
.__mapping
.items()
649 class Operands(dict):
661 def __init__(self
, insn
, operands
):
663 "b": {"target_addr": TargetAddrOperandLI
},
664 "ba": {"target_addr": TargetAddrOperandLI
},
665 "bl": {"target_addr": TargetAddrOperandLI
},
666 "bla": {"target_addr": TargetAddrOperandLI
},
667 "bc": {"target_addr": TargetAddrOperandBD
},
668 "bca": {"target_addr": TargetAddrOperandBD
},
669 "bcl": {"target_addr": TargetAddrOperandBD
},
670 "bcla": {"target_addr": TargetAddrOperandBD
},
671 "addpcis": {"D": DOperandDX
},
672 "fishmv": {"D": DOperandDX
},
673 "fmvis": {"D": DOperandDX
},
676 "SVi": NonZeroOperand
,
677 "SVd": NonZeroOperand
,
678 "SVxd": NonZeroOperand
,
679 "SVyd": NonZeroOperand
,
680 "SVzd": NonZeroOperand
,
682 "D": SignedImmediateOperand
,
686 "SIM": SignedOperand
,
687 "SVD": SignedOperand
,
688 "SVDS": SignedOperand
,
689 "RSp": GPRPairOperand
,
690 "RTp": GPRPairOperand
,
691 "FRAp": FPRPairOperand
,
692 "FRBp": FPRPairOperand
,
693 "FRSp": FPRPairOperand
,
694 "FRTp": FPRPairOperand
,
696 custom_immediates
= {
702 for operand
in operands
:
706 (name
, value
) = operand
.split("=")
707 mapping
[name
] = (StaticOperand
, (
709 ("value", int(value
)),
713 if name
.endswith(")"):
714 name
= name
.replace("(", " ").replace(")", "")
715 (imm_name
, _
, name
) = name
.partition(" ")
719 if imm_name
is not None:
720 imm_cls
= custom_immediates
.get(imm_name
, ImmediateOperand
)
722 if insn
in custom_insns
and name
in custom_insns
[insn
]:
723 cls
= custom_insns
[insn
][name
]
724 elif name
in custom_fields
:
725 cls
= custom_fields
[name
]
726 elif name
in _Reg
.__members
__:
728 if reg
in self
.__class
__.__GPR
_PAIRS
:
730 elif reg
in self
.__class
__.__FPR
_PAIRS
:
733 regtype
= _RegType
[name
]
734 if regtype
is _RegType
.GPR
:
736 elif regtype
is _RegType
.FPR
:
738 elif regtype
is _RegType
.CR_3BIT
:
740 elif regtype
is _RegType
.CR_5BIT
:
743 if imm_name
is not None:
744 mapping
[imm_name
] = (imm_cls
, (
747 mapping
[name
] = (cls
, (
751 return super().__init
__(mapping
)
754 for (cls
, kwargs
) in self
.values():
755 yield (cls
, dict(kwargs
))
758 return hash(tuple(sorted(self
.items())))
762 return tuple(filter(lambda pair
: issubclass(pair
[0], StaticOperand
), self
))
766 return tuple(filter(lambda pair
: issubclass(pair
[0], DynamicOperand
), self
))
769 class Arguments(tuple):
770 def __new__(cls
, record
, arguments
, operands
):
771 operands
= iter(tuple(operands
))
772 arguments
= iter(tuple(arguments
))
777 operand
= next(operands
)
778 except StopIteration:
782 argument
= next(arguments
)
783 except StopIteration:
784 raise ValueError("operands count mismatch")
786 if isinstance(operand
, ImmediateOperand
):
787 argument
= argument
.replace("(", " ").replace(")", "")
788 (imm_argument
, _
, argument
) = argument
.partition(" ")
790 (imm_operand
, operand
) = (operand
, next(operands
))
791 except StopIteration:
792 raise ValueError("operands count mismatch")
793 items
.append((imm_argument
, imm_operand
))
794 items
.append((argument
, operand
))
798 except StopIteration:
801 raise ValueError("operands count mismatch")
803 return super().__new
__(cls
, items
)
810 class MarkdownRecord(Dataclass
):
815 @_functools.total_ordering
816 class Record(Dataclass
):
822 svp64
: SVP64Record
= None
826 if self
.svp64
is not None:
827 return self
.svp64
.extras
829 return _types
.MappingProxyType({})
833 return self
.mdwn
.pcode
835 def __lt__(self
, other
):
836 if not isinstance(other
, Record
):
837 return NotImplemented
838 lhs
= (min(self
.opcodes
), self
.name
)
839 rhs
= (min(other
.opcodes
), other
.name
)
844 return (self
.static_operands
+ self
.dynamic_operands
)
847 def static_operands(self
):
849 operands
.append(POStaticOperand(record
=self
, value
=self
.PO
))
851 operands
.append(XOStaticOperand(
853 value
=ppc
.opcode
.value
,
854 span
=self
.section
.bitsel
,
856 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
857 operands
.append(cls(record
=self
, **kwargs
))
858 return tuple(operands
)
861 def dynamic_operands(self
):
863 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
864 operands
.append(cls(record
=self
, **kwargs
))
865 return tuple(operands
)
870 return int("".join(str(int(mapping
[bit
])) \
871 for bit
in sorted(mapping
)), 2)
873 def PO_XO(value
, mask
, opcode
, bits
):
876 for (src
, dst
) in enumerate(reversed(bits
)):
877 value
[dst
] = ((opcode
.value
& (1 << src
)) != 0)
878 mask
[dst
] = ((opcode
.mask
& (1 << src
)) != 0)
881 def PO(value
, mask
, opcode
, bits
):
882 return PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
884 def XO(value
, mask
, opcode
, bits
):
885 (value
, mask
) = PO_XO(value
=value
, mask
=mask
,
886 opcode
=opcode
, bits
=bits
)
887 for (op_cls
, op_kwargs
) in self
.mdwn
.operands
.static
:
888 operand
= op_cls(record
=self
, **op_kwargs
)
889 for (src
, dst
) in enumerate(reversed(operand
.span
)):
890 value
[dst
] = ((operand
.value
& (1 << src
)) != 0)
895 value
= {bit
:False for bit
in range(32)}
896 mask
= {bit
:False for bit
in range(32)}
897 if self
.section
.opcode
is not None:
898 (value
, mask
) = PO(value
=value
, mask
=mask
,
899 opcode
=self
.section
.opcode
, bits
=range(0, 6))
901 pairs
.append(XO(value
=value
, mask
=mask
,
902 opcode
=ppc
.opcode
, bits
=self
.section
.bitsel
))
905 for (value
, mask
) in pairs
:
906 value
= Opcode
.Value(binary(value
))
907 mask
= Opcode
.Mask(binary(mask
))
908 result
.append(Opcode(value
=value
, mask
=mask
))
914 opcode
= self
.section
.opcode
916 opcode
= self
.ppc
[0].opcode
917 if isinstance(opcode
, PatternOpcode
):
918 value
= int(opcode
.value
)
919 bits
= opcode
.value
.bit_length()
920 return int(_SelectableInt(value
=value
, bits
=bits
)[0:6])
922 return int(opcode
.value
)
926 return tuple(ppc
.opcode
for ppc
in self
.ppc
)
928 def match(self
, key
):
929 for opcode
in self
.opcodes
:
930 if opcode
.match(key
):
937 return self
.svp64
.mode
957 if self
.svp64
is None:
963 return self
.ppc
.cr_in
967 return self
.ppc
.cr_in2
971 return self
.ppc
.cr_out
973 ptype
= property(lambda self
: self
.svp64
.ptype
)
974 etype
= property(lambda self
: self
.svp64
.etype
)
976 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
977 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
978 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
979 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
980 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
981 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
982 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
983 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
985 def __contains__(self
, key
):
986 return self
.mdwn
.operands
.__contains
__(key
)
988 def __getitem__(self
, key
):
989 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
990 return cls(record
=self
, **dict(kwargs
))
996 return self
["Rc"].value
1000 def __init__(self
, record
, name
):
1001 self
.__record
= record
1005 yield ("record", self
.record
)
1006 yield ("name", self
.__name
)
1009 return f
"{self.__class__.__name__}({self.name})"
1017 return self
.__record
1021 return self
.record
.fields
[self
.name
]
1023 def assemble(self
, insn
):
1024 raise NotImplementedError()
1026 def disassemble(self
, insn
,
1027 style
=Style
.NORMAL
, indent
=""):
1028 raise NotImplementedError()
1031 class DynamicOperand(Operand
):
1032 def assemble(self
, insn
, value
):
1034 if isinstance(value
, str):
1035 value
= int(value
, 0)
1037 raise ValueError("signed operands not allowed")
1040 def disassemble(self
, insn
,
1041 style
=Style
.NORMAL
, indent
=""):
1045 if style
>= Style
.VERBOSE
:
1046 span
= map(str, span
)
1047 yield f
"{indent}{self.name}"
1048 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1049 yield f
"{indent}{indent}{', '.join(span)}"
1051 yield str(int(value
))
1054 class SignedOperand(DynamicOperand
):
1055 def assemble(self
, insn
, value
):
1056 if isinstance(value
, str):
1057 value
= int(value
, 0)
1058 return super().assemble(value
=value
, insn
=insn
)
1060 def assemble(self
, insn
, value
):
1062 if isinstance(value
, str):
1063 value
= int(value
, 0)
1066 def disassemble(self
, insn
,
1067 style
=Style
.NORMAL
, indent
=""):
1069 value
= insn
[span
].to_signed_int()
1070 sign
= "-" if (value
< 0) else ""
1073 if style
>= Style
.VERBOSE
:
1074 span
= map(str, span
)
1075 yield f
"{indent}{self.name}"
1076 yield f
"{indent}{indent}{sign}{value}"
1077 yield f
"{indent}{indent}{', '.join(span)}"
1079 yield f
"{sign}{value}"
1082 class StaticOperand(Operand
):
1083 def __init__(self
, record
, name
, value
):
1084 self
.__value
= value
1085 return super().__init
__(record
=record
, name
=name
)
1088 yield ("value", self
.__value
)
1089 yield from super().__iter
__()
1092 return f
"{self.__class__.__name__}({self.name}, value={self.value})"
1098 def assemble(self
, insn
):
1099 insn
[self
.span
] = self
.value
1101 def disassemble(self
, insn
,
1102 style
=Style
.NORMAL
, indent
=""):
1106 if style
>= Style
.VERBOSE
:
1107 span
= map(str, span
)
1108 yield f
"{indent}{self.name}"
1109 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1110 yield f
"{indent}{indent}{', '.join(span)}"
1112 yield str(int(value
))
1115 class SpanStaticOperand(StaticOperand
):
1116 def __init__(self
, record
, name
, value
, span
):
1117 self
.__span
= tuple(span
)
1118 return super().__init
__(record
=record
, name
=name
, value
=value
)
1121 yield ("span", self
.__span
)
1122 yield from super().__iter
__()
1129 class POStaticOperand(SpanStaticOperand
):
1130 def __init__(self
, record
, value
):
1131 return super().__init
__(record
=record
, name
="PO",
1132 value
=value
, span
=range(0, 6))
1135 for (key
, value
) in super().__iter
__():
1136 if key
not in {"name", "span"}:
1140 class XOStaticOperand(SpanStaticOperand
):
1141 def __init__(self
, record
, value
, span
):
1142 bits
= record
.section
.bitsel
1143 value
= _SelectableInt(value
=value
, bits
=len(bits
))
1144 span
= dict(zip(bits
, range(len(bits
))))
1145 span_rev
= {value
:key
for (key
, value
) in span
.items()}
1147 # This part is tricky: we cannot use record.operands,
1148 # as this code is called by record.static_operands method.
1149 for (cls
, kwargs
) in record
.mdwn
.operands
:
1150 operand
= cls(record
=record
, **kwargs
)
1151 for idx
in operand
.span
:
1152 rev
= span
.pop(idx
, None)
1154 span_rev
.pop(rev
, None)
1156 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1157 span
= tuple(span
.keys())
1159 return super().__init
__(record
=record
, name
="XO",
1160 value
=value
, span
=span
)
1163 for (key
, value
) in super().__iter
__():
1164 if key
not in {"name"}:
1168 class ImmediateOperand(DynamicOperand
):
1172 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1176 class NonZeroOperand(DynamicOperand
):
1177 def assemble(self
, insn
, value
):
1178 if isinstance(value
, str):
1179 value
= int(value
, 0)
1180 if not isinstance(value
, int):
1181 raise ValueError("non-integer operand")
1183 raise ValueError("non-zero operand")
1185 return super().assemble(value
=value
, insn
=insn
)
1187 def disassemble(self
, insn
,
1188 style
=Style
.NORMAL
, indent
=""):
1192 if style
>= Style
.VERBOSE
:
1193 span
= map(str, span
)
1194 yield f
"{indent}{self.name}"
1195 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1196 yield f
"{indent}{indent}{', '.join(span)}"
1198 yield str(int(value
) + 1)
1201 class ExtendableOperand(DynamicOperand
):
1202 def sv_spec_enter(self
, value
, span
):
1203 return (value
, span
)
1205 def sv_spec(self
, insn
):
1209 span
= tuple(map(str, span
))
1211 if isinstance(insn
, SVP64Instruction
):
1212 (origin_value
, origin_span
) = (value
, span
)
1213 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1215 for extra_idx
in self
.extra_idx
:
1216 if self
.record
.etype
is _SVEType
.EXTRA3
:
1217 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1218 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1219 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1221 raise ValueError(self
.record
.etype
)
1224 vector
= bool(spec
[0])
1225 spec_span
= spec
.__class
__
1226 if self
.record
.etype
is _SVEType
.EXTRA3
:
1227 spec_span
= tuple(map(str, spec_span
[1, 2]))
1229 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1230 spec_span
= tuple(map(str, spec_span
[1,]))
1231 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1234 spec_span
= (spec_span
+ ("{0}",))
1236 spec_span
= (("{0}",) + spec_span
)
1238 raise ValueError(self
.record
.etype
)
1240 vector_shift
= (2 + (5 - value
.bits
))
1241 scalar_shift
= value
.bits
1242 spec_shift
= (5 - value
.bits
)
1244 bits
= (len(span
) + len(spec_span
))
1245 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1246 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1248 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1249 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1251 value
= ((spec
<< scalar_shift
) | value
)
1252 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1254 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1255 origin_value
=origin_value
, origin_span
=origin_span
)
1257 return (vector
, value
, span
)
1259 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1260 return (value
, span
)
1263 def extra_idx(self
):
1264 for (key
, record
) in self
.record
.svp64
.extras
.items():
1265 if record
["reg"].alias
is self
.extra_reg
.alias
:
1269 def extra_reg(self
):
1270 return _Reg(self
.name
)
1272 def remap(self
, value
, vector
):
1273 raise NotImplementedError()
1275 def assemble(self
, value
, insn
, prefix
):
1278 if isinstance(value
, str):
1279 value
= value
.lower()
1280 if value
.startswith("%"):
1282 if value
.startswith("*"):
1283 if not isinstance(insn
, SVP64Instruction
):
1284 raise ValueError(value
)
1287 if value
.startswith(prefix
):
1288 if (self
.extra_reg
.or_zero
and (value
== f
"{prefix}0")):
1289 raise ValueError(value
)
1290 value
= value
[len(prefix
):]
1291 value
= int(value
, 0)
1293 if isinstance(insn
, SVP64Instruction
):
1294 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1296 for extra_idx
in self
.extra_idx
:
1297 if self
.record
.etype
is _SVEType
.EXTRA3
:
1298 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1299 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1300 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1302 raise ValueError(self
.record
.etype
)
1304 return super().assemble(value
=value
, insn
=insn
)
1306 def disassemble(self
, insn
,
1307 style
=Style
.NORMAL
, prefix
="", indent
=""):
1308 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1310 if (self
.extra_reg
.or_zero
and (value
== 0)):
1313 if style
>= Style
.VERBOSE
:
1314 mode
= "vector" if vector
else "scalar"
1315 yield f
"{indent}{self.name} ({mode})"
1316 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1317 yield f
"{indent}{indent}{', '.join(span)}"
1318 if isinstance(insn
, SVP64Instruction
):
1319 for extra_idx
in frozenset(self
.extra_idx
):
1320 if self
.record
.etype
is _SVEType
.NONE
:
1321 yield f
"{indent}{indent}extra[none]"
1323 etype
= repr(self
.record
.etype
).lower()
1324 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1326 vector
= "*" if vector
else ""
1327 yield f
"{vector}{prefix}{int(value)}"
1330 class SimpleRegisterOperand(ExtendableOperand
):
1331 def remap(self
, value
, vector
):
1333 extra
= (value
& 0b11)
1334 value
= (value
>> 2)
1336 extra
= (value
>> 5)
1337 value
= (value
& 0b11111)
1339 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1340 # (and shrink to a single bit if ok)
1341 if self
.record
.etype
is _SVEType
.EXTRA2
:
1343 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1344 assert (extra
& 0b01) == 0, \
1345 ("vector field %s cannot fit into EXTRA2" % value
)
1346 extra
= (0b10 |
(extra
>> 1))
1348 # range is r0-r63 in increments of 1
1349 assert (extra
>> 1) == 0, \
1350 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1352 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1354 # EXTRA3 vector bit needs marking
1357 raise ValueError(self
.record
.etype
)
1359 return (value
, extra
)
1362 class GPROperand(SimpleRegisterOperand
):
1363 def assemble(self
, insn
, value
):
1364 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1366 def disassemble(self
, insn
,
1367 style
=Style
.NORMAL
, indent
=""):
1368 prefix
= "" if (style
<= Style
.SHORT
) else "r"
1369 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1370 style
=style
, indent
=indent
)
1373 class GPRPairOperand(GPROperand
):
1377 class FPROperand(SimpleRegisterOperand
):
1378 def assemble(self
, insn
, value
):
1379 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1381 def disassemble(self
, insn
,
1382 style
=Style
.NORMAL
, indent
=""):
1383 prefix
= "" if (style
<= Style
.SHORT
) else "f"
1384 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1385 style
=style
, indent
=indent
)
1388 class FPRPairOperand(FPROperand
):
1392 class ConditionRegisterFieldOperand(ExtendableOperand
):
1393 def pattern(name_pattern
):
1394 (name
, pattern
) = name_pattern
1395 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1404 CR
= r
"(?:CR|cr)([0-9]+)"
1406 BIT
= rf
"({'|'.join(CONDS.keys())})"
1407 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1408 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1409 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1410 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1411 XCR
= fr
"{CR}\.{BIT}"
1412 PATTERNS
= tuple(map(pattern
, (
1417 ("BIT+CR", (LBIT
+ CR
)),
1418 ("CR+BIT", (CR
+ RBIT
)),
1419 ("BIT+CR*N", (LBIT
+ CRN
)),
1420 ("CR*N+BIT", (CRN
+ RBIT
)),
1421 ("BIT+N*CR", (LBIT
+ NCR
)),
1422 ("N*CR+BIT", (NCR
+ RBIT
)),
1425 def remap(self
, value
, vector
, regtype
):
1426 if regtype
is _RegType
.CR_5BIT
:
1427 subvalue
= (value
& 0b11)
1431 extra
= (value
& 0b1111)
1434 extra
= (value
>> 3)
1437 if self
.record
.etype
is _SVEType
.EXTRA2
:
1439 assert (extra
& 0b111) == 0, \
1440 "vector CR cannot fit into EXTRA2"
1441 extra
= (0b10 |
(extra
>> 3))
1443 assert (extra
>> 1) == 0, \
1444 "scalar CR cannot fit into EXTRA2"
1446 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1448 assert (extra
& 0b11) == 0, \
1449 "vector CR cannot fit into EXTRA3"
1450 extra
= (0b100 |
(extra
>> 2))
1452 assert (extra
>> 2) == 0, \
1453 "scalar CR cannot fit into EXTRA3"
1456 if regtype
is _RegType
.CR_5BIT
:
1457 value
= ((value
<< 2) | subvalue
)
1459 return (value
, extra
)
1461 def assemble(self
, insn
, value
):
1462 if isinstance(value
, str):
1465 if value
.startswith("*"):
1466 if not isinstance(insn
, SVP64Instruction
):
1467 raise ValueError(value
)
1471 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1472 match
= pattern
.match(value
)
1473 if match
is not None:
1474 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1475 values
= match
.groups()
1476 match
= dict(zip(keys
, values
))
1477 CR
= int(match
["CR"])
1481 N
= int(match
.get("N", "1"))
1482 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1483 value
= ((CR
* N
) + BIT
)
1490 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1492 def disassemble(self
, insn
,
1493 style
=Style
.NORMAL
, prefix
="", indent
=""):
1494 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1496 if style
>= Style
.VERBOSE
:
1497 mode
= "vector" if vector
else "scalar"
1498 yield f
"{indent}{self.name} ({mode})"
1499 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1500 yield f
"{indent}{indent}{', '.join(span)}"
1501 if isinstance(insn
, SVP64Instruction
):
1502 for extra_idx
in frozenset(self
.extra_idx
):
1503 if self
.record
.etype
is _SVEType
.NONE
:
1504 yield f
"{indent}{indent}extra[none]"
1506 etype
= repr(self
.record
.etype
).lower()
1507 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1509 vector
= "*" if vector
else ""
1510 CR
= int(value
>> 2)
1512 cond
= ("lt", "gt", "eq", "so")[CC
]
1513 if style
>= Style
.NORMAL
:
1515 if isinstance(insn
, SVP64Instruction
):
1516 yield f
"{vector}cr{CR}.{cond}"
1518 yield f
"4*cr{CR}+{cond}"
1522 yield f
"{vector}{prefix}{int(value)}"
1525 class CR3Operand(ConditionRegisterFieldOperand
):
1526 def remap(self
, value
, vector
):
1527 return super().remap(value
=value
, vector
=vector
,
1528 regtype
=_RegType
.CR_3BIT
)
1531 class CR5Operand(ConditionRegisterFieldOperand
):
1532 def remap(self
, value
, vector
):
1533 return super().remap(value
=value
, vector
=vector
,
1534 regtype
=_RegType
.CR_5BIT
)
1536 def sv_spec_enter(self
, value
, span
):
1537 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1538 return (value
, span
)
1540 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1541 value
= _selectconcat(value
, origin_value
[3:5])
1543 return (value
, span
)
1546 class EXTSOperand(SignedOperand
):
1547 field
: str # real name to report
1548 nz
: int = 0 # number of zeros
1549 fmt
: str = "d" # integer formatter
1551 def __init__(self
, record
, name
, field
, nz
=0, fmt
="d"):
1552 self
.__field
= field
1555 return super().__init
__(record
=record
, name
=name
)
1571 return self
.record
.fields
[self
.field
]
1573 def assemble(self
, insn
, value
):
1575 if isinstance(value
, str):
1576 value
= int(value
, 0)
1577 insn
[span
] = (value
>> self
.nz
)
1579 def disassemble(self
, insn
,
1580 style
=Style
.NORMAL
, indent
=""):
1582 value
= insn
[span
].to_signed_int()
1583 sign
= "-" if (value
< 0) else ""
1584 value
= (abs(value
) << self
.nz
)
1586 if style
>= Style
.VERBOSE
:
1587 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1588 zeros
= ("0" * self
.nz
)
1589 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1590 yield f
"{indent * 1}{hint}"
1591 yield f
"{indent * 2}{self.field}"
1592 yield f
"{indent * 3}{sign}{value:{self.fmt}}"
1593 yield f
"{indent * 3}{', '.join(span)}"
1595 yield f
"{sign}{value:{self.fmt}}"
1598 class TargetAddrOperand(EXTSOperand
):
1599 def __init__(self
, record
, name
, field
):
1600 return super().__init
__(record
=record
, name
=name
, field
=field
,
1604 class TargetAddrOperandLI(TargetAddrOperand
):
1605 def __init__(self
, record
, name
):
1606 return super().__init
__(record
=record
, name
=name
, field
="LI")
1609 class TargetAddrOperandBD(TargetAddrOperand
):
1610 def __init__(self
, record
, name
):
1611 return super().__init
__(record
=record
, name
=name
, field
="BD")
1614 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1615 def __init__(self
, record
, name
):
1616 return super().__init
__(record
=record
, name
=name
, field
="DS", nz
=2)
1619 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1620 def __init__(self
, record
, name
):
1621 return super().__init
__(record
=record
, name
=name
, field
="DQ", nz
=4)
1624 class DOperandDX(SignedOperand
):
1627 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1628 operands
= map(cls
, ("d0", "d1", "d2"))
1629 spans
= map(lambda operand
: operand
.span
, operands
)
1630 return sum(spans
, tuple())
1632 def disassemble(self
, insn
,
1633 style
=Style
.NORMAL
, indent
=""):
1635 value
= insn
[span
].to_signed_int()
1636 sign
= "-" if (value
< 0) else ""
1639 if style
>= Style
.VERBOSE
:
1646 for (subname
, subspan
) in mapping
.items():
1647 operand
= DynamicOperand(name
=subname
)
1649 span
= map(str, span
)
1650 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1651 yield f
"{indent}{indent}{indent}{sign}{value}"
1652 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1654 yield f
"{sign}{value}"
1657 class Instruction(_Mapping
):
1659 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1660 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1661 raise ValueError(bits
)
1663 if isinstance(value
, bytes
):
1664 if ((len(value
) * 8) != bits
):
1665 raise ValueError(f
"bit length mismatch")
1666 value
= int.from_bytes(value
, byteorder
=byteorder
)
1668 if isinstance(value
, int):
1669 value
= _SelectableInt(value
=value
, bits
=bits
)
1670 elif isinstance(value
, Instruction
):
1671 value
= value
.storage
1673 if not isinstance(value
, _SelectableInt
):
1674 raise ValueError(value
)
1677 if len(value
) != bits
:
1678 raise ValueError(value
)
1680 value
= _SelectableInt(value
=value
, bits
=bits
)
1682 return cls(storage
=value
)
1685 return hash(int(self
))
1687 def __getitem__(self
, key
):
1688 return self
.storage
.__getitem
__(key
)
1690 def __setitem__(self
, key
, value
):
1691 return self
.storage
.__setitem
__(key
, value
)
1693 def bytes(self
, byteorder
="little"):
1694 nr_bytes
= (len(self
.__class
__) // 8)
1695 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1698 def record(cls
, db
, entry
):
1701 raise KeyError(entry
)
1705 def operands(cls
, record
):
1706 yield from record
.operands
1709 def static_operands(cls
, record
):
1710 return filter(lambda operand
: isinstance(operand
, StaticOperand
),
1711 cls
.operands(record
=record
))
1714 def dynamic_operands(cls
, record
):
1715 return filter(lambda operand
: isinstance(operand
, DynamicOperand
),
1716 cls
.operands(record
=record
))
1718 def spec(self
, record
, prefix
):
1719 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1720 self
.spec_dynamic_operands(record
=record
)))
1722 static_operands
= []
1723 for (name
, value
) in self
.spec_static_operands(record
=record
):
1724 static_operands
.append(f
"{name}={value}")
1727 if dynamic_operands
:
1729 operands
+= ",".join(dynamic_operands
)
1732 operands
+= " ".join(static_operands
)
1734 return f
"{prefix}{record.name}{operands}"
1736 def spec_static_operands(self
, record
):
1737 for operand
in self
.static_operands(record
=record
):
1738 if not isinstance(operand
, (POStaticOperand
, XOStaticOperand
)):
1739 yield (operand
.name
, operand
.value
)
1741 def spec_dynamic_operands(self
, record
, style
=Style
.NORMAL
):
1745 for operand
in self
.dynamic_operands(record
=record
):
1747 value
= " ".join(operand
.disassemble(insn
=self
,
1748 style
=min(style
, Style
.NORMAL
)))
1750 name
= f
"{imm_name}({name})"
1751 value
= f
"{imm_value}({value})"
1753 if isinstance(operand
, ImmediateOperand
):
1761 def assemble(cls
, record
, arguments
=None):
1762 if arguments
is None:
1765 insn
= cls
.integer(value
=0)
1767 for operand
in cls
.static_operands(record
=record
):
1768 operand
.assemble(insn
=insn
)
1770 arguments
= Arguments(record
=record
,
1771 arguments
=arguments
, operands
=cls
.dynamic_operands(record
=record
))
1772 for (value
, operand
) in arguments
:
1773 operand
.assemble(insn
=insn
, value
=value
)
1777 def disassemble(self
, record
,
1779 style
=Style
.NORMAL
):
1780 raise NotImplementedError()
1783 class WordInstruction(Instruction
):
1784 _
: _Field
= range(0, 32)
1785 PO
: _Field
= range(0, 6)
1788 def integer(cls
, value
, byteorder
="little"):
1789 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1794 for idx
in range(32):
1795 bit
= int(self
[idx
])
1797 return "".join(map(str, bits
))
1799 def disassemble(self
, record
,
1801 style
=Style
.NORMAL
):
1802 if style
<= Style
.SHORT
:
1805 blob
= self
.bytes(byteorder
=byteorder
)
1806 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1810 yield f
"{blob}.long 0x{int(self):08x}"
1813 # awful temporary hack: workaround for ld-update
1814 # https://bugs.libre-soc.org/show_bug.cgi?id=1056#c2
1815 # XXX TODO must check that *EXTENDED* RA != extended-RT
1816 if (record
.svp64
is not None and
1817 record
.mode
== _SVMode
.LDST_IMM
and
1818 'u' in record
.name
):
1819 yield f
"{blob}.long 0x{int(self):08x}"
1823 if style
is Style
.LEGACY
:
1825 for operand
in self
.dynamic_operands(record
=record
):
1826 if isinstance(operand
, (GPRPairOperand
, FPRPairOperand
)):
1829 # unofficial == "0" means an official instruction that needs .long
1830 if style
is Style
.LEGACY
and (paired
or record
.ppc
.unofficial
!= ""):
1831 yield f
"{blob}.long 0x{int(self):08x}"
1833 operands
= tuple(map(_operator
.itemgetter(1),
1834 self
.spec_dynamic_operands(record
=record
, style
=style
)))
1836 operands
= ",".join(operands
)
1837 yield f
"{blob}{record.name} {operands}"
1839 yield f
"{blob}{record.name}"
1841 if style
>= Style
.VERBOSE
:
1843 binary
= self
.binary
1844 spec
= self
.spec(record
=record
, prefix
="")
1845 yield f
"{indent}spec"
1846 yield f
"{indent}{indent}{spec}"
1847 yield f
"{indent}pcode"
1848 for stmt
in record
.mdwn
.pcode
:
1849 yield f
"{indent}{indent}{stmt}"
1850 yield f
"{indent}binary"
1851 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1852 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1853 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1854 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1855 yield f
"{indent}opcodes"
1856 for opcode
in record
.opcodes
:
1857 yield f
"{indent}{indent}{opcode!r}"
1858 for operand
in self
.operands(record
=record
):
1859 yield from operand
.disassemble(insn
=self
,
1860 style
=style
, indent
=indent
)
1864 class PrefixedInstruction(Instruction
):
1865 class Prefix(WordInstruction
.remap(range(0, 32))):
1868 class Suffix(WordInstruction
.remap(range(32, 64))):
1871 _
: _Field
= range(64)
1877 def integer(cls
, value
, byteorder
="little"):
1878 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1881 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1882 def transform(value
):
1883 return WordInstruction
.integer(value
=value
,
1884 byteorder
=byteorder
)[0:32]
1886 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1887 value
= _selectconcat(prefix
, suffix
)
1889 return super().integer(bits
=64, value
=value
)
1892 class Mode(_Mapping
):
1893 _
: _Field
= range(0, 5)
1894 sel
: _Field
= (0, 1)
1897 class ExtraRM(_Mapping
):
1898 _
: _Field
= range(0, 9)
1901 class Extra2RM(ExtraRM
):
1902 idx0
: _Field
= range(0, 2)
1903 idx1
: _Field
= range(2, 4)
1904 idx2
: _Field
= range(4, 6)
1905 idx3
: _Field
= range(6, 8)
1907 def __getitem__(self
, key
):
1913 _SVExtra
.Idx0
: self
.idx0
,
1914 _SVExtra
.Idx1
: self
.idx1
,
1915 _SVExtra
.Idx2
: self
.idx2
,
1916 _SVExtra
.Idx3
: self
.idx3
,
1919 def __setitem__(self
, key
, value
):
1920 self
[key
].assign(value
)
1923 class Extra3RM(ExtraRM
):
1924 idx0
: _Field
= range(0, 3)
1925 idx1
: _Field
= range(3, 6)
1926 idx2
: _Field
= range(6, 9)
1928 def __getitem__(self
, key
):
1933 _SVExtra
.Idx0
: self
.idx0
,
1934 _SVExtra
.Idx1
: self
.idx1
,
1935 _SVExtra
.Idx2
: self
.idx2
,
1938 def __setitem__(self
, key
, value
):
1939 self
[key
].assign(value
)
1942 class BaseRM(_Mapping
):
1943 _
: _Field
= range(24)
1944 mmode
: _Field
= (0,)
1945 mask
: _Field
= range(1, 4)
1946 elwidth
: _Field
= range(4, 6)
1947 ewsrc
: _Field
= range(6, 8)
1948 subvl
: _Field
= range(8, 10)
1949 mode
: Mode
.remap(range(19, 24))
1950 smask_extra322
: _Field
= (6,7,18,) # LDST_IDX is EXTRA332
1951 smask
: _Field
= range(16, 19) # everything else use this
1952 extra
: ExtraRM
.remap(range(10, 19))
1953 extra2
: Extra2RM
.remap(range(10, 19))
1954 extra3
: Extra3RM
.remap(range(10, 19))
1955 # XXX extra332 = (extra3[0], extra3[1], extra2[3])
1957 def specifiers(self
, record
):
1958 subvl
= int(self
.subvl
)
1966 def disassemble(self
, style
=Style
.NORMAL
):
1967 if style
>= Style
.VERBOSE
:
1969 for (name
, span
) in self
.traverse(path
="RM"):
1970 value
= self
.storage
[span
]
1972 yield f
"{indent}{int(value):0{value.bits}b}"
1973 yield f
"{indent}{', '.join(map(str, span))}"
1976 class FFRc1BaseRM(BaseRM
):
1977 def specifiers(self
, record
, mode
):
1978 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1979 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1980 mask
= int(_selectconcat(CR
, inv
))
1981 predicate
= PredicateBaseRM
.predicate(True, mask
)
1982 yield f
"{mode}={predicate}"
1984 yield from super().specifiers(record
=record
)
1987 class FFRc0BaseRM(BaseRM
):
1988 def specifiers(self
, record
, mode
):
1990 inv
= "~" if self
.inv
else ""
1991 yield f
"{mode}={inv}RC1"
1993 yield from super().specifiers(record
=record
)
1996 class SatBaseRM(BaseRM
):
1997 def specifiers(self
, record
):
2003 yield from super().specifiers(record
=record
)
2006 class ZZBaseRM(BaseRM
):
2007 def specifiers(self
, record
):
2011 yield from super().specifiers(record
=record
)
2014 class ZZCombinedBaseRM(BaseRM
):
2015 def specifiers(self
, record
):
2016 if self
.sz
and self
.dz
:
2023 yield from super().specifiers(record
=record
)
2026 class DZBaseRM(BaseRM
):
2027 def specifiers(self
, record
):
2031 yield from super().specifiers(record
=record
)
2034 class SZBaseRM(BaseRM
):
2035 def specifiers(self
, record
):
2039 yield from super().specifiers(record
=record
)
2042 class MRBaseRM(BaseRM
):
2043 def specifiers(self
, record
):
2049 yield from super().specifiers(record
=record
)
2052 class ElsBaseRM(BaseRM
):
2053 def specifiers(self
, record
):
2057 yield from super().specifiers(record
=record
)
2060 class WidthBaseRM(BaseRM
):
2062 def width(FP
, width
):
2071 width
= ("fp" + width
)
2074 def specifiers(self
, record
):
2075 # elwidths: use "w=" if same otherwise dw/sw
2076 # FIXME this should consider FP instructions
2078 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
2079 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2080 if record
.svp64
.mode
is _SVMode
.CROP
:
2084 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2093 yield from super().specifiers(record
=record
)
2096 class PredicateBaseRM(BaseRM
):
2098 def predicate(CR
, mask
):
2101 (False, 0b001): "1<<r3",
2102 (False, 0b010): "r3",
2103 (False, 0b011): "~r3",
2104 (False, 0b100): "r10",
2105 (False, 0b101): "~r10",
2106 (False, 0b110): "r30",
2107 (False, 0b111): "~r30",
2109 (True, 0b000): "lt",
2110 (True, 0b001): "ge",
2111 (True, 0b010): "gt",
2112 (True, 0b011): "le",
2113 (True, 0b100): "eq",
2114 (True, 0b101): "ne",
2115 (True, 0b110): "so",
2116 (True, 0b111): "ns",
2119 def specifiers(self
, record
):
2120 # predication - single and twin
2121 # use "m=" if same otherwise sm/dm
2122 CR
= (int(self
.mmode
) == 1)
2123 mask
= int(self
.mask
)
2124 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
2125 if record
.svp64
.ptype
is _SVPType
.P2
:
2126 # LDST_IDX smask moving to extra322 but not straight away (False)
2127 if False and record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2128 smask
= int(self
.smask_extra332
)
2130 smask
= int(self
.smask
)
2131 sm
= PredicateBaseRM
.predicate(CR
, smask
)
2140 yield from super().specifiers(record
=record
)
2143 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
2147 class SEABaseRM(BaseRM
):
2148 def specifiers(self
, record
):
2152 yield from super().specifiers(record
=record
)
2155 class VLiBaseRM(BaseRM
):
2156 def specifiers(self
, record
):
2160 yield from super().specifiers(record
=record
)
2163 class NormalBaseRM(PredicateWidthBaseRM
):
2166 https://libre-soc.org/openpower/sv/normal/
2171 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
2172 """normal: simple mode"""
2176 def specifiers(self
, record
):
2177 yield from super().specifiers(record
=record
)
2180 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2181 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2185 class NormalFFRc1RM(FFRc1BaseRM
, VLiBaseRM
, NormalBaseRM
):
2186 """normal: Rc=1: ffirst CR sel"""
2189 CR
: BaseRM
.mode
[3, 4]
2191 def specifiers(self
, record
):
2192 yield from super().specifiers(record
=record
, mode
="ff")
2195 class NormalFFRc0RM(FFRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2196 """normal: Rc=0: ffirst z/nonz"""
2201 def specifiers(self
, record
):
2202 yield from super().specifiers(record
=record
, mode
="ff")
2205 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2206 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2212 class NormalRM(NormalBaseRM
):
2213 simple
: NormalSimpleRM
2215 ffrc1
: NormalFFRc1RM
2216 ffrc0
: NormalFFRc0RM
2220 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2222 LD/ST Immediate mode
2223 https://libre-soc.org/openpower/sv/ldst/
2228 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2229 """ld/st immediate: simple mode"""
2230 pi
: BaseRM
.mode
[2] # Post-Increment Mode
2231 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2237 def specifiers(self
, record
):
2243 yield from super().specifiers(record
=record
)
2246 class LDSTFFRc1RM(FFRc1BaseRM
, VLiBaseRM
, LDSTImmBaseRM
):
2247 """ld/st immediate&indexed: Rc=1: ffirst CR sel"""
2250 CR
: BaseRM
.mode
[3, 4]
2252 def specifiers(self
, record
):
2253 yield from super().specifiers(record
=record
, mode
="ff")
2256 class LDSTFFRc0RM(FFRc0BaseRM
, VLiBaseRM
, LDSTImmBaseRM
):
2257 """ld/st immediate&indexed: Rc=0: ffirst z/nonz"""
2262 def specifiers(self
, record
):
2263 yield from super().specifiers(record
=record
, mode
="ff")
2266 class LDSTImmRM(LDSTImmBaseRM
):
2267 simple
: LDSTImmSimpleRM
2272 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2275 https://libre-soc.org/openpower/sv/ldst/
2280 class LDSTIdxSimpleRM(SEABaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2281 """ld/st index: simple mode (includes element-strided and Signed-EA)"""
2282 pi
: BaseRM
.mode
[2] # Post-Increment Mode
2289 def specifiers(self
, record
):
2295 yield from super().specifiers(record
=record
)
2298 class LDSTIdxRM(LDSTIdxBaseRM
):
2299 simple
: LDSTIdxSimpleRM
2305 class CROpBaseRM(BaseRM
):
2308 https://libre-soc.org/openpower/sv/cr_ops/
2313 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2314 """crop: simple mode"""
2319 def specifiers(self
, record
):
2321 yield "rg" # simple CR Mode reports /rg
2323 yield from super().specifiers(record
=record
)
2326 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2327 """crop: scalar reduce mode (mapreduce)"""
2333 class CROpFF5RM(FFRc0BaseRM
, PredicateBaseRM
, VLiBaseRM
, DZBaseRM
,
2334 SZBaseRM
, CROpBaseRM
):
2335 """crop: ffirst 5-bit mode"""
2342 def specifiers(self
, record
):
2343 yield from super().specifiers(record
=record
, mode
="ff")
2346 # FIXME: almost everything in this class contradicts the specs (it doesn't)
2347 # The modes however are swapped: 5-bit is 3-bit, 3-bit is 5-bit
2348 class CROpFF3RM(FFRc1BaseRM
, PredicateBaseRM
, VLiBaseRM
, ZZBaseRM
, CROpBaseRM
):
2349 """cr_op: ffirst 3-bit mode"""
2355 def specifiers(self
, record
):
2356 yield from super().specifiers(record
=record
, mode
="ff")
2359 class CROpRM(CROpBaseRM
):
2360 simple
: CROpSimpleRM
2366 # ********************
2368 # https://libre-soc.org/openpower/sv/branches/
2369 class BranchBaseRM(BaseRM
):
2379 def specifiers(self
, record
):
2391 raise ValueError(self
.sz
)
2403 # Branch modes lack source mask.
2404 # Therefore a custom code is needed.
2405 CR
= (int(self
.mmode
) == 1)
2406 mask
= int(self
.mask
)
2407 m
= PredicateBaseRM
.predicate(CR
, mask
)
2411 yield from super().specifiers(record
=record
)
2414 class BranchSimpleRM(BranchBaseRM
):
2415 """branch: simple mode"""
2419 class BranchVLSRM(BranchBaseRM
):
2420 """branch: VLSET mode"""
2424 def specifiers(self
, record
):
2430 }[int(self
.VSb
), int(self
.VLi
)]
2432 yield from super().specifiers(record
=record
)
2435 class BranchCTRRM(BranchBaseRM
):
2436 """branch: CTR-test mode"""
2439 def specifiers(self
, record
):
2445 yield from super().specifiers(record
=record
)
2448 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2449 """branch: CTR-test+VLSET mode"""
2453 class BranchRM(BranchBaseRM
):
2454 simple
: BranchSimpleRM
2457 ctrvls
: BranchCTRVLSRM
2468 @_dataclasses.dataclass(eq
=True, frozen
=True)
2473 def match(cls
, desc
, record
):
2474 raise NotImplementedError()
2476 def validate(self
, others
):
2479 def assemble(self
, insn
):
2480 raise NotImplementedError()
2483 @_dataclasses.dataclass(eq
=True, frozen
=True)
2484 class SpecifierWidth(Specifier
):
2488 def match(cls
, desc
, record
, etalon
):
2489 (mode
, _
, value
) = desc
.partition("=")
2491 value
= value
.strip()
2494 width
= _SVP64Width(value
)
2496 return cls(record
=record
, width
=width
)
2499 @_dataclasses.dataclass(eq
=True, frozen
=True)
2500 class SpecifierW(SpecifierWidth
):
2502 def match(cls
, desc
, record
):
2503 return super().match(desc
=desc
, record
=record
, etalon
="w")
2505 def assemble(self
, insn
):
2506 selector
= insn
.select(record
=self
.record
)
2507 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2508 selector
.ewsrc
= self
.width
.value
2509 selector
.elwidth
= self
.width
.value
2512 @_dataclasses.dataclass(eq
=True, frozen
=True)
2513 class SpecifierSW(SpecifierWidth
):
2515 def match(cls
, desc
, record
):
2516 if record
.svp64
.mode
is _SVMode
.CROP
:
2518 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2520 def assemble(self
, insn
):
2521 selector
= insn
.select(record
=self
.record
)
2522 selector
.ewsrc
= self
.width
.value
2525 @_dataclasses.dataclass(eq
=True, frozen
=True)
2526 class SpecifierDW(SpecifierWidth
):
2528 def match(cls
, desc
, record
):
2529 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2531 def assemble(self
, insn
):
2532 selector
= insn
.select(record
=self
.record
)
2533 selector
.elwidth
= self
.width
.value
2536 @_dataclasses.dataclass(eq
=True, frozen
=True)
2537 class SpecifierSubVL(Specifier
):
2541 def match(cls
, desc
, record
):
2543 value
= _SVP64SubVL(desc
)
2547 return cls(record
=record
, value
=value
)
2549 def assemble(self
, insn
):
2550 selector
= insn
.select(record
=self
.record
)
2551 selector
.subvl
= int(self
.value
.value
)
2554 @_dataclasses.dataclass(eq
=True, frozen
=True)
2555 class SpecifierPredicate(Specifier
):
2560 def match(cls
, desc
, record
, mode_match
, pred_match
):
2561 (mode
, _
, pred
) = desc
.partition("=")
2564 if not mode_match(mode
):
2567 pred
= _SVP64Pred(pred
.strip())
2568 if not pred_match(pred
):
2569 raise ValueError(pred
)
2571 return cls(record
=record
, mode
=mode
, pred
=pred
)
2574 @_dataclasses.dataclass(eq
=True, frozen
=True)
2575 class SpecifierFF(SpecifierPredicate
):
2577 def match(cls
, desc
, record
):
2578 return super().match(desc
=desc
, record
=record
,
2579 mode_match
=lambda mode_arg
: mode_arg
== "ff",
2580 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2585 def assemble(self
, insn
):
2586 selector
= insn
.select(record
=self
.record
)
2587 if selector
.mode
.sel
!= 0:
2588 raise ValueError("cannot override mode")
2589 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2590 selector
.mode
.sel
= 0b01
2591 # HACK: please finally provide correct logic for CRs.
2592 if self
.pred
in (_SVP64Pred
.RC1
, _SVP64Pred
.RC1_N
):
2593 selector
.mode
[2] = (self
.pred
is _SVP64Pred
.RC1_N
)
2595 selector
.mode
[2] = self
.pred
.inv
2596 selector
.mode
[3, 4] = self
.pred
.state
2598 selector
.mode
.sel
= 0b01 if self
.mode
== "ff" else 0b11
2599 selector
.inv
= self
.pred
.inv
2601 selector
.CR
= self
.pred
.state
2603 selector
.RC1
= self
.pred
.state
2606 @_dataclasses.dataclass(eq
=True, frozen
=True)
2607 class SpecifierMask(SpecifierPredicate
):
2609 def match(cls
, desc
, record
, mode
):
2610 return super().match(desc
=desc
, record
=record
,
2611 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2612 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2617 def assemble(self
, insn
):
2618 raise NotImplementedError()
2621 @_dataclasses.dataclass(eq
=True, frozen
=True)
2622 class SpecifierM(SpecifierMask
):
2624 def match(cls
, desc
, record
):
2625 return super().match(desc
=desc
, record
=record
, mode
="m")
2627 def validate(self
, others
):
2629 if isinstance(spec
, SpecifierSM
):
2630 raise ValueError("source-mask and predicate mask conflict")
2631 elif isinstance(spec
, SpecifierDM
):
2632 raise ValueError("dest-mask and predicate mask conflict")
2634 def assemble(self
, insn
):
2635 selector
= insn
.select(record
=self
.record
)
2636 selector
.mask
= int(self
.pred
)
2637 if ((self
.record
.ptype
is _SVPType
.P2
) and
2638 (self
.record
.svp64
.mode
is not _SVMode
.BRANCH
)):
2639 selector
.smask
= int(self
.pred
)
2640 # LDST_IDX smask moving to extra322 but not straight away (False)
2641 if False and self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2642 selector
.smask_extra332
= int(self
.pred
)
2644 selector
.smask
= int(self
.pred
)
2646 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2649 @_dataclasses.dataclass(eq
=True, frozen
=True)
2650 class SpecifierSM(SpecifierMask
):
2652 def match(cls
, desc
, record
):
2653 return super().match(desc
=desc
, record
=record
, mode
="sm")
2655 def validate(self
, others
):
2656 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2657 raise ValueError("source-mask on non-twin predicate")
2659 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2662 if isinstance(spec
, SpecifierDM
):
2666 raise ValueError("missing dest-mask in CR twin predication")
2667 if self
.pred
.mode
!= twin
.pred
.mode
:
2668 raise ValueError(f
"predicate masks mismatch: "
2669 f
"{self.pred!r} vs {twin.pred!r}")
2671 def assemble(self
, insn
):
2672 selector
= insn
.select(record
=self
.record
)
2673 # LDST_IDX smask moving to extra322 but not straight away (False)
2674 if False and self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2675 selector
.smask_extra332
= int(self
.pred
)
2677 selector
.smask
= int(self
.pred
)
2678 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2681 @_dataclasses.dataclass(eq
=True, frozen
=True)
2682 class SpecifierDM(SpecifierMask
):
2684 def match(cls
, desc
, record
):
2685 return super().match(desc
=desc
, record
=record
, mode
="dm")
2687 def validate(self
, others
):
2688 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2689 raise ValueError("dest-mask on non-twin predicate")
2691 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2694 if isinstance(spec
, SpecifierSM
):
2698 raise ValueError("missing source-mask in CR twin predication")
2699 if self
.pred
.mode
!= twin
.pred
.mode
:
2700 raise ValueError(f
"predicate masks mismatch: "
2701 f
"{self.pred!r} vs {twin.pred!r}")
2703 def assemble(self
, insn
):
2704 selector
= insn
.select(record
=self
.record
)
2705 selector
.mask
= int(self
.pred
)
2706 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2709 @_dataclasses.dataclass(eq
=True, frozen
=True)
2710 class SpecifierZZ(Specifier
):
2712 def match(cls
, desc
, record
):
2716 return cls(record
=record
)
2718 def validate(self
, others
):
2720 # Since zz takes precedence (overrides) sz and dz,
2721 # treat them as mutually exclusive.
2722 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2723 raise ValueError("mutually exclusive predicate masks")
2725 def assemble(self
, insn
):
2726 selector
= insn
.select(record
=self
.record
)
2727 if hasattr(selector
, "zz"): # this should be done in a different way
2734 @_dataclasses.dataclass(eq
=True, frozen
=True)
2735 class SpecifierXZ(Specifier
):
2737 hint
: str = _dataclasses
.field(repr=False)
2740 def match(cls
, desc
, record
, etalon
, hint
):
2744 return cls(desc
=desc
, record
=record
, hint
=hint
)
2746 def validate(self
, others
):
2747 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2748 raise ValueError(f
"{self.hint} on non-twin predicate")
2750 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2753 if isinstance(spec
, SpecifierXZ
):
2757 raise ValueError(f
"missing {self.hint} in CR twin predication")
2758 if self
.pred
!= twin
.pred
:
2759 raise ValueError(f
"predicate masks mismatch: "
2760 f
"{self.pred!r} vs {twin.pred!r}")
2762 def assemble(self
, insn
):
2763 selector
= insn
.select(record
=self
.record
)
2764 setattr(selector
, self
.desc
, 1)
2767 @_dataclasses.dataclass(eq
=True, frozen
=True)
2768 class SpecifierSZ(SpecifierXZ
):
2770 def match(cls
, desc
, record
):
2771 return super().match(desc
=desc
, record
=record
,
2772 etalon
="sz", hint
="source-mask")
2774 def validate(self
, others
):
2776 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2777 if isinstance(spec
, SpecifierFF
):
2778 raise ValueError("source-zero not allowed in ff mode")
2781 @_dataclasses.dataclass(eq
=True, frozen
=True)
2782 class SpecifierDZ(SpecifierXZ
):
2784 def match(cls
, desc
, record
):
2785 return super().match(desc
=desc
, record
=record
,
2786 etalon
="dz", hint
="dest-mask")
2788 def validate(self
, others
):
2790 if ((self
.record
.svp64
.mode
is not _SVMode
.CROP
) and
2791 isinstance(spec
, SpecifierFF
) and
2792 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2793 raise ValueError(f
"dest-zero not allowed in ff mode BO")
2796 @_dataclasses.dataclass(eq
=True, frozen
=True)
2797 class SpecifierEls(Specifier
):
2799 def match(cls
, desc
, record
):
2803 if record
.svp64
.mode
not in (_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2804 raise ValueError("els is only valid in ld/st modes, not "
2805 "%s" % str(self
.record
.svp64
.mode
))
2807 return cls(record
=record
)
2809 def assemble(self
, insn
):
2810 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
: # stride mode
2811 insn
.prefix
.rm
.mode
[1] = 0
2813 selector
= insn
.select(record
=self
.record
)
2818 @_dataclasses.dataclass(eq
=True, frozen
=True)
2819 class SpecifierSEA(Specifier
):
2821 def match(cls
, desc
, record
):
2825 return cls(record
=record
)
2827 def validate(self
, others
):
2828 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2829 raise ValueError("sea is only valid in ld/st modes, not "
2830 "%s" % str(self
.record
.svp64
.mode
))
2833 if isinstance(spec
, SpecifierFF
):
2834 raise ValueError(f
"sea cannot be used in ff mode")
2836 def assemble(self
, insn
):
2837 selector
= insn
.select(record
=self
.record
)
2838 if selector
.mode
.sel
not in (0b10, 0b00):
2839 raise ValueError("sea is only valid for normal and els modes, "
2840 "not %d" % int(selector
.mode
.sel
))
2844 @_dataclasses.dataclass(eq
=True, frozen
=True)
2845 class SpecifierSat(Specifier
):
2850 def match(cls
, desc
, record
, etalon
, sign
):
2854 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.LDST_IMM
,
2856 raise ValueError("only normal, ld/st imm and "
2857 "ld/st idx modes supported")
2859 return cls(record
=record
, desc
=desc
, sign
=sign
)
2861 def assemble(self
, insn
):
2862 selector
= insn
.select(record
=self
.record
)
2863 selector
.mode
[0] = 0b1
2864 selector
.mode
[1] = 0b0
2865 selector
.N
= int(self
.sign
)
2868 @_dataclasses.dataclass(eq
=True, frozen
=True)
2869 class SpecifierSatS(SpecifierSat
):
2871 def match(cls
, desc
, record
):
2872 return super().match(desc
=desc
, record
=record
,
2873 etalon
="sats", sign
=True)
2876 @_dataclasses.dataclass(eq
=True, frozen
=True)
2877 class SpecifierSatU(SpecifierSat
):
2879 def match(cls
, desc
, record
):
2880 return super().match(desc
=desc
, record
=record
,
2881 etalon
="satu", sign
=False)
2884 @_dataclasses.dataclass(eq
=True, frozen
=True)
2885 class SpecifierMapReduce(Specifier
):
2889 def match(cls
, record
, RG
):
2890 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2891 raise ValueError("only normal and crop modes supported")
2893 return cls(record
=record
, RG
=RG
)
2895 def assemble(self
, insn
):
2896 selector
= insn
.select(record
=self
.record
)
2897 if self
.record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2898 raise ValueError("only normal and crop modes supported")
2899 selector
.mode
[0] = 0
2900 selector
.mode
[1] = 0
2901 selector
.mode
[2] = 1
2902 selector
.RG
= self
.RG
2905 @_dataclasses.dataclass(eq
=True, frozen
=True)
2906 class SpecifierMR(SpecifierMapReduce
):
2908 def match(cls
, desc
, record
):
2912 return super().match(record
=record
, RG
=False)
2915 @_dataclasses.dataclass(eq
=True, frozen
=True)
2916 class SpecifierMRR(SpecifierMapReduce
):
2918 def match(cls
, desc
, record
):
2922 return super().match(record
=record
, RG
=True)
2925 @_dataclasses.dataclass(eq
=True, frozen
=True)
2926 class SpecifierBranch(Specifier
):
2928 def match(cls
, desc
, record
, etalon
):
2932 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
2933 raise ValueError("only branch modes supported")
2935 return cls(record
=record
)
2938 @_dataclasses.dataclass(eq
=True, frozen
=True)
2939 class SpecifierAll(SpecifierBranch
):
2941 def match(cls
, desc
, record
):
2942 return super().match(desc
=desc
, record
=record
, etalon
="all")
2944 def assemble(self
, insn
):
2945 selector
= insn
.select(record
=self
.record
)
2949 @_dataclasses.dataclass(eq
=True, frozen
=True)
2950 class SpecifierSNZ(Specifier
):
2952 def match(cls
, desc
, record
):
2956 if record
.svp64
.mode
not in (_SVMode
.BRANCH
, _SVMode
.CROP
):
2957 raise ValueError("only branch and crop modes supported")
2959 return cls(record
=record
)
2961 def assemble(self
, insn
):
2962 selector
= insn
.select(record
=self
.record
)
2963 if self
.record
.svp64
.mode
in (_SVMode
.CROP
, _SVMode
.BRANCH
):
2965 if self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
2968 raise ValueError("only branch and crop modes supported")
2971 @_dataclasses.dataclass(eq
=True, frozen
=True)
2972 class SpecifierSL(SpecifierBranch
):
2974 def match(cls
, desc
, record
):
2975 return super().match(desc
=desc
, record
=record
, etalon
="sl")
2977 def assemble(self
, insn
):
2978 selector
= insn
.select(record
=self
.record
)
2982 @_dataclasses.dataclass(eq
=True, frozen
=True)
2983 class SpecifierSLu(SpecifierBranch
):
2985 def match(cls
, desc
, record
):
2986 return super().match(desc
=desc
, record
=record
, etalon
="slu")
2988 def assemble(self
, insn
):
2989 selector
= insn
.select(record
=self
.record
)
2993 @_dataclasses.dataclass(eq
=True, frozen
=True)
2994 class SpecifierLRu(SpecifierBranch
):
2996 def match(cls
, desc
, record
):
2997 return super().match(desc
=desc
, record
=record
, etalon
="lru")
2999 def assemble(self
, insn
):
3000 selector
= insn
.select(record
=self
.record
)
3004 @_dataclasses.dataclass(eq
=True, frozen
=True)
3005 class SpecifierVSXX(SpecifierBranch
):
3010 def match(cls
, desc
, record
, etalon
, VSb
, VLi
):
3014 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3015 raise ValueError("only branch modes supported")
3017 return cls(record
=record
, VSb
=VSb
, VLi
=VLi
)
3019 def assemble(self
, insn
):
3020 selector
= insn
.select(record
=self
.record
)
3022 selector
.VSb
= int(self
.VSb
)
3023 selector
.VLi
= int(self
.VLi
)
3026 @_dataclasses.dataclass(eq
=True, frozen
=True)
3027 class SpecifierVS(SpecifierVSXX
):
3029 def match(cls
, desc
, record
):
3030 return super().match(desc
=desc
, record
=record
,
3031 etalon
="vs", VSb
=False, VLi
=False)
3034 @_dataclasses.dataclass(eq
=True, frozen
=True)
3035 class SpecifierVSi(SpecifierVSXX
):
3037 def match(cls
, desc
, record
):
3038 return super().match(desc
=desc
, record
=record
,
3039 etalon
="vsi", VSb
=False, VLi
=True)
3042 @_dataclasses.dataclass(eq
=True, frozen
=True)
3043 class SpecifierVSb(SpecifierVSXX
):
3045 def match(cls
, desc
, record
):
3046 return super().match(desc
=desc
, record
=record
,
3047 etalon
="vsb", VSb
=True, VLi
=False)
3050 @_dataclasses.dataclass(eq
=True, frozen
=True)
3051 class SpecifierVSbi(SpecifierVSXX
):
3053 def match(cls
, desc
, record
):
3054 return super().match(desc
=desc
, record
=record
,
3055 etalon
="vsbi", VSb
=True, VLi
=True)
3058 @_dataclasses.dataclass(eq
=True, frozen
=True)
3059 class SpecifierCTX(Specifier
):
3063 def match(cls
, desc
, record
, etalon
, CTi
):
3067 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3068 raise ValueError("only branch modes supported")
3070 return cls(record
=record
, CTi
=CTi
)
3072 def assemble(self
, insn
):
3073 selector
= insn
.select(record
=self
.record
)
3075 selector
.CTi
= int(self
.CTi
)
3078 @_dataclasses.dataclass(eq
=True, frozen
=True)
3079 class SpecifierCTR(SpecifierCTX
):
3081 def match(cls
, desc
, record
):
3082 return super().match(desc
=desc
, record
=record
,
3083 etalon
="ctr", CTi
=False)
3086 @_dataclasses.dataclass(eq
=True, frozen
=True)
3087 class SpecifierCTi(SpecifierCTX
):
3089 def match(cls
, desc
, record
):
3090 return super().match(desc
=desc
, record
=record
,
3091 etalon
="cti", CTi
=True)
3094 @_dataclasses.dataclass(eq
=True, frozen
=True)
3095 class SpecifierPI(Specifier
):
3097 def match(cls
, desc
, record
):
3101 if record
.svp64
.mode
not in [_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
]:
3102 raise ValueError("only ld/st imm/idx mode supported")
3104 return cls(record
=record
)
3106 def assemble(self
, insn
):
3107 selector
= insn
.select(record
=self
.record
)
3108 selector
.mode
[2] = 0b1
3112 @_dataclasses.dataclass(eq
=True, frozen
=True)
3113 class SpecifierLF(Specifier
):
3115 def match(cls
, desc
, record
):
3119 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3120 raise ValueError("only ld/st imm mode supported")
3122 return cls(record
=record
)
3124 def assemble(self
, insn
):
3125 selector
= insn
.select(record
=self
.record
)
3126 selector
.mode
[1] = 0
3130 @_dataclasses.dataclass(eq
=True, frozen
=True)
3131 class SpecifierVLi(Specifier
):
3133 def match(cls
, desc
, record
):
3137 return cls(record
=record
)
3139 def validate(self
, others
):
3141 if isinstance(spec
, SpecifierFF
):
3144 raise ValueError("VLi only allowed in failfirst")
3146 def assemble(self
, insn
):
3147 selector
= insn
.select(record
=self
.record
)
3148 selector
.mode
[1] = 1
3152 class Specifiers(tuple):
3187 def __new__(cls
, items
, record
):
3188 def transform(item
):
3189 for spec_cls
in cls
.SPECS
:
3190 spec
= spec_cls
.match(item
, record
=record
)
3191 if spec
is not None:
3193 raise ValueError(item
)
3195 # TODO: remove this hack
3196 items
= dict.fromkeys(items
)
3200 items
= tuple(items
)
3202 specs
= tuple(map(transform
, items
))
3203 for (index
, spec
) in enumerate(specs
):
3204 head
= specs
[:index
]
3205 tail
= specs
[index
+ 1:]
3206 spec
.validate(others
=(head
+ tail
))
3208 return super().__new
__(cls
, specs
)
3211 class SVP64OperandMeta(type):
3212 class SVP64NonZeroOperand(NonZeroOperand
):
3213 def assemble(self
, insn
, value
):
3214 if isinstance(value
, str):
3215 value
= int(value
, 0)
3216 if not isinstance(value
, int):
3217 raise ValueError("non-integer operand")
3219 # FIXME: this is really weird
3220 if self
.record
.name
in ("svstep", "svstep."):
3221 value
+= 1 # compensation
3223 return super().assemble(value
=value
, insn
=insn
)
3225 class SVP64XOStaticOperand(SpanStaticOperand
):
3226 def __init__(self
, record
, value
, span
):
3227 return super().__init
__(record
=record
, name
="XO",
3228 value
=value
, span
=span
)
3231 NonZeroOperand
: SVP64NonZeroOperand
,
3232 XOStaticOperand
: SVP64XOStaticOperand
,
3235 def __new__(metacls
, name
, bases
, ns
):
3237 for (index
, base_cls
) in enumerate(bases
):
3238 bases
[index
] = metacls
.__TRANSFORM
.get(base_cls
, base_cls
)
3240 bases
= tuple(bases
)
3242 return super().__new
__(metacls
, name
, bases
, ns
)
3245 class SVP64Operand(Operand
, metaclass
=SVP64OperandMeta
):
3248 return tuple(map(lambda bit
: (bit
+ 32), super().span
))
3252 def __init__(self
, insn
, record
):
3254 self
.__record
= record
3255 return super().__init
__()
3258 return self
.rm
.__doc
__
3261 return repr(self
.rm
)
3269 return self
.__record
3273 rm
= getattr(self
.insn
.prefix
.rm
, self
.record
.svp64
.mode
.name
.lower())
3275 # The idea behind these tables is that they are now literally
3276 # in identical format to insndb.csv and minor_xx.csv and can
3277 # be done precisely as that. The only thing to watch out for
3278 # is the insertion of Rc=1 as a "mask/value" bit and likewise
3279 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
3282 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
3283 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3284 # mode Rc mask Rc member
3286 (0b000000, 0b111000, "simple"), # simple (no Rc)
3287 (0b001000, 0b111100, "mr"), # mapreduce (no Rc)
3288 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3289 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3290 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3291 (0b001100, 0b111100, "rsvd"), # reserved
3293 mode
= int(self
.insn
.prefix
.rm
.normal
.mode
)
3294 search
= ((mode
<< 1) | self
.record
.Rc
)
3296 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
3297 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3298 # mode Rc mask Rc member
3299 # ironically/coincidentally this table is identical to NORMAL
3300 # mode except reserved in place of mr
3302 (0b000000, 0b010000, "simple"), # simple (no Rc involved)
3303 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3304 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3306 search
= ((int(self
.insn
.prefix
.rm
.ldst_imm
.mode
) << 1) |
3309 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
3310 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3311 # mode Rc mask Rc member
3313 (0b000000, 0b010000, "simple"), # simple (no Rc involved)
3314 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3315 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3317 search
= ((int(self
.insn
.prefix
.rm
.ldst_idx
.mode
) << 1) |
3320 elif self
.record
.svp64
.mode
is _SVMode
.CROP
:
3321 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
3322 # mode 3b mask 3b member
3324 (0b000000, 0b111000, "simple"), # simple
3325 (0b001000, 0b111000, "mr"), # mapreduce
3326 (0b010001, 0b010001, "ff3"), # ffirst, 3-bit CR
3327 (0b010000, 0b010000, "ff5"), # ffirst, 5-bit CR
3329 search
= ((int(self
.insn
.prefix
.rm
.crop
.mode
) << 1) |
3330 int(self
.record
.svp64
.extra_CR_3bit
))
3332 elif self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3336 (0b00, 0b11, "simple"), # simple
3337 (0b01, 0b11, "vls"), # VLset
3338 (0b10, 0b11, "ctr"), # CTR mode
3339 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
3341 # slightly weird: doesn't have a 5-bit "mode" field like others
3342 search
= int(self
.insn
.prefix
.rm
.branch
.mode
.sel
)
3345 if table
is not None:
3346 for (value
, mask
, field
) in table
:
3347 if field
.startswith("rsvd"):
3349 if ((value
& mask
) == (search
& mask
)):
3350 return getattr(rm
, field
)
3354 def __getattr__(self
, key
):
3355 if key
.startswith(f
"_{self.__class__.__name__}__"):
3356 return super().__getattribute
__(key
)
3358 return getattr(self
.rm
, key
)
3360 def __setattr__(self
, key
, value
):
3361 if key
.startswith(f
"_{self.__class__.__name__}__"):
3362 return super().__setattr
__(key
, value
)
3365 if not hasattr(rm
, key
):
3366 raise AttributeError(key
)
3368 return setattr(rm
, key
, value
)
3371 class SVP64Instruction(PrefixedInstruction
):
3372 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3373 class Prefix(PrefixedInstruction
.Prefix
):
3375 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3379 def select(self
, record
):
3380 return RMSelector(insn
=self
, record
=record
)
3385 for idx
in range(64):
3386 bit
= int(self
[idx
])
3388 return "".join(map(str, bits
))
3391 def assemble(cls
, record
, arguments
=None, specifiers
=None):
3392 insn
= super().assemble(record
=record
, arguments
=arguments
)
3394 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3395 for specifier
in specifiers
:
3396 specifier
.assemble(insn
=insn
)
3398 insn
.prefix
.PO
= 0x1
3399 insn
.prefix
.id = 0x3
3403 def disassemble(self
, record
,
3405 style
=Style
.NORMAL
):
3407 if style
<= Style
.SHORT
:
3410 blob
= insn
.bytes(byteorder
=byteorder
)
3411 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3414 blob_prefix
= blob(self
.prefix
)
3415 blob_suffix
= blob(self
.suffix
)
3417 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3418 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3421 assert record
.svp64
is not None
3423 name
= f
"sv.{record.name}"
3425 rm
= self
.select(record
=record
)
3427 # convert specifiers to /x/y/z (sorted lexicographically)
3428 specifiers
= sorted(rm
.specifiers(record
=record
))
3429 if specifiers
: # if any add one extra to get the extra "/"
3430 specifiers
= ([""] + specifiers
)
3431 specifiers
= "/".join(specifiers
)
3433 # convert operands to " ,x,y,z"
3434 operands
= tuple(map(_operator
.itemgetter(1),
3435 self
.spec_dynamic_operands(record
=record
, style
=style
)))
3436 operands
= ",".join(operands
)
3437 if len(operands
) > 0: # if any separate with a space
3438 operands
= (" " + operands
)
3440 if style
<= Style
.LEGACY
:
3441 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3442 suffix
= WordInstruction
.integer(value
=int(self
.suffix
))
3443 yield from suffix
.disassemble(record
=record
,
3444 byteorder
=byteorder
, style
=style
)
3446 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3448 yield f
"{blob_suffix}"
3450 if style
>= Style
.VERBOSE
:
3452 binary
= self
.binary
3453 spec
= self
.spec(record
=record
, prefix
="sv.")
3455 yield f
"{indent}spec"
3456 yield f
"{indent}{indent}{spec}"
3457 yield f
"{indent}pcode"
3458 for stmt
in record
.mdwn
.pcode
:
3459 yield f
"{indent}{indent}{stmt}"
3460 yield f
"{indent}binary"
3461 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3462 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3463 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3464 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3465 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3466 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3467 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3468 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3469 yield f
"{indent}opcodes"
3470 for opcode
in record
.opcodes
:
3471 yield f
"{indent}{indent}{opcode!r}"
3472 for operand
in self
.operands(record
=record
):
3473 yield from operand
.disassemble(insn
=self
,
3474 style
=style
, indent
=indent
)
3476 yield f
"{indent}{indent}{str(rm)}"
3477 for line
in rm
.disassemble(style
=style
):
3478 yield f
"{indent}{indent}{line}"
3482 def operands(cls
, record
):
3483 for operand
in super().operands(record
=record
):
3484 parent
= operand
.__class
__
3485 name
= f
"SVP64{parent.__name__}"
3486 bases
= (SVP64Operand
, parent
)
3487 child
= type(name
, bases
, {})
3488 yield child(**dict(operand
))
3491 def parse(stream
, factory
):
3493 return ("TODO" not in frozenset(entry
.values()))
3495 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3496 entries
= _csv
.DictReader(lines
)
3497 entries
= filter(match
, entries
)
3498 return tuple(map(factory
, entries
))
3501 class MarkdownDatabase
:
3504 for (name
, desc
) in _ISA():
3507 (dynamic
, *static
) = desc
.regs
3508 operands
.extend(dynamic
)
3509 operands
.extend(static
)
3510 pcode
= PCode(filter(str.strip
, desc
.pcode
))
3511 operands
= Operands(insn
=name
, operands
=operands
)
3512 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3514 self
.__db
= dict(sorted(db
.items()))
3516 return super().__init
__()
3519 yield from self
.__db
.items()
3521 def __contains__(self
, key
):
3522 return self
.__db
.__contains
__(key
)
3524 def __getitem__(self
, key
):
3525 return self
.__db
.__getitem
__(key
)
3528 class FieldsDatabase
:
3531 df
= _DecodeFields()
3533 for (form
, fields
) in df
.instrs
.items():
3534 if form
in {"DQE", "TX"}:
3538 db
[_Form
[form
]] = Fields(fields
)
3542 return super().__init
__()
3544 def __getitem__(self
, key
):
3545 return self
.__db
.__getitem
__(key
)
3549 def __init__(self
, root
, mdwndb
):
3550 # The code below groups the instructions by name:section.
3551 # There can be multiple names for the same instruction.
3552 # The point is to capture different opcodes for the same instruction.
3554 records
= _collections
.defaultdict(set)
3555 path
= (root
/ "insndb.csv")
3556 with
open(path
, "r", encoding
="UTF-8") as stream
:
3557 for section
in sorted(parse(stream
, Section
.CSV
)):
3558 path
= (root
/ section
.csv
)
3560 section
.Mode
.INTEGER
: IntegerOpcode
,
3561 section
.Mode
.PATTERN
: PatternOpcode
,
3563 factory
= _functools
.partial(PPCRecord
.CSV
,
3564 opcode_cls
=opcode_cls
)
3565 with
open(path
, "r", encoding
="UTF-8") as stream
:
3566 for insn
in parse(stream
, factory
):
3567 for name
in insn
.names
:
3568 records
[name
].add(insn
)
3569 sections
[name
] = section
3571 items
= sorted(records
.items())
3573 for (name
, multirecord
) in items
:
3574 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3576 def exact_match(name
):
3577 record
= records
.get(name
)
3583 if not name
.endswith("l"):
3585 alias
= exact_match(name
[:-1])
3588 record
= records
[alias
]
3589 if "lk" not in record
.flags
:
3590 raise ValueError(record
)
3594 if not name
.endswith("a"):
3596 alias
= LK_match(name
[:-1])
3599 record
= records
[alias
]
3600 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3601 raise ValueError(record
)
3602 if "AA" not in mdwndb
[name
].operands
:
3603 raise ValueError(record
)
3607 if not name
.endswith("."):
3609 alias
= exact_match(name
[:-1])
3612 record
= records
[alias
]
3613 if record
.Rc
is _RCOE
.NONE
:
3614 raise ValueError(record
)
3618 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3619 for (name
, _
) in mdwndb
:
3620 if name
.startswith("sv."):
3623 for match
in matches
:
3625 if alias
is not None:
3629 section
= sections
[alias
]
3630 record
= records
[alias
]
3631 db
[name
] = (section
, record
)
3633 self
.__db
= dict(sorted(db
.items()))
3635 return super().__init
__()
3637 @_functools.lru_cache(maxsize
=512, typed
=False)
3638 def __getitem__(self
, key
):
3639 return self
.__db
.get(key
, (None, None))
3642 class SVP64Database
:
3643 def __init__(self
, root
, ppcdb
):
3645 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3646 for (prefix
, _
, names
) in _os
.walk(root
):
3647 prefix
= _pathlib
.Path(prefix
)
3648 for name
in filter(lambda name
: pattern
.match(name
), names
):
3649 path
= (prefix
/ _pathlib
.Path(name
))
3650 with
open(path
, "r", encoding
="UTF-8") as stream
:
3651 db
.update(parse(stream
, SVP64Record
.CSV
))
3652 db
= {record
.name
:record
for record
in db
}
3654 self
.__db
= dict(sorted(db
.items()))
3655 self
.__ppcdb
= ppcdb
3657 return super().__init
__()
3659 def __getitem__(self
, key
):
3660 (_
, record
) = self
.__ppcdb
[key
]
3664 for name
in record
.names
:
3665 record
= self
.__db
.get(name
, None)
3666 if record
is not None:
3672 class Records(tuple):
3673 def __new__(cls
, records
):
3674 return super().__new
__(cls
, sorted(records
))
3678 def __init__(self
, root
):
3679 root
= _pathlib
.Path(root
)
3680 mdwndb
= MarkdownDatabase()
3681 fieldsdb
= FieldsDatabase()
3682 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3683 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3687 opcodes
= _collections
.defaultdict(
3688 lambda: _collections
.defaultdict(set))
3690 for (name
, mdwn
) in mdwndb
:
3691 if name
.startswith("sv."):
3693 (section
, ppc
) = ppcdb
[name
]
3696 svp64
= svp64db
[name
]
3697 fields
= fieldsdb
[ppc
.form
]
3698 record
= Record(name
=name
,
3699 section
=section
, ppc
=ppc
, svp64
=svp64
,
3700 mdwn
=mdwn
, fields
=fields
)
3702 names
[record
.name
] = record
3703 opcodes
[section
][record
.PO
].add(record
)
3705 self
.__db
= Records(db
)
3706 self
.__names
= dict(sorted(names
.items()))
3707 self
.__opcodes
= dict(sorted(opcodes
.items()))
3709 return super().__init
__()
3712 return repr(self
.__db
)
3715 yield from self
.__db
3717 @_functools.lru_cache(maxsize
=None)
3718 def __contains__(self
, key
):
3719 return self
.__getitem
__(key
) is not None
3721 @_functools.lru_cache(maxsize
=None)
3722 def __getitem__(self
, key
):
3723 if isinstance(key
, SVP64Instruction
):
3726 if isinstance(key
, Instruction
):
3729 sections
= sorted(self
.__opcodes
)
3730 for section
in sections
:
3731 group
= self
.__opcodes
[section
]
3732 for record
in group
[PO
]:
3733 if record
.match(key
=key
):
3738 elif isinstance(key
, str):
3739 return self
.__names
.get(key
)
3741 raise ValueError("instruction or name expected")
3744 class Walker(mdis
.walker
.Walker
):
3745 @mdis.dispatcher
.Hook(Database
)
3746 def dispatch_database(self
, node
):
3747 yield from self(tuple(node
))