1 import collections
as _collections
2 import contextlib
as _contextlib
4 import dataclasses
as _dataclasses
6 import functools
as _functools
7 import inspect
as _inspect
9 import operator
as _operator
10 import pathlib
as _pathlib
12 import types
as _types
13 import typing
as _typing
15 import mdis
.dispatcher
19 from functools
import cached_property
21 from cached_property
import cached_property
23 from openpower
.decoder
.power_enums
import (
24 Function
as _Function
,
31 CRIn2Sel
as _CRIn2Sel
,
32 CROutSel
as _CROutSel
,
34 LDSTMode
as _LDSTMode
,
39 SVMaskSrc
as _SVMaskSrc
,
46 SVP64SubVL
as _SVP64SubVL
,
47 SVP64Pred
as _SVP64Pred
,
48 SVP64PredMode
as _SVP64PredMode
,
49 SVP64Width
as _SVP64Width
,
51 from openpower
.decoder
.selectable_int
import (
52 SelectableInt
as _SelectableInt
,
53 selectconcat
as _selectconcat
,
55 from openpower
.decoder
.power_fields
import (
58 DecodeFields
as _DecodeFields
,
60 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
63 class DataclassMeta(type):
64 def __new__(metacls
, name
, bases
, ns
):
65 cls
= super().__new
__(metacls
, name
, bases
, ns
)
66 return _dataclasses
.dataclass(cls
, eq
=True, frozen
=True)
69 class Dataclass(metaclass
=DataclassMeta
):
73 @_functools.total_ordering
74 class Style(_enum
.Enum
):
78 VERBOSE
= _enum
.auto()
80 def __lt__(self
, other
):
81 if not isinstance(other
, self
.__class
__):
83 return (self
.value
< other
.value
)
86 def dataclass(cls
, record
, keymap
=None, typemap
=None):
90 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
92 def transform(key_value
):
93 (key
, value
) = key_value
94 key
= keymap
.get(key
, key
)
95 hook
= typemap
.get(key
, lambda value
: value
)
96 if hook
is bool and value
in ("", "0"):
102 record
= dict(map(transform
, record
.items()))
103 for key
in frozenset(record
.keys()):
104 if record
[key
] == "":
110 @_functools.total_ordering
113 def __new__(cls
, value
):
114 if isinstance(value
, str):
115 value
= int(value
, 0)
116 if not isinstance(value
, int):
117 raise ValueError(value
)
119 if value
.bit_length() > 64:
120 raise ValueError(value
)
122 return super().__new
__(cls
, value
)
125 return self
.__repr
__()
128 return f
"{self:0{self.bit_length()}b}"
130 def bit_length(self
):
131 if super().bit_length() > 32:
135 class Value(Integer
):
141 def __init__(self
, value
, mask
):
144 return super().__init
__()
154 def __lt__(self
, other
):
155 if not isinstance(other
, Opcode
):
156 return NotImplemented
157 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
160 return (self
.value
& self
.mask
)
163 return int(self
).__index
__()
166 def pattern(value
, mask
, bit_length
):
167 for bit
in range(bit_length
):
168 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
170 elif (value
& (1 << (bit_length
- bit
- 1))):
175 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
177 def match(self
, key
):
178 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
181 @_functools.total_ordering
182 class IntegerOpcode(Opcode
):
183 def __init__(self
, value
):
184 if value
.startswith("0b"):
185 mask
= int(("1" * len(value
[2:])), 2)
189 value
= Opcode
.Value(value
)
190 mask
= Opcode
.Mask(mask
)
192 return super().__init
__(value
=value
, mask
=mask
)
195 @_functools.total_ordering
196 class PatternOpcode(Opcode
):
197 def __init__(self
, pattern
):
198 if not isinstance(pattern
, str):
199 raise ValueError(pattern
)
201 (value
, mask
) = (0, 0)
202 for symbol
in pattern
:
203 if symbol
not in {"0", "1", "-"}:
204 raise ValueError(pattern
)
205 value |
= (symbol
== "1")
206 mask |
= (symbol
!= "-")
212 value
= Opcode
.Value(value
)
213 mask
= Opcode
.Mask(mask
)
215 return super().__init
__(value
=value
, mask
=mask
)
218 class PPCRecord(Dataclass
):
219 class FlagsMeta(type):
234 class Flags(tuple, metaclass
=FlagsMeta
):
235 def __new__(cls
, flags
=frozenset()):
236 flags
= frozenset(flags
)
237 diff
= (flags
- frozenset(cls
))
239 raise ValueError(flags
)
240 return super().__new
__(cls
, sorted(flags
))
244 flags
: Flags
= Flags()
246 function
: _Function
= _Function
.NONE
247 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
248 in1
: _In1Sel
= _In1Sel
.NONE
249 in2
: _In2Sel
= _In2Sel
.NONE
250 in3
: _In3Sel
= _In3Sel
.NONE
251 out
: _OutSel
= _OutSel
.NONE
252 cr_in
: _CRInSel
= _CRInSel
.NONE
253 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
254 cr_out
: _CROutSel
= _CROutSel
.NONE
255 cry_in
: _CryIn
= _CryIn
.ZERO
256 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
257 upd
: _LDSTMode
= _LDSTMode
.NONE
258 Rc
: _RCOE
= _RCOE
.NONE
259 form
: _Form
= _Form
.NONE
265 "internal op": "intop",
269 "ldst len": "ldst_len",
271 "CONDITIONS": "conditions",
274 def __lt__(self
, other
):
275 if not isinstance(other
, self
.__class
__):
276 return NotImplemented
277 lhs
= (self
.opcode
, self
.comment
)
278 rhs
= (other
.opcode
, other
.comment
)
282 def CSV(cls
, record
, opcode_cls
):
283 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
284 typemap
["opcode"] = opcode_cls
286 if record
["CR in"] == "BA_BB":
287 record
["cr_in"] = "BA"
288 record
["cr_in2"] = "BB"
292 for flag
in frozenset(PPCRecord
.Flags
):
293 if bool(record
.pop(flag
, "")):
295 record
["flags"] = PPCRecord
.Flags(flags
)
297 return dataclass(cls
, record
,
298 keymap
=PPCRecord
.__KEYMAP
,
303 return frozenset(self
.comment
.split("=")[-1].split("/"))
306 class PPCMultiRecord(tuple):
307 def __getattr__(self
, attr
):
310 raise AttributeError(attr
)
311 return getattr(self
[0], attr
)
314 class SVP64Record(Dataclass
):
315 class ExtraMap(tuple):
317 @_dataclasses.dataclass(eq
=True, frozen
=True)
319 seltype
: _SelType
= _SelType
.NONE
320 reg
: _Reg
= _Reg
.NONE
323 return f
"{self.seltype.value}:{self.reg.name}"
325 def __new__(cls
, value
="0"):
326 if isinstance(value
, str):
327 def transform(value
):
328 (seltype
, reg
) = value
.split(":")
329 seltype
= _SelType(seltype
)
331 return cls
.Entry(seltype
=seltype
, reg
=reg
)
336 value
= map(transform
, value
.split(";"))
338 return super().__new
__(cls
, value
)
341 return repr(list(self
))
343 def __new__(cls
, value
=tuple()):
347 return super().__new
__(cls
, map(cls
.Extra
, value
))
350 return repr({index
:self
[index
] for index
in range(0, 4)})
353 ptype
: _SVPType
= _SVPType
.NONE
354 etype
: _SVEType
= _SVEType
.NONE
355 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
356 in1
: _In1Sel
= _In1Sel
.NONE
357 in2
: _In2Sel
= _In2Sel
.NONE
358 in3
: _In3Sel
= _In3Sel
.NONE
359 out
: _OutSel
= _OutSel
.NONE
360 out2
: _OutSel
= _OutSel
.NONE
361 cr_in
: _CRInSel
= _CRInSel
.NONE
362 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
363 cr_out
: _CROutSel
= _CROutSel
.NONE
364 extra
: ExtraMap
= ExtraMap()
366 mode
: _SVMode
= _SVMode
.NORMAL
370 "CONDITIONS": "conditions",
379 def CSV(cls
, record
):
380 record
["insn"] = record
["insn"].split("=")[-1]
382 for key
in frozenset({
383 "in1", "in2", "in3", "CR in",
384 "out", "out2", "CR out",
390 if record
["CR in"] == "BA_BB":
391 record
["cr_in"] = "BA"
392 record
["cr_in2"] = "BB"
396 for idx
in range(0, 4):
397 extra
.append(record
.pop(f
"{idx}"))
399 record
["extra"] = cls
.ExtraMap(extra
)
401 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
406 "in1", "in2", "in3", "cr_in", "cr_in2",
407 "out", "out2", "cr_out",
422 for index
in range(0, 4):
423 for entry
in self
.extra
[index
]:
424 extras
[entry
.seltype
][entry
.reg
] = idxmap
[index
]
426 for (seltype
, regs
) in extras
.items():
427 idx
= regs
.get(reg
, _SVExtra
.NONE
)
428 if idx
is not _SVExtra
.NONE
:
429 yield (reg
, seltype
, idx
)
436 # has the word "in", it is a SelType.SRC "out" -> DST
437 # in1/2/3 and CR in are SRC, and must match only against "s:NN"
438 # out/out1 and CR out are DST, and must match only against "d:NN"
439 keytype
= _SelType
.SRC
if ("in" in key
) else _SelType
.DST
440 sel
= sels
[key
] = getattr(self
, key
)
441 reg
= regs
[key
] = _Reg(sel
)
442 seltypes
[key
] = _SelType
.NONE
443 idxs
[key
] = _SVExtra
.NONE
444 for (reg
, seltype
, idx
) in extra(reg
.alias
):
445 if keytype
!= seltype
: # only check SRC-to-SRC and DST-to-DST
447 if idx
!= idxs
[key
] and idxs
[key
] is not _SVExtra
.NONE
:
448 raise ValueError(idx
)
451 seltypes
[key
] = seltype
453 if sels
["cr_in"] is _CRInSel
.BA_BB
:
454 sels
["cr_in"] = _CRIn2Sel
.BA
455 sels
["cr_in2"] = _CRIn2Sel
.BB
456 idxs
["cr_in2"] = idxs
["cr_in"]
457 for key
in ("cr_in", "cr_in2"):
458 regs
[key
] = _Reg(sels
[key
])
459 seltype
[key
] = _SelType
.SRC
466 "seltype": seltypes
[key
],
470 return _types
.MappingProxyType(records
)
472 extra_idx_in1
= property(lambda self
: self
.extras
["in1"]["idx"])
473 extra_idx_in2
= property(lambda self
: self
.extras
["in2"]["idx"])
474 extra_idx_in3
= property(lambda self
: self
.extras
["in3"]["idx"])
475 extra_idx_out
= property(lambda self
: self
.extras
["out"]["idx"])
476 extra_idx_out2
= property(lambda self
: self
.extras
["out2"]["idx"])
477 extra_idx_cr_in
= property(lambda self
: self
.extras
["cr_in"]["idx"])
478 extra_idx_cr_in2
= property(lambda self
: self
.extras
["cr_in2"]["idx"])
479 extra_idx_cr_out
= property(lambda self
: self
.extras
["cr_out"]["idx"])
484 for idx
in range(0, 4):
485 for entry
in self
.extra
[idx
]:
486 if entry
.seltype
is _SelType
.DST
:
487 if extra
is not None:
488 raise ValueError(self
.svp64
)
492 if _RegType(extra
.reg
) not in (_RegType
.CR_3BIT
, _RegType
.CR_5BIT
):
493 raise ValueError(self
.svp64
)
498 def extra_CR_3bit(self
):
499 return (_RegType(self
.extra_CR
.reg
) is _RegType
.CR_3BIT
)
502 class Section(Dataclass
):
503 class Path(type(_pathlib
.Path("."))):
507 def __init__(self
, value
=(0, 32)):
508 if isinstance(value
, str):
509 (start
, end
) = map(int, value
.split(":"))
512 if start
< 0 or end
< 0 or start
>= end
:
513 raise ValueError(value
)
518 return super().__init
__()
521 return (self
.__end
- self
.__start
+ 1)
524 return f
"[{self.__start}:{self.__end}]"
527 yield from range(self
.start
, (self
.end
+ 1))
529 def __reversed__(self
):
530 return tuple(reversed(tuple(self
)))
540 class Mode(_enum
.Enum
):
541 INTEGER
= _enum
.auto()
542 PATTERN
= _enum
.auto()
545 def _missing_(cls
, value
):
546 if isinstance(value
, str):
547 return cls
[value
.upper()]
548 return super()._missing
_(value
)
551 def __new__(cls
, value
=None):
552 if isinstance(value
, str):
553 if value
.upper() == "NONE":
556 value
= int(value
, 0)
560 return super().__new
__(cls
, value
)
566 return (bin(self
) if self
else "None")
568 class Opcode(IntegerOpcode
):
571 @_functools.total_ordering
572 class Priority(_enum
.Enum
):
578 def _missing_(cls
, value
):
579 if isinstance(value
, str):
580 value
= value
.upper()
584 return super()._missing
_(value
)
586 def __lt__(self
, other
):
587 if not isinstance(other
, self
.__class
__):
588 return NotImplemented
590 # NOTE: the order is inversed, LOW < NORMAL < HIGH
591 return (self
.value
> other
.value
)
597 opcode
: Opcode
= None
598 priority
: Priority
= Priority
.NORMAL
600 def __lt__(self
, other
):
601 if not isinstance(other
, self
.__class
__):
602 return NotImplemented
603 return (self
.priority
< other
.priority
)
606 def CSV(cls
, record
):
607 keymap
= {"path": "csv"}
608 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
609 if record
["opcode"] == "NONE":
610 typemap
["opcode"] = lambda _
: None
612 return dataclass(cls
, record
, typemap
=typemap
, keymap
=keymap
)
616 def __init__(self
, items
):
617 if isinstance(items
, dict):
618 items
= items
.items()
621 (name
, bitrange
) = item
622 return (name
, tuple(bitrange
.values()))
624 mapping
= dict(map(transform
, items
))
626 return super().__init
__(mapping
)
629 return hash(tuple(sorted(self
.items())))
632 yield from self
.__mapping
.items()
635 class Operands(dict):
647 def __init__(self
, insn
, operands
):
649 "b": {"target_addr": TargetAddrOperandLI
},
650 "ba": {"target_addr": TargetAddrOperandLI
},
651 "bl": {"target_addr": TargetAddrOperandLI
},
652 "bla": {"target_addr": TargetAddrOperandLI
},
653 "bc": {"target_addr": TargetAddrOperandBD
},
654 "bca": {"target_addr": TargetAddrOperandBD
},
655 "bcl": {"target_addr": TargetAddrOperandBD
},
656 "bcla": {"target_addr": TargetAddrOperandBD
},
657 "addpcis": {"D": DOperandDX
},
658 "fishmv": {"D": DOperandDX
},
659 "fmvis": {"D": DOperandDX
},
662 "SVi": NonZeroOperand
,
663 "SVd": NonZeroOperand
,
664 "SVxd": NonZeroOperand
,
665 "SVyd": NonZeroOperand
,
666 "SVzd": NonZeroOperand
,
668 "D": SignedImmediateOperand
,
672 "SIM": SignedOperand
,
673 "SVD": SignedOperand
,
674 "SVDS": SignedOperand
,
675 "RSp": GPRPairOperand
,
676 "RTp": GPRPairOperand
,
677 "FRAp": FPRPairOperand
,
678 "FRBp": FPRPairOperand
,
679 "FRSp": FPRPairOperand
,
680 "FRTp": FPRPairOperand
,
682 custom_immediates
= {
688 for operand
in operands
:
692 (name
, value
) = operand
.split("=")
693 mapping
[name
] = (StaticOperand
, (
695 ("value", int(value
)),
699 if name
.endswith(")"):
700 name
= name
.replace("(", " ").replace(")", "")
701 (imm_name
, _
, name
) = name
.partition(" ")
705 if imm_name
is not None:
706 imm_cls
= custom_immediates
.get(imm_name
, ImmediateOperand
)
708 if insn
in custom_insns
and name
in custom_insns
[insn
]:
709 cls
= custom_insns
[insn
][name
]
710 elif name
in custom_fields
:
711 cls
= custom_fields
[name
]
712 elif name
in _Reg
.__members
__:
714 if reg
in self
.__class
__.__GPR
_PAIRS
:
716 elif reg
in self
.__class
__.__FPR
_PAIRS
:
719 regtype
= _RegType
[name
]
720 if regtype
is _RegType
.GPR
:
722 elif regtype
is _RegType
.FPR
:
724 elif regtype
is _RegType
.CR_3BIT
:
726 elif regtype
is _RegType
.CR_5BIT
:
729 if imm_name
is not None:
730 mapping
[imm_name
] = (imm_cls
, (
733 mapping
[name
] = (cls
, (
737 return super().__init
__(mapping
)
740 for (cls
, kwargs
) in self
.values():
741 yield (cls
, dict(kwargs
))
744 return hash(tuple(sorted(self
.items())))
748 return tuple(filter(lambda pair
: issubclass(pair
[0], StaticOperand
), self
))
752 return tuple(filter(lambda pair
: issubclass(pair
[0], DynamicOperand
), self
))
755 class Arguments(tuple):
756 def __new__(cls
, record
, arguments
, operands
):
757 operands
= iter(tuple(operands
))
758 arguments
= iter(tuple(arguments
))
763 operand
= next(operands
)
764 except StopIteration:
768 argument
= next(arguments
)
769 except StopIteration:
770 raise ValueError("operands count mismatch")
772 if isinstance(operand
, ImmediateOperand
):
773 argument
= argument
.replace("(", " ").replace(")", "")
774 (imm_argument
, _
, argument
) = argument
.partition(" ")
776 (imm_operand
, operand
) = (operand
, next(operands
))
777 except StopIteration:
778 raise ValueError("operands count mismatch")
779 items
.append((imm_argument
, imm_operand
))
780 items
.append((argument
, operand
))
784 except StopIteration:
787 raise ValueError("operands count mismatch")
789 return super().__new
__(cls
, items
)
796 class MarkdownRecord(Dataclass
):
801 @_functools.total_ordering
802 class Record(Dataclass
):
808 svp64
: SVP64Record
= None
812 if self
.svp64
is not None:
813 return self
.svp64
.extras
815 return _types
.MappingProxyType({})
819 return self
.mdwn
.pcode
821 def __lt__(self
, other
):
822 if not isinstance(other
, Record
):
823 return NotImplemented
824 lhs
= (min(self
.opcodes
), self
.name
)
825 rhs
= (min(other
.opcodes
), other
.name
)
830 return (self
.static_operands
+ self
.dynamic_operands
)
833 def static_operands(self
):
835 operands
.append(POStaticOperand(record
=self
, value
=self
.PO
))
837 operands
.append(XOStaticOperand(
839 value
=ppc
.opcode
.value
,
840 span
=self
.section
.bitsel
,
842 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
843 operands
.append(cls(record
=self
, **kwargs
))
844 return tuple(operands
)
847 def dynamic_operands(self
):
849 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
850 operands
.append(cls(record
=self
, **kwargs
))
851 return tuple(operands
)
856 return int("".join(str(int(mapping
[bit
])) \
857 for bit
in sorted(mapping
)), 2)
859 def PO_XO(value
, mask
, opcode
, bits
):
862 for (src
, dst
) in enumerate(reversed(bits
)):
863 value
[dst
] = ((opcode
.value
& (1 << src
)) != 0)
864 mask
[dst
] = ((opcode
.mask
& (1 << src
)) != 0)
867 def PO(value
, mask
, opcode
, bits
):
868 return PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
870 def XO(value
, mask
, opcode
, bits
):
871 (value
, mask
) = PO_XO(value
=value
, mask
=mask
,
872 opcode
=opcode
, bits
=bits
)
873 for (op_cls
, op_kwargs
) in self
.mdwn
.operands
.static
:
874 operand
= op_cls(record
=self
, **op_kwargs
)
875 for (src
, dst
) in enumerate(reversed(operand
.span
)):
876 value
[dst
] = ((operand
.value
& (1 << src
)) != 0)
881 value
= {bit
:False for bit
in range(32)}
882 mask
= {bit
:False for bit
in range(32)}
883 if self
.section
.opcode
is not None:
884 (value
, mask
) = PO(value
=value
, mask
=mask
,
885 opcode
=self
.section
.opcode
, bits
=range(0, 6))
887 pairs
.append(XO(value
=value
, mask
=mask
,
888 opcode
=ppc
.opcode
, bits
=self
.section
.bitsel
))
891 for (value
, mask
) in pairs
:
892 value
= Opcode
.Value(binary(value
))
893 mask
= Opcode
.Mask(binary(mask
))
894 result
.append(Opcode(value
=value
, mask
=mask
))
900 opcode
= self
.section
.opcode
902 opcode
= self
.ppc
[0].opcode
903 if isinstance(opcode
, PatternOpcode
):
904 value
= int(opcode
.value
)
905 bits
= opcode
.value
.bit_length()
906 return int(_SelectableInt(value
=value
, bits
=bits
)[0:6])
908 return int(opcode
.value
)
912 return tuple(ppc
.opcode
for ppc
in self
.ppc
)
914 def match(self
, key
):
915 for opcode
in self
.opcodes
:
916 if opcode
.match(key
):
923 return self
.svp64
.mode
943 if self
.svp64
is None:
949 return self
.ppc
.cr_in
953 return self
.ppc
.cr_in2
957 return self
.ppc
.cr_out
959 ptype
= property(lambda self
: self
.svp64
.ptype
)
960 etype
= property(lambda self
: self
.svp64
.etype
)
962 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
963 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
964 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
965 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
966 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
967 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
968 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
969 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
971 def __contains__(self
, key
):
972 return self
.mdwn
.operands
.__contains
__(key
)
974 def __getitem__(self
, key
):
975 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
976 return cls(record
=self
, **dict(kwargs
))
982 return self
["Rc"].value
986 def __init__(self
, record
, name
):
987 self
.__record
= record
991 yield ("record", self
.record
)
992 yield ("name", self
.__name
)
995 return f
"{self.__class__.__name__}({self.name})"
1003 return self
.__record
1007 return self
.record
.fields
[self
.name
]
1009 def assemble(self
, insn
):
1010 raise NotImplementedError()
1012 def disassemble(self
, insn
,
1013 style
=Style
.NORMAL
, indent
=""):
1014 raise NotImplementedError()
1017 class DynamicOperand(Operand
):
1018 def assemble(self
, insn
, value
):
1020 if isinstance(value
, str):
1021 value
= int(value
, 0)
1023 raise ValueError("signed operands not allowed")
1026 def disassemble(self
, insn
,
1027 style
=Style
.NORMAL
, indent
=""):
1031 if style
>= Style
.VERBOSE
:
1032 span
= map(str, span
)
1033 yield f
"{indent}{self.name}"
1034 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1035 yield f
"{indent}{indent}{', '.join(span)}"
1037 yield str(int(value
))
1040 class SignedOperand(DynamicOperand
):
1041 def assemble(self
, insn
, value
):
1042 if isinstance(value
, str):
1043 value
= int(value
, 0)
1044 return super().assemble(value
=value
, insn
=insn
)
1046 def assemble(self
, insn
, value
):
1048 if isinstance(value
, str):
1049 value
= int(value
, 0)
1052 def disassemble(self
, insn
,
1053 style
=Style
.NORMAL
, indent
=""):
1055 value
= insn
[span
].to_signed_int()
1056 sign
= "-" if (value
< 0) else ""
1059 if style
>= Style
.VERBOSE
:
1060 span
= map(str, span
)
1061 yield f
"{indent}{self.name}"
1062 yield f
"{indent}{indent}{sign}{value}"
1063 yield f
"{indent}{indent}{', '.join(span)}"
1065 yield f
"{sign}{value}"
1068 class StaticOperand(Operand
):
1069 def __init__(self
, record
, name
, value
):
1070 self
.__value
= value
1071 return super().__init
__(record
=record
, name
=name
)
1074 yield ("value", self
.__value
)
1075 yield from super().__iter
__()
1078 return f
"{self.__class__.__name__}({self.name}, value={self.value})"
1084 def assemble(self
, insn
):
1085 insn
[self
.span
] = self
.value
1087 def disassemble(self
, insn
,
1088 style
=Style
.NORMAL
, indent
=""):
1092 if style
>= Style
.VERBOSE
:
1093 span
= map(str, span
)
1094 yield f
"{indent}{self.name}"
1095 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1096 yield f
"{indent}{indent}{', '.join(span)}"
1098 yield str(int(value
))
1101 class SpanStaticOperand(StaticOperand
):
1102 def __init__(self
, record
, name
, value
, span
):
1103 self
.__span
= tuple(span
)
1104 return super().__init
__(record
=record
, name
=name
, value
=value
)
1107 yield ("span", self
.__span
)
1108 yield from super().__iter
__()
1115 class POStaticOperand(SpanStaticOperand
):
1116 def __init__(self
, record
, value
):
1117 return super().__init
__(record
=record
, name
="PO",
1118 value
=value
, span
=range(0, 6))
1121 for (key
, value
) in super().__iter
__():
1122 if key
not in {"name", "span"}:
1126 class XOStaticOperand(SpanStaticOperand
):
1127 def __init__(self
, record
, value
, span
):
1128 bits
= record
.section
.bitsel
1129 value
= _SelectableInt(value
=value
, bits
=len(bits
))
1130 span
= dict(zip(bits
, range(len(bits
))))
1131 span_rev
= {value
:key
for (key
, value
) in span
.items()}
1133 # This part is tricky: we cannot use record.operands,
1134 # as this code is called by record.static_operands method.
1135 for (cls
, kwargs
) in record
.mdwn
.operands
:
1136 operand
= cls(record
=record
, **kwargs
)
1137 for idx
in operand
.span
:
1138 rev
= span
.pop(idx
, None)
1140 span_rev
.pop(rev
, None)
1142 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1143 span
= tuple(span
.keys())
1145 return super().__init
__(record
=record
, name
="XO",
1146 value
=value
, span
=span
)
1149 for (key
, value
) in super().__iter
__():
1150 if key
not in {"name"}:
1154 class ImmediateOperand(DynamicOperand
):
1158 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1162 class NonZeroOperand(DynamicOperand
):
1163 def assemble(self
, insn
, value
):
1164 if isinstance(value
, str):
1165 value
= int(value
, 0)
1166 if not isinstance(value
, int):
1167 raise ValueError("non-integer operand")
1169 raise ValueError("non-zero operand")
1171 return super().assemble(value
=value
, insn
=insn
)
1173 def disassemble(self
, insn
,
1174 style
=Style
.NORMAL
, indent
=""):
1178 if style
>= Style
.VERBOSE
:
1179 span
= map(str, span
)
1180 yield f
"{indent}{self.name}"
1181 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1182 yield f
"{indent}{indent}{', '.join(span)}"
1184 yield str(int(value
) + 1)
1187 class ExtendableOperand(DynamicOperand
):
1188 def sv_spec_enter(self
, value
, span
):
1189 return (value
, span
)
1191 def sv_spec(self
, insn
):
1195 span
= tuple(map(str, span
))
1197 if isinstance(insn
, SVP64Instruction
):
1198 (origin_value
, origin_span
) = (value
, span
)
1199 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1201 for extra_idx
in self
.extra_idx
:
1202 if self
.record
.etype
is _SVEType
.EXTRA3
:
1203 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1204 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1205 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1207 raise ValueError(self
.record
.etype
)
1210 vector
= bool(spec
[0])
1211 spec_span
= spec
.__class
__
1212 if self
.record
.etype
is _SVEType
.EXTRA3
:
1213 spec_span
= tuple(map(str, spec_span
[1, 2]))
1215 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1216 spec_span
= tuple(map(str, spec_span
[1,]))
1217 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1220 spec_span
= (spec_span
+ ("{0}",))
1222 spec_span
= (("{0}",) + spec_span
)
1224 raise ValueError(self
.record
.etype
)
1226 vector_shift
= (2 + (5 - value
.bits
))
1227 scalar_shift
= value
.bits
1228 spec_shift
= (5 - value
.bits
)
1230 bits
= (len(span
) + len(spec_span
))
1231 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1232 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1234 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1235 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1237 value
= ((spec
<< scalar_shift
) | value
)
1238 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1240 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1241 origin_value
=origin_value
, origin_span
=origin_span
)
1243 return (vector
, value
, span
)
1245 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1246 return (value
, span
)
1249 def extra_idx(self
):
1250 for (key
, record
) in self
.record
.svp64
.extras
.items():
1251 if record
["reg"].alias
is self
.extra_reg
.alias
:
1255 def extra_reg(self
):
1256 return _Reg(self
.name
)
1258 def remap(self
, value
, vector
):
1259 raise NotImplementedError()
1261 def assemble(self
, value
, insn
, prefix
):
1264 if isinstance(value
, str):
1265 value
= value
.lower()
1266 if value
.startswith("%"):
1268 if value
.startswith("*"):
1269 if not isinstance(insn
, SVP64Instruction
):
1270 raise ValueError(value
)
1273 if value
.startswith(prefix
):
1274 if (self
.extra_reg
.or_zero
and (value
== f
"{prefix}0")):
1275 raise ValueError(value
)
1276 value
= value
[len(prefix
):]
1277 value
= int(value
, 0)
1279 if isinstance(insn
, SVP64Instruction
):
1280 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1282 for extra_idx
in self
.extra_idx
:
1283 if self
.record
.etype
is _SVEType
.EXTRA3
:
1284 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1285 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1286 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1288 raise ValueError(self
.record
.etype
)
1290 return super().assemble(value
=value
, insn
=insn
)
1292 def disassemble(self
, insn
,
1293 style
=Style
.NORMAL
, prefix
="", indent
=""):
1294 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1296 if (self
.extra_reg
.or_zero
and (value
== 0)):
1299 if style
>= Style
.VERBOSE
:
1300 mode
= "vector" if vector
else "scalar"
1301 yield f
"{indent}{self.name} ({mode})"
1302 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1303 yield f
"{indent}{indent}{', '.join(span)}"
1304 if isinstance(insn
, SVP64Instruction
):
1305 for extra_idx
in frozenset(self
.extra_idx
):
1306 if self
.record
.etype
is _SVEType
.NONE
:
1307 yield f
"{indent}{indent}extra[none]"
1309 etype
= repr(self
.record
.etype
).lower()
1310 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1312 vector
= "*" if vector
else ""
1313 yield f
"{vector}{prefix}{int(value)}"
1316 class SimpleRegisterOperand(ExtendableOperand
):
1317 def remap(self
, value
, vector
):
1319 extra
= (value
& 0b11)
1320 value
= (value
>> 2)
1322 extra
= (value
>> 5)
1323 value
= (value
& 0b11111)
1325 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1326 # (and shrink to a single bit if ok)
1327 if self
.record
.etype
is _SVEType
.EXTRA2
:
1329 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1330 assert (extra
& 0b01) == 0, \
1331 ("vector field %s cannot fit into EXTRA2" % value
)
1332 extra
= (0b10 |
(extra
>> 1))
1334 # range is r0-r63 in increments of 1
1335 assert (extra
>> 1) == 0, \
1336 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1338 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1340 # EXTRA3 vector bit needs marking
1343 raise ValueError(self
.record
.etype
)
1345 return (value
, extra
)
1348 class GPROperand(SimpleRegisterOperand
):
1349 def assemble(self
, insn
, value
):
1350 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1352 def disassemble(self
, insn
,
1353 style
=Style
.NORMAL
, indent
=""):
1354 prefix
= "" if (style
<= Style
.SHORT
) else "r"
1355 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1356 style
=style
, indent
=indent
)
1359 class GPRPairOperand(GPROperand
):
1363 class FPROperand(SimpleRegisterOperand
):
1364 def assemble(self
, insn
, value
):
1365 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1367 def disassemble(self
, insn
,
1368 style
=Style
.NORMAL
, indent
=""):
1369 prefix
= "" if (style
<= Style
.SHORT
) else "f"
1370 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1371 style
=style
, indent
=indent
)
1374 class FPRPairOperand(FPROperand
):
1378 class ConditionRegisterFieldOperand(ExtendableOperand
):
1379 def pattern(name_pattern
):
1380 (name
, pattern
) = name_pattern
1381 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1390 CR
= r
"(?:CR|cr)([0-9]+)"
1392 BIT
= rf
"({'|'.join(CONDS.keys())})"
1393 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1394 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1395 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1396 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1397 XCR
= fr
"{CR}\.{BIT}"
1398 PATTERNS
= tuple(map(pattern
, (
1403 ("BIT+CR", (LBIT
+ CR
)),
1404 ("CR+BIT", (CR
+ RBIT
)),
1405 ("BIT+CR*N", (LBIT
+ CRN
)),
1406 ("CR*N+BIT", (CRN
+ RBIT
)),
1407 ("BIT+N*CR", (LBIT
+ NCR
)),
1408 ("N*CR+BIT", (NCR
+ RBIT
)),
1411 def remap(self
, value
, vector
, regtype
):
1412 if regtype
is _RegType
.CR_5BIT
:
1413 subvalue
= (value
& 0b11)
1417 extra
= (value
& 0b1111)
1420 extra
= (value
>> 3)
1423 if self
.record
.etype
is _SVEType
.EXTRA2
:
1425 assert (extra
& 0b111) == 0, \
1426 "vector CR cannot fit into EXTRA2"
1427 extra
= (0b10 |
(extra
>> 3))
1429 assert (extra
>> 1) == 0, \
1430 "scalar CR cannot fit into EXTRA2"
1432 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1434 assert (extra
& 0b11) == 0, \
1435 "vector CR cannot fit into EXTRA3"
1436 extra
= (0b100 |
(extra
>> 2))
1438 assert (extra
>> 2) == 0, \
1439 "scalar CR cannot fit into EXTRA3"
1442 if regtype
is _RegType
.CR_5BIT
:
1443 value
= ((value
<< 2) | subvalue
)
1445 return (value
, extra
)
1447 def assemble(self
, insn
, value
):
1448 if isinstance(value
, str):
1451 if value
.startswith("*"):
1452 if not isinstance(insn
, SVP64Instruction
):
1453 raise ValueError(value
)
1457 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1458 match
= pattern
.match(value
)
1459 if match
is not None:
1460 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1461 values
= match
.groups()
1462 match
= dict(zip(keys
, values
))
1463 CR
= int(match
["CR"])
1467 N
= int(match
.get("N", "1"))
1468 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1469 value
= ((CR
* N
) + BIT
)
1476 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1478 def disassemble(self
, insn
,
1479 style
=Style
.NORMAL
, prefix
="", indent
=""):
1480 (vector
, value
, span
) = self
.sv_spec(insn
=insn
)
1482 if style
>= Style
.VERBOSE
:
1483 mode
= "vector" if vector
else "scalar"
1484 yield f
"{indent}{self.name} ({mode})"
1485 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1486 yield f
"{indent}{indent}{', '.join(span)}"
1487 if isinstance(insn
, SVP64Instruction
):
1488 for extra_idx
in frozenset(self
.extra_idx
):
1489 if self
.record
.etype
is _SVEType
.NONE
:
1490 yield f
"{indent}{indent}extra[none]"
1492 etype
= repr(self
.record
.etype
).lower()
1493 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1495 vector
= "*" if vector
else ""
1496 CR
= int(value
>> 2)
1498 cond
= ("lt", "gt", "eq", "so")[CC
]
1499 if style
>= Style
.NORMAL
:
1501 if isinstance(insn
, SVP64Instruction
):
1502 yield f
"{vector}cr{CR}.{cond}"
1504 yield f
"4*cr{CR}+{cond}"
1508 yield f
"{vector}{prefix}{int(value)}"
1511 class CR3Operand(ConditionRegisterFieldOperand
):
1512 def remap(self
, value
, vector
):
1513 return super().remap(value
=value
, vector
=vector
,
1514 regtype
=_RegType
.CR_3BIT
)
1517 class CR5Operand(ConditionRegisterFieldOperand
):
1518 def remap(self
, value
, vector
):
1519 return super().remap(value
=value
, vector
=vector
,
1520 regtype
=_RegType
.CR_5BIT
)
1522 def sv_spec_enter(self
, value
, span
):
1523 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1524 return (value
, span
)
1526 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1527 value
= _selectconcat(value
, origin_value
[3:5])
1529 return (value
, span
)
1532 class EXTSOperand(SignedOperand
):
1533 field
: str # real name to report
1534 nz
: int = 0 # number of zeros
1535 fmt
: str = "d" # integer formatter
1537 def __init__(self
, record
, name
, field
, nz
=0, fmt
="d"):
1538 self
.__field
= field
1541 return super().__init
__(record
=record
, name
=name
)
1557 return self
.record
.fields
[self
.field
]
1559 def assemble(self
, insn
, value
):
1561 if isinstance(value
, str):
1562 value
= int(value
, 0)
1563 insn
[span
] = (value
>> self
.nz
)
1565 def disassemble(self
, insn
,
1566 style
=Style
.NORMAL
, indent
=""):
1568 value
= insn
[span
].to_signed_int()
1569 sign
= "-" if (value
< 0) else ""
1570 value
= (abs(value
) << self
.nz
)
1572 if style
>= Style
.VERBOSE
:
1573 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1574 zeros
= ("0" * self
.nz
)
1575 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1576 yield f
"{indent * 1}{hint}"
1577 yield f
"{indent * 2}{self.field}"
1578 yield f
"{indent * 3}{sign}{value:{self.fmt}}"
1579 yield f
"{indent * 3}{', '.join(span)}"
1581 yield f
"{sign}{value:{self.fmt}}"
1584 class TargetAddrOperand(EXTSOperand
):
1585 def __init__(self
, record
, name
, field
):
1586 return super().__init
__(record
=record
, name
=name
, field
=field
,
1590 class TargetAddrOperandLI(TargetAddrOperand
):
1591 def __init__(self
, record
, name
):
1592 return super().__init
__(record
=record
, name
=name
, field
="LI")
1595 class TargetAddrOperandBD(TargetAddrOperand
):
1596 def __init__(self
, record
, name
):
1597 return super().__init
__(record
=record
, name
=name
, field
="BD")
1600 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1601 def __init__(self
, record
, name
):
1602 return super().__init
__(record
=record
, name
=name
, field
="DS", nz
=2)
1605 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1606 def __init__(self
, record
, name
):
1607 return super().__init
__(record
=record
, name
=name
, field
="DQ", nz
=4)
1610 class DOperandDX(SignedOperand
):
1613 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1614 operands
= map(cls
, ("d0", "d1", "d2"))
1615 spans
= map(lambda operand
: operand
.span
, operands
)
1616 return sum(spans
, tuple())
1618 def disassemble(self
, insn
,
1619 style
=Style
.NORMAL
, indent
=""):
1621 value
= insn
[span
].to_signed_int()
1622 sign
= "-" if (value
< 0) else ""
1625 if style
>= Style
.VERBOSE
:
1632 for (subname
, subspan
) in mapping
.items():
1633 operand
= DynamicOperand(name
=subname
)
1635 span
= map(str, span
)
1636 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1637 yield f
"{indent}{indent}{indent}{sign}{value}"
1638 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1640 yield f
"{sign}{value}"
1643 class Instruction(_Mapping
):
1645 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1646 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1647 raise ValueError(bits
)
1649 if isinstance(value
, bytes
):
1650 if ((len(value
) * 8) != bits
):
1651 raise ValueError(f
"bit length mismatch")
1652 value
= int.from_bytes(value
, byteorder
=byteorder
)
1654 if isinstance(value
, int):
1655 value
= _SelectableInt(value
=value
, bits
=bits
)
1656 elif isinstance(value
, Instruction
):
1657 value
= value
.storage
1659 if not isinstance(value
, _SelectableInt
):
1660 raise ValueError(value
)
1663 if len(value
) != bits
:
1664 raise ValueError(value
)
1666 value
= _SelectableInt(value
=value
, bits
=bits
)
1668 return cls(storage
=value
)
1671 return hash(int(self
))
1673 def __getitem__(self
, key
):
1674 return self
.storage
.__getitem
__(key
)
1676 def __setitem__(self
, key
, value
):
1677 return self
.storage
.__setitem
__(key
, value
)
1679 def bytes(self
, byteorder
="little"):
1680 nr_bytes
= (len(self
.__class
__) // 8)
1681 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1684 def record(cls
, db
, entry
):
1687 raise KeyError(entry
)
1691 def operands(cls
, record
):
1692 yield from record
.operands
1695 def static_operands(cls
, record
):
1696 return filter(lambda operand
: isinstance(operand
, StaticOperand
),
1697 cls
.operands(record
=record
))
1700 def dynamic_operands(cls
, record
):
1701 return filter(lambda operand
: isinstance(operand
, DynamicOperand
),
1702 cls
.operands(record
=record
))
1704 def spec(self
, record
, prefix
):
1705 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1706 self
.spec_dynamic_operands(record
=record
)))
1708 static_operands
= []
1709 for (name
, value
) in self
.spec_static_operands(record
=record
):
1710 static_operands
.append(f
"{name}={value}")
1713 if dynamic_operands
:
1715 operands
+= ",".join(dynamic_operands
)
1718 operands
+= " ".join(static_operands
)
1720 return f
"{prefix}{record.name}{operands}"
1722 def spec_static_operands(self
, record
):
1723 for operand
in self
.static_operands(record
=record
):
1724 if not isinstance(operand
, (POStaticOperand
, XOStaticOperand
)):
1725 yield (operand
.name
, operand
.value
)
1727 def spec_dynamic_operands(self
, record
, style
=Style
.NORMAL
):
1731 for operand
in self
.dynamic_operands(record
=record
):
1733 value
= " ".join(operand
.disassemble(insn
=self
,
1734 style
=min(style
, Style
.NORMAL
)))
1736 name
= f
"{imm_name}({name})"
1737 value
= f
"{imm_value}({value})"
1739 if isinstance(operand
, ImmediateOperand
):
1747 def assemble(cls
, record
, arguments
=None):
1748 if arguments
is None:
1751 insn
= cls
.integer(value
=0)
1753 for operand
in cls
.static_operands(record
=record
):
1754 operand
.assemble(insn
=insn
)
1756 arguments
= Arguments(record
=record
,
1757 arguments
=arguments
, operands
=cls
.dynamic_operands(record
=record
))
1758 for (value
, operand
) in arguments
:
1759 operand
.assemble(insn
=insn
, value
=value
)
1763 def disassemble(self
, record
,
1765 style
=Style
.NORMAL
):
1766 raise NotImplementedError()
1769 class WordInstruction(Instruction
):
1770 _
: _Field
= range(0, 32)
1771 PO
: _Field
= range(0, 6)
1774 def integer(cls
, value
, byteorder
="little"):
1775 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1780 for idx
in range(32):
1781 bit
= int(self
[idx
])
1783 return "".join(map(str, bits
))
1785 def disassemble(self
, record
,
1787 style
=Style
.NORMAL
):
1788 if style
<= Style
.SHORT
:
1791 blob
= self
.bytes(byteorder
=byteorder
)
1792 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1796 yield f
"{blob}.long 0x{int(self):08x}"
1799 # awful temporary hack: workaround for ld-update
1800 # https://bugs.libre-soc.org/show_bug.cgi?id=1056#c2
1801 # XXX TODO must check that *EXTENDED* RA != extended-RT
1802 if (record
.svp64
is not None and
1803 record
.mode
== _SVMode
.LDST_IMM
and
1804 'u' in record
.name
):
1805 yield f
"{blob}.long 0x{int(self):08x}"
1809 if style
is Style
.LEGACY
:
1811 for operand
in self
.dynamic_operands(record
=record
):
1812 if isinstance(operand
, (GPRPairOperand
, FPRPairOperand
)):
1815 # unofficial == "0" means an official instruction that needs .long
1816 if style
is Style
.LEGACY
and (paired
or record
.ppc
.unofficial
!= ""):
1817 yield f
"{blob}.long 0x{int(self):08x}"
1819 operands
= tuple(map(_operator
.itemgetter(1),
1820 self
.spec_dynamic_operands(record
=record
, style
=style
)))
1822 operands
= ",".join(operands
)
1823 yield f
"{blob}{record.name} {operands}"
1825 yield f
"{blob}{record.name}"
1827 if style
>= Style
.VERBOSE
:
1829 binary
= self
.binary
1830 spec
= self
.spec(record
=record
, prefix
="")
1831 yield f
"{indent}spec"
1832 yield f
"{indent}{indent}{spec}"
1833 yield f
"{indent}pcode"
1834 for stmt
in record
.mdwn
.pcode
:
1835 yield f
"{indent}{indent}{stmt}"
1836 yield f
"{indent}binary"
1837 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1838 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1839 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1840 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1841 yield f
"{indent}opcodes"
1842 for opcode
in record
.opcodes
:
1843 yield f
"{indent}{indent}{opcode!r}"
1844 for operand
in self
.operands(record
=record
):
1845 yield from operand
.disassemble(insn
=self
,
1846 style
=style
, indent
=indent
)
1850 class PrefixedInstruction(Instruction
):
1851 class Prefix(WordInstruction
.remap(range(0, 32))):
1854 class Suffix(WordInstruction
.remap(range(32, 64))):
1857 _
: _Field
= range(64)
1863 def integer(cls
, value
, byteorder
="little"):
1864 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1867 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1868 def transform(value
):
1869 return WordInstruction
.integer(value
=value
,
1870 byteorder
=byteorder
)[0:32]
1872 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1873 value
= _selectconcat(prefix
, suffix
)
1875 return super().integer(bits
=64, value
=value
)
1878 class Mode(_Mapping
):
1879 _
: _Field
= range(0, 5)
1880 sel
: _Field
= (0, 1)
1883 class ExtraRM(_Mapping
):
1884 _
: _Field
= range(0, 9)
1887 class Extra2RM(ExtraRM
):
1888 idx0
: _Field
= range(0, 2)
1889 idx1
: _Field
= range(2, 4)
1890 idx2
: _Field
= range(4, 6)
1891 idx3
: _Field
= range(6, 8)
1893 def __getitem__(self
, key
):
1899 _SVExtra
.Idx0
: self
.idx0
,
1900 _SVExtra
.Idx1
: self
.idx1
,
1901 _SVExtra
.Idx2
: self
.idx2
,
1902 _SVExtra
.Idx3
: self
.idx3
,
1905 def __setitem__(self
, key
, value
):
1906 self
[key
].assign(value
)
1909 class Extra3RM(ExtraRM
):
1910 idx0
: _Field
= range(0, 3)
1911 idx1
: _Field
= range(3, 6)
1912 idx2
: _Field
= range(6, 9)
1914 def __getitem__(self
, key
):
1919 _SVExtra
.Idx0
: self
.idx0
,
1920 _SVExtra
.Idx1
: self
.idx1
,
1921 _SVExtra
.Idx2
: self
.idx2
,
1924 def __setitem__(self
, key
, value
):
1925 self
[key
].assign(value
)
1928 class BaseRM(_Mapping
):
1929 _
: _Field
= range(24)
1930 mmode
: _Field
= (0,)
1931 mask
: _Field
= range(1, 4)
1932 elwidth
: _Field
= range(4, 6)
1933 ewsrc
: _Field
= range(6, 8)
1934 subvl
: _Field
= range(8, 10)
1935 mode
: Mode
.remap(range(19, 24))
1936 smask_extra322
: _Field
= (6,7,18,) # LDST_IDX is EXTRA332
1937 smask
: _Field
= range(16, 19) # everything else use this
1938 extra
: ExtraRM
.remap(range(10, 19))
1939 extra2
: Extra2RM
.remap(range(10, 19))
1940 extra3
: Extra3RM
.remap(range(10, 19))
1941 # XXX extra332 = (extra3[0], extra3[1], extra2[3])
1943 def specifiers(self
, record
):
1944 subvl
= int(self
.subvl
)
1952 def disassemble(self
, style
=Style
.NORMAL
):
1953 if style
>= Style
.VERBOSE
:
1955 for (name
, span
) in self
.traverse(path
="RM"):
1956 value
= self
.storage
[span
]
1958 yield f
"{indent}{int(value):0{value.bits}b}"
1959 yield f
"{indent}{', '.join(map(str, span))}"
1962 class FFRc1BaseRM(BaseRM
):
1963 def specifiers(self
, record
, mode
):
1964 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1965 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1966 mask
= int(_selectconcat(CR
, inv
))
1967 predicate
= PredicateBaseRM
.predicate(True, mask
)
1968 yield f
"{mode}={predicate}"
1970 yield from super().specifiers(record
=record
)
1973 class FFRc0BaseRM(BaseRM
):
1974 def specifiers(self
, record
, mode
):
1976 inv
= "~" if self
.inv
else ""
1977 yield f
"{mode}={inv}RC1"
1979 yield from super().specifiers(record
=record
)
1982 class SatBaseRM(BaseRM
):
1983 def specifiers(self
, record
):
1989 yield from super().specifiers(record
=record
)
1992 class ZZBaseRM(BaseRM
):
1993 def specifiers(self
, record
):
1997 yield from super().specifiers(record
=record
)
2000 class ZZCombinedBaseRM(BaseRM
):
2001 def specifiers(self
, record
):
2002 if self
.sz
and self
.dz
:
2009 yield from super().specifiers(record
=record
)
2012 class DZBaseRM(BaseRM
):
2013 def specifiers(self
, record
):
2017 yield from super().specifiers(record
=record
)
2020 class SZBaseRM(BaseRM
):
2021 def specifiers(self
, record
):
2025 yield from super().specifiers(record
=record
)
2028 class MRBaseRM(BaseRM
):
2029 def specifiers(self
, record
):
2035 yield from super().specifiers(record
=record
)
2038 class ElsBaseRM(BaseRM
):
2039 def specifiers(self
, record
):
2043 yield from super().specifiers(record
=record
)
2046 class WidthBaseRM(BaseRM
):
2048 def width(FP
, width
):
2057 width
= ("fp" + width
)
2060 def specifiers(self
, record
):
2061 # elwidths: use "w=" if same otherwise dw/sw
2062 # FIXME this should consider FP instructions
2064 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
2065 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2066 if record
.svp64
.mode
is _SVMode
.CROP
:
2070 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2079 yield from super().specifiers(record
=record
)
2082 class PredicateBaseRM(BaseRM
):
2084 def predicate(CR
, mask
):
2087 (False, 0b001): "1<<r3",
2088 (False, 0b010): "r3",
2089 (False, 0b011): "~r3",
2090 (False, 0b100): "r10",
2091 (False, 0b101): "~r10",
2092 (False, 0b110): "r30",
2093 (False, 0b111): "~r30",
2095 (True, 0b000): "lt",
2096 (True, 0b001): "ge",
2097 (True, 0b010): "gt",
2098 (True, 0b011): "le",
2099 (True, 0b100): "eq",
2100 (True, 0b101): "ne",
2101 (True, 0b110): "so",
2102 (True, 0b111): "ns",
2105 def specifiers(self
, record
):
2106 # predication - single and twin
2107 # use "m=" if same otherwise sm/dm
2108 CR
= (int(self
.mmode
) == 1)
2109 mask
= int(self
.mask
)
2110 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
2111 if record
.svp64
.ptype
is _SVPType
.P2
:
2112 # LDST_IDX smask moving to extra322 but not straight away (False)
2113 if False and record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2114 smask
= int(self
.smask_extra332
)
2116 smask
= int(self
.smask
)
2117 sm
= PredicateBaseRM
.predicate(CR
, smask
)
2126 yield from super().specifiers(record
=record
)
2129 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
2133 class SEABaseRM(BaseRM
):
2134 def specifiers(self
, record
):
2138 yield from super().specifiers(record
=record
)
2141 class VLiBaseRM(BaseRM
):
2142 def specifiers(self
, record
):
2146 yield from super().specifiers(record
=record
)
2149 class NormalBaseRM(PredicateWidthBaseRM
):
2152 https://libre-soc.org/openpower/sv/normal/
2157 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
2158 """normal: simple mode"""
2162 def specifiers(self
, record
):
2163 yield from super().specifiers(record
=record
)
2166 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2167 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2171 class NormalFFRc1RM(FFRc1BaseRM
, VLiBaseRM
, NormalBaseRM
):
2172 """normal: Rc=1: ffirst CR sel"""
2175 CR
: BaseRM
.mode
[3, 4]
2177 def specifiers(self
, record
):
2178 yield from super().specifiers(record
=record
, mode
="ff")
2181 class NormalFFRc0RM(FFRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2182 """normal: Rc=0: ffirst z/nonz"""
2187 def specifiers(self
, record
):
2188 yield from super().specifiers(record
=record
, mode
="ff")
2191 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2192 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2198 class NormalRM(NormalBaseRM
):
2199 simple
: NormalSimpleRM
2201 ffrc1
: NormalFFRc1RM
2202 ffrc0
: NormalFFRc0RM
2206 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2208 LD/ST Immediate mode
2209 https://libre-soc.org/openpower/sv/ldst/
2214 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2215 """ld/st immediate: simple mode"""
2216 pi
: BaseRM
.mode
[2] # Post-Increment Mode
2217 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2223 def specifiers(self
, record
):
2229 yield from super().specifiers(record
=record
)
2232 class LDSTFFRc1RM(FFRc1BaseRM
, VLiBaseRM
, LDSTImmBaseRM
):
2233 """ld/st immediate&indexed: Rc=1: ffirst CR sel"""
2236 CR
: BaseRM
.mode
[3, 4]
2238 def specifiers(self
, record
):
2239 yield from super().specifiers(record
=record
, mode
="ff")
2242 class LDSTFFRc0RM(FFRc0BaseRM
, VLiBaseRM
, LDSTImmBaseRM
):
2243 """ld/st immediate&indexed: Rc=0: ffirst z/nonz"""
2248 def specifiers(self
, record
):
2249 yield from super().specifiers(record
=record
, mode
="ff")
2252 class LDSTImmRM(LDSTImmBaseRM
):
2253 simple
: LDSTImmSimpleRM
2258 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2261 https://libre-soc.org/openpower/sv/ldst/
2266 class LDSTIdxSimpleRM(SEABaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2267 """ld/st index: simple mode (includes element-strided and Signed-EA)"""
2268 pi
: BaseRM
.mode
[2] # Post-Increment Mode
2275 def specifiers(self
, record
):
2281 yield from super().specifiers(record
=record
)
2284 class LDSTIdxRM(LDSTIdxBaseRM
):
2285 simple
: LDSTIdxSimpleRM
2291 class CROpBaseRM(BaseRM
):
2294 https://libre-soc.org/openpower/sv/cr_ops/
2299 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2300 """crop: simple mode"""
2305 def specifiers(self
, record
):
2307 yield "rg" # simple CR Mode reports /rg
2309 yield from super().specifiers(record
=record
)
2312 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2313 """crop: scalar reduce mode (mapreduce)"""
2319 class CROpFF5RM(FFRc0BaseRM
, PredicateBaseRM
, VLiBaseRM
, DZBaseRM
,
2320 SZBaseRM
, CROpBaseRM
):
2321 """crop: ffirst 5-bit mode"""
2328 def specifiers(self
, record
):
2329 yield from super().specifiers(record
=record
, mode
="ff")
2332 # FIXME: almost everything in this class contradicts the specs (it doesn't)
2333 # The modes however are swapped: 5-bit is 3-bit, 3-bit is 5-bit
2334 class CROpFF3RM(FFRc1BaseRM
, PredicateBaseRM
, VLiBaseRM
, ZZBaseRM
, CROpBaseRM
):
2335 """cr_op: ffirst 3-bit mode"""
2341 def specifiers(self
, record
):
2342 yield from super().specifiers(record
=record
, mode
="ff")
2345 class CROpRM(CROpBaseRM
):
2346 simple
: CROpSimpleRM
2352 # ********************
2354 # https://libre-soc.org/openpower/sv/branches/
2355 class BranchBaseRM(BaseRM
):
2365 def specifiers(self
, record
):
2377 raise ValueError(self
.sz
)
2389 # Branch modes lack source mask.
2390 # Therefore a custom code is needed.
2391 CR
= (int(self
.mmode
) == 1)
2392 mask
= int(self
.mask
)
2393 m
= PredicateBaseRM
.predicate(CR
, mask
)
2397 yield from super().specifiers(record
=record
)
2400 class BranchSimpleRM(BranchBaseRM
):
2401 """branch: simple mode"""
2405 class BranchVLSRM(BranchBaseRM
):
2406 """branch: VLSET mode"""
2410 def specifiers(self
, record
):
2416 }[int(self
.VSb
), int(self
.VLi
)]
2418 yield from super().specifiers(record
=record
)
2421 class BranchCTRRM(BranchBaseRM
):
2422 """branch: CTR-test mode"""
2425 def specifiers(self
, record
):
2431 yield from super().specifiers(record
=record
)
2434 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2435 """branch: CTR-test+VLSET mode"""
2439 class BranchRM(BranchBaseRM
):
2440 simple
: BranchSimpleRM
2443 ctrvls
: BranchCTRVLSRM
2454 @_dataclasses.dataclass(eq
=True, frozen
=True)
2459 def match(cls
, desc
, record
):
2460 raise NotImplementedError()
2462 def validate(self
, others
):
2465 def assemble(self
, insn
):
2466 raise NotImplementedError()
2469 @_dataclasses.dataclass(eq
=True, frozen
=True)
2470 class SpecifierWidth(Specifier
):
2474 def match(cls
, desc
, record
, etalon
):
2475 (mode
, _
, value
) = desc
.partition("=")
2477 value
= value
.strip()
2480 width
= _SVP64Width(value
)
2482 return cls(record
=record
, width
=width
)
2485 @_dataclasses.dataclass(eq
=True, frozen
=True)
2486 class SpecifierW(SpecifierWidth
):
2488 def match(cls
, desc
, record
):
2489 return super().match(desc
=desc
, record
=record
, etalon
="w")
2491 def assemble(self
, insn
):
2492 selector
= insn
.select(record
=self
.record
)
2493 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2494 selector
.ewsrc
= self
.width
.value
2495 selector
.elwidth
= self
.width
.value
2498 @_dataclasses.dataclass(eq
=True, frozen
=True)
2499 class SpecifierSW(SpecifierWidth
):
2501 def match(cls
, desc
, record
):
2502 if record
.svp64
.mode
is _SVMode
.CROP
:
2504 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2506 def assemble(self
, insn
):
2507 selector
= insn
.select(record
=self
.record
)
2508 selector
.ewsrc
= self
.width
.value
2511 @_dataclasses.dataclass(eq
=True, frozen
=True)
2512 class SpecifierDW(SpecifierWidth
):
2514 def match(cls
, desc
, record
):
2515 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2517 def assemble(self
, insn
):
2518 selector
= insn
.select(record
=self
.record
)
2519 selector
.elwidth
= self
.width
.value
2522 @_dataclasses.dataclass(eq
=True, frozen
=True)
2523 class SpecifierSubVL(Specifier
):
2527 def match(cls
, desc
, record
):
2529 value
= _SVP64SubVL(desc
)
2533 return cls(record
=record
, value
=value
)
2535 def assemble(self
, insn
):
2536 selector
= insn
.select(record
=self
.record
)
2537 selector
.subvl
= int(self
.value
.value
)
2540 @_dataclasses.dataclass(eq
=True, frozen
=True)
2541 class SpecifierPredicate(Specifier
):
2546 def match(cls
, desc
, record
, mode_match
, pred_match
):
2547 (mode
, _
, pred
) = desc
.partition("=")
2550 if not mode_match(mode
):
2553 pred
= _SVP64Pred(pred
.strip())
2554 if not pred_match(pred
):
2555 raise ValueError(pred
)
2557 return cls(record
=record
, mode
=mode
, pred
=pred
)
2560 @_dataclasses.dataclass(eq
=True, frozen
=True)
2561 class SpecifierFF(SpecifierPredicate
):
2563 def match(cls
, desc
, record
):
2564 return super().match(desc
=desc
, record
=record
,
2565 mode_match
=lambda mode_arg
: mode_arg
== "ff",
2566 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2571 def assemble(self
, insn
):
2572 selector
= insn
.select(record
=self
.record
)
2573 if selector
.mode
.sel
!= 0:
2574 raise ValueError("cannot override mode")
2575 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2576 selector
.mode
.sel
= 0b01
2577 # HACK: please finally provide correct logic for CRs.
2578 if self
.pred
in (_SVP64Pred
.RC1
, _SVP64Pred
.RC1_N
):
2579 selector
.mode
[2] = (self
.pred
is _SVP64Pred
.RC1_N
)
2581 selector
.mode
[2] = self
.pred
.inv
2582 selector
.mode
[3, 4] = self
.pred
.state
2584 selector
.mode
.sel
= 0b01 if self
.mode
== "ff" else 0b11
2585 selector
.inv
= self
.pred
.inv
2587 selector
.CR
= self
.pred
.state
2589 selector
.RC1
= self
.pred
.state
2592 @_dataclasses.dataclass(eq
=True, frozen
=True)
2593 class SpecifierMask(SpecifierPredicate
):
2595 def match(cls
, desc
, record
, mode
):
2596 return super().match(desc
=desc
, record
=record
,
2597 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2598 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2603 def assemble(self
, insn
):
2604 raise NotImplementedError()
2607 @_dataclasses.dataclass(eq
=True, frozen
=True)
2608 class SpecifierM(SpecifierMask
):
2610 def match(cls
, desc
, record
):
2611 return super().match(desc
=desc
, record
=record
, mode
="m")
2613 def validate(self
, others
):
2615 if isinstance(spec
, SpecifierSM
):
2616 raise ValueError("source-mask and predicate mask conflict")
2617 elif isinstance(spec
, SpecifierDM
):
2618 raise ValueError("dest-mask and predicate mask conflict")
2620 def assemble(self
, insn
):
2621 selector
= insn
.select(record
=self
.record
)
2622 selector
.mask
= int(self
.pred
)
2623 if ((self
.record
.ptype
is _SVPType
.P2
) and
2624 (self
.record
.svp64
.mode
is not _SVMode
.BRANCH
)):
2625 selector
.smask
= int(self
.pred
)
2626 # LDST_IDX smask moving to extra322 but not straight away (False)
2627 if False and self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2628 selector
.smask_extra332
= int(self
.pred
)
2630 selector
.smask
= int(self
.pred
)
2632 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2635 @_dataclasses.dataclass(eq
=True, frozen
=True)
2636 class SpecifierSM(SpecifierMask
):
2638 def match(cls
, desc
, record
):
2639 return super().match(desc
=desc
, record
=record
, mode
="sm")
2641 def validate(self
, others
):
2642 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2643 raise ValueError("source-mask on non-twin predicate")
2645 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2648 if isinstance(spec
, SpecifierDM
):
2652 raise ValueError("missing dest-mask in CR twin predication")
2653 if self
.pred
.mode
!= twin
.pred
.mode
:
2654 raise ValueError(f
"predicate masks mismatch: "
2655 f
"{self.pred!r} vs {twin.pred!r}")
2657 def assemble(self
, insn
):
2658 selector
= insn
.select(record
=self
.record
)
2659 # LDST_IDX smask moving to extra322 but not straight away (False)
2660 if False and self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2661 selector
.smask_extra332
= int(self
.pred
)
2663 selector
.smask
= int(self
.pred
)
2664 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2667 @_dataclasses.dataclass(eq
=True, frozen
=True)
2668 class SpecifierDM(SpecifierMask
):
2670 def match(cls
, desc
, record
):
2671 return super().match(desc
=desc
, record
=record
, mode
="dm")
2673 def validate(self
, others
):
2674 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2675 raise ValueError("dest-mask on non-twin predicate")
2677 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2680 if isinstance(spec
, SpecifierSM
):
2684 raise ValueError("missing source-mask in CR twin predication")
2685 if self
.pred
.mode
!= twin
.pred
.mode
:
2686 raise ValueError(f
"predicate masks mismatch: "
2687 f
"{self.pred!r} vs {twin.pred!r}")
2689 def assemble(self
, insn
):
2690 selector
= insn
.select(record
=self
.record
)
2691 selector
.mask
= int(self
.pred
)
2692 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2695 @_dataclasses.dataclass(eq
=True, frozen
=True)
2696 class SpecifierZZ(Specifier
):
2698 def match(cls
, desc
, record
):
2702 return cls(record
=record
)
2704 def validate(self
, others
):
2706 # Since zz takes precedence (overrides) sz and dz,
2707 # treat them as mutually exclusive.
2708 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2709 raise ValueError("mutually exclusive predicate masks")
2711 def assemble(self
, insn
):
2712 selector
= insn
.select(record
=self
.record
)
2713 if hasattr(selector
, "zz"): # this should be done in a different way
2720 @_dataclasses.dataclass(eq
=True, frozen
=True)
2721 class SpecifierXZ(Specifier
):
2723 hint
: str = _dataclasses
.field(repr=False)
2726 def match(cls
, desc
, record
, etalon
, hint
):
2730 return cls(desc
=desc
, record
=record
, hint
=hint
)
2732 def validate(self
, others
):
2733 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2734 raise ValueError(f
"{self.hint} on non-twin predicate")
2736 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2739 if isinstance(spec
, SpecifierXZ
):
2743 raise ValueError(f
"missing {self.hint} in CR twin predication")
2744 if self
.pred
!= twin
.pred
:
2745 raise ValueError(f
"predicate masks mismatch: "
2746 f
"{self.pred!r} vs {twin.pred!r}")
2748 def assemble(self
, insn
):
2749 selector
= insn
.select(record
=self
.record
)
2750 setattr(selector
, self
.desc
, 1)
2753 @_dataclasses.dataclass(eq
=True, frozen
=True)
2754 class SpecifierSZ(SpecifierXZ
):
2756 def match(cls
, desc
, record
):
2757 return super().match(desc
=desc
, record
=record
,
2758 etalon
="sz", hint
="source-mask")
2760 def validate(self
, others
):
2762 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2763 if isinstance(spec
, SpecifierFF
):
2764 raise ValueError("source-zero not allowed in ff mode")
2767 @_dataclasses.dataclass(eq
=True, frozen
=True)
2768 class SpecifierDZ(SpecifierXZ
):
2770 def match(cls
, desc
, record
):
2771 return super().match(desc
=desc
, record
=record
,
2772 etalon
="dz", hint
="dest-mask")
2774 def validate(self
, others
):
2776 if ((self
.record
.svp64
.mode
is not _SVMode
.CROP
) and
2777 isinstance(spec
, SpecifierFF
) and
2778 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2779 raise ValueError(f
"dest-zero not allowed in ff mode BO")
2782 @_dataclasses.dataclass(eq
=True, frozen
=True)
2783 class SpecifierEls(Specifier
):
2785 def match(cls
, desc
, record
):
2789 if record
.svp64
.mode
not in (_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2790 raise ValueError("els is only valid in ld/st modes, not "
2791 "%s" % str(self
.record
.svp64
.mode
))
2793 return cls(record
=record
)
2795 def assemble(self
, insn
):
2796 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
: # stride mode
2797 insn
.prefix
.rm
.mode
[1] = 0
2799 selector
= insn
.select(record
=self
.record
)
2804 @_dataclasses.dataclass(eq
=True, frozen
=True)
2805 class SpecifierSEA(Specifier
):
2807 def match(cls
, desc
, record
):
2811 return cls(record
=record
)
2813 def validate(self
, others
):
2814 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2815 raise ValueError("sea is only valid in ld/st modes, not "
2816 "%s" % str(self
.record
.svp64
.mode
))
2819 if isinstance(spec
, SpecifierFF
):
2820 raise ValueError(f
"sea cannot be used in ff mode")
2822 def assemble(self
, insn
):
2823 selector
= insn
.select(record
=self
.record
)
2824 if selector
.mode
.sel
not in (0b10, 0b00):
2825 raise ValueError("sea is only valid for normal and els modes, "
2826 "not %d" % int(selector
.mode
.sel
))
2830 @_dataclasses.dataclass(eq
=True, frozen
=True)
2831 class SpecifierSat(Specifier
):
2836 def match(cls
, desc
, record
, etalon
, sign
):
2840 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.LDST_IMM
,
2842 raise ValueError("only normal, ld/st imm and "
2843 "ld/st idx modes supported")
2845 return cls(record
=record
, desc
=desc
, sign
=sign
)
2847 def assemble(self
, insn
):
2848 selector
= insn
.select(record
=self
.record
)
2849 selector
.mode
[0] = 0b1
2850 selector
.mode
[1] = 0b0
2851 selector
.N
= int(self
.sign
)
2854 @_dataclasses.dataclass(eq
=True, frozen
=True)
2855 class SpecifierSatS(SpecifierSat
):
2857 def match(cls
, desc
, record
):
2858 return super().match(desc
=desc
, record
=record
,
2859 etalon
="sats", sign
=True)
2862 @_dataclasses.dataclass(eq
=True, frozen
=True)
2863 class SpecifierSatU(SpecifierSat
):
2865 def match(cls
, desc
, record
):
2866 return super().match(desc
=desc
, record
=record
,
2867 etalon
="satu", sign
=False)
2870 @_dataclasses.dataclass(eq
=True, frozen
=True)
2871 class SpecifierMapReduce(Specifier
):
2875 def match(cls
, record
, RG
):
2876 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2877 raise ValueError("only normal and crop modes supported")
2879 return cls(record
=record
, RG
=RG
)
2881 def assemble(self
, insn
):
2882 selector
= insn
.select(record
=self
.record
)
2883 if self
.record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2884 raise ValueError("only normal and crop modes supported")
2885 selector
.mode
[0] = 0
2886 selector
.mode
[1] = 0
2887 selector
.mode
[2] = 1
2888 selector
.RG
= self
.RG
2891 @_dataclasses.dataclass(eq
=True, frozen
=True)
2892 class SpecifierMR(SpecifierMapReduce
):
2894 def match(cls
, desc
, record
):
2898 return super().match(record
=record
, RG
=False)
2901 @_dataclasses.dataclass(eq
=True, frozen
=True)
2902 class SpecifierMRR(SpecifierMapReduce
):
2904 def match(cls
, desc
, record
):
2908 return super().match(record
=record
, RG
=True)
2911 @_dataclasses.dataclass(eq
=True, frozen
=True)
2912 class SpecifierBranch(Specifier
):
2914 def match(cls
, desc
, record
, etalon
):
2918 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
2919 raise ValueError("only branch modes supported")
2921 return cls(record
=record
)
2924 @_dataclasses.dataclass(eq
=True, frozen
=True)
2925 class SpecifierAll(SpecifierBranch
):
2927 def match(cls
, desc
, record
):
2928 return super().match(desc
=desc
, record
=record
, etalon
="all")
2930 def assemble(self
, insn
):
2931 selector
= insn
.select(record
=self
.record
)
2935 @_dataclasses.dataclass(eq
=True, frozen
=True)
2936 class SpecifierSNZ(Specifier
):
2938 def match(cls
, desc
, record
):
2942 if record
.svp64
.mode
not in (_SVMode
.BRANCH
, _SVMode
.CROP
):
2943 raise ValueError("only branch and crop modes supported")
2945 return cls(record
=record
)
2947 def assemble(self
, insn
):
2948 selector
= insn
.select(record
=self
.record
)
2949 if self
.record
.svp64
.mode
in (_SVMode
.CROP
, _SVMode
.BRANCH
):
2951 if self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
2954 raise ValueError("only branch and crop modes supported")
2957 @_dataclasses.dataclass(eq
=True, frozen
=True)
2958 class SpecifierSL(SpecifierBranch
):
2960 def match(cls
, desc
, record
):
2961 return super().match(desc
=desc
, record
=record
, etalon
="sl")
2963 def assemble(self
, insn
):
2964 selector
= insn
.select(record
=self
.record
)
2968 @_dataclasses.dataclass(eq
=True, frozen
=True)
2969 class SpecifierSLu(SpecifierBranch
):
2971 def match(cls
, desc
, record
):
2972 return super().match(desc
=desc
, record
=record
, etalon
="slu")
2974 def assemble(self
, insn
):
2975 selector
= insn
.select(record
=self
.record
)
2979 @_dataclasses.dataclass(eq
=True, frozen
=True)
2980 class SpecifierLRu(SpecifierBranch
):
2982 def match(cls
, desc
, record
):
2983 return super().match(desc
=desc
, record
=record
, etalon
="lru")
2985 def assemble(self
, insn
):
2986 selector
= insn
.select(record
=self
.record
)
2990 @_dataclasses.dataclass(eq
=True, frozen
=True)
2991 class SpecifierVSXX(SpecifierBranch
):
2996 def match(cls
, desc
, record
, etalon
, VSb
, VLi
):
3000 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3001 raise ValueError("only branch modes supported")
3003 return cls(record
=record
, VSb
=VSb
, VLi
=VLi
)
3005 def assemble(self
, insn
):
3006 selector
= insn
.select(record
=self
.record
)
3008 selector
.VSb
= int(self
.VSb
)
3009 selector
.VLi
= int(self
.VLi
)
3012 @_dataclasses.dataclass(eq
=True, frozen
=True)
3013 class SpecifierVS(SpecifierVSXX
):
3015 def match(cls
, desc
, record
):
3016 return super().match(desc
=desc
, record
=record
,
3017 etalon
="vs", VSb
=False, VLi
=False)
3020 @_dataclasses.dataclass(eq
=True, frozen
=True)
3021 class SpecifierVSi(SpecifierVSXX
):
3023 def match(cls
, desc
, record
):
3024 return super().match(desc
=desc
, record
=record
,
3025 etalon
="vsi", VSb
=False, VLi
=True)
3028 @_dataclasses.dataclass(eq
=True, frozen
=True)
3029 class SpecifierVSb(SpecifierVSXX
):
3031 def match(cls
, desc
, record
):
3032 return super().match(desc
=desc
, record
=record
,
3033 etalon
="vsb", VSb
=True, VLi
=False)
3036 @_dataclasses.dataclass(eq
=True, frozen
=True)
3037 class SpecifierVSbi(SpecifierVSXX
):
3039 def match(cls
, desc
, record
):
3040 return super().match(desc
=desc
, record
=record
,
3041 etalon
="vsbi", VSb
=True, VLi
=True)
3044 @_dataclasses.dataclass(eq
=True, frozen
=True)
3045 class SpecifierCTX(Specifier
):
3049 def match(cls
, desc
, record
, etalon
, CTi
):
3053 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3054 raise ValueError("only branch modes supported")
3056 return cls(record
=record
, CTi
=CTi
)
3058 def assemble(self
, insn
):
3059 selector
= insn
.select(record
=self
.record
)
3061 selector
.CTi
= int(self
.CTi
)
3064 @_dataclasses.dataclass(eq
=True, frozen
=True)
3065 class SpecifierCTR(SpecifierCTX
):
3067 def match(cls
, desc
, record
):
3068 return super().match(desc
=desc
, record
=record
,
3069 etalon
="ctr", CTi
=False)
3072 @_dataclasses.dataclass(eq
=True, frozen
=True)
3073 class SpecifierCTi(SpecifierCTX
):
3075 def match(cls
, desc
, record
):
3076 return super().match(desc
=desc
, record
=record
,
3077 etalon
="cti", CTi
=True)
3080 @_dataclasses.dataclass(eq
=True, frozen
=True)
3081 class SpecifierPI(Specifier
):
3083 def match(cls
, desc
, record
):
3087 if record
.svp64
.mode
not in [_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
]:
3088 raise ValueError("only ld/st imm/idx mode supported")
3090 return cls(record
=record
)
3092 def assemble(self
, insn
):
3093 selector
= insn
.select(record
=self
.record
)
3094 selector
.mode
[2] = 0b1
3098 @_dataclasses.dataclass(eq
=True, frozen
=True)
3099 class SpecifierLF(Specifier
):
3101 def match(cls
, desc
, record
):
3105 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3106 raise ValueError("only ld/st imm mode supported")
3108 return cls(record
=record
)
3110 def assemble(self
, insn
):
3111 selector
= insn
.select(record
=self
.record
)
3112 selector
.mode
[1] = 0
3116 @_dataclasses.dataclass(eq
=True, frozen
=True)
3117 class SpecifierVLi(Specifier
):
3119 def match(cls
, desc
, record
):
3123 return cls(record
=record
)
3125 def validate(self
, others
):
3127 if isinstance(spec
, SpecifierFF
):
3130 raise ValueError("VLi only allowed in failfirst")
3132 def assemble(self
, insn
):
3133 selector
= insn
.select(record
=self
.record
)
3134 selector
.mode
[1] = 1
3138 class Specifiers(tuple):
3173 def __new__(cls
, items
, record
):
3174 def transform(item
):
3175 for spec_cls
in cls
.SPECS
:
3176 spec
= spec_cls
.match(item
, record
=record
)
3177 if spec
is not None:
3179 raise ValueError(item
)
3181 # TODO: remove this hack
3182 items
= dict.fromkeys(items
)
3186 items
= tuple(items
)
3188 specs
= tuple(map(transform
, items
))
3189 for (index
, spec
) in enumerate(specs
):
3190 head
= specs
[:index
]
3191 tail
= specs
[index
+ 1:]
3192 spec
.validate(others
=(head
+ tail
))
3194 return super().__new
__(cls
, specs
)
3197 class SVP64OperandMeta(type):
3198 class SVP64NonZeroOperand(NonZeroOperand
):
3199 def assemble(self
, insn
, value
):
3200 if isinstance(value
, str):
3201 value
= int(value
, 0)
3202 if not isinstance(value
, int):
3203 raise ValueError("non-integer operand")
3205 # FIXME: this is really weird
3206 if self
.record
.name
in ("svstep", "svstep."):
3207 value
+= 1 # compensation
3209 return super().assemble(value
=value
, insn
=insn
)
3211 class SVP64XOStaticOperand(SpanStaticOperand
):
3212 def __init__(self
, record
, value
, span
):
3213 return super().__init
__(record
=record
, name
="XO",
3214 value
=value
, span
=span
)
3217 NonZeroOperand
: SVP64NonZeroOperand
,
3218 XOStaticOperand
: SVP64XOStaticOperand
,
3221 def __new__(metacls
, name
, bases
, ns
):
3223 for (index
, base_cls
) in enumerate(bases
):
3224 bases
[index
] = metacls
.__TRANSFORM
.get(base_cls
, base_cls
)
3226 bases
= tuple(bases
)
3228 return super().__new
__(metacls
, name
, bases
, ns
)
3231 class SVP64Operand(Operand
, metaclass
=SVP64OperandMeta
):
3234 return tuple(map(lambda bit
: (bit
+ 32), super().span
))
3238 def __init__(self
, insn
, record
):
3240 self
.__record
= record
3241 return super().__init
__()
3244 return self
.rm
.__doc
__
3247 return repr(self
.rm
)
3255 return self
.__record
3259 rm
= getattr(self
.insn
.prefix
.rm
, self
.record
.svp64
.mode
.name
.lower())
3261 # The idea behind these tables is that they are now literally
3262 # in identical format to insndb.csv and minor_xx.csv and can
3263 # be done precisely as that. The only thing to watch out for
3264 # is the insertion of Rc=1 as a "mask/value" bit and likewise
3265 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
3268 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
3269 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3270 # mode Rc mask Rc member
3272 (0b000000, 0b111000, "simple"), # simple (no Rc)
3273 (0b001000, 0b111100, "mr"), # mapreduce (no Rc)
3274 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3275 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3276 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3277 (0b001100, 0b111100, "rsvd"), # reserved
3279 mode
= int(self
.insn
.prefix
.rm
.normal
.mode
)
3280 search
= ((mode
<< 1) | self
.record
.Rc
)
3282 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
3283 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3284 # mode Rc mask Rc member
3285 # ironically/coincidentally this table is identical to NORMAL
3286 # mode except reserved in place of mr
3288 (0b000000, 0b010000, "simple"), # simple (no Rc involved)
3289 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3290 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3292 search
= ((int(self
.insn
.prefix
.rm
.ldst_imm
.mode
) << 1) |
3295 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
3296 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3297 # mode Rc mask Rc member
3299 (0b000000, 0b010000, "simple"), # simple (no Rc involved)
3300 (0b010001, 0b010001, "ffrc1"), # ffirst, Rc=1
3301 (0b010000, 0b010001, "ffrc0"), # ffirst, Rc=0
3303 search
= ((int(self
.insn
.prefix
.rm
.ldst_idx
.mode
) << 1) |
3306 elif self
.record
.svp64
.mode
is _SVMode
.CROP
:
3307 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
3308 # mode 3b mask 3b member
3310 (0b000000, 0b111000, "simple"), # simple
3311 (0b001000, 0b111000, "mr"), # mapreduce
3312 (0b010001, 0b010001, "ff3"), # ffirst, 3-bit CR
3313 (0b010000, 0b010000, "ff5"), # ffirst, 5-bit CR
3315 search
= ((int(self
.insn
.prefix
.rm
.crop
.mode
) << 1) |
3316 int(self
.record
.svp64
.extra_CR_3bit
))
3318 elif self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3322 (0b00, 0b11, "simple"), # simple
3323 (0b01, 0b11, "vls"), # VLset
3324 (0b10, 0b11, "ctr"), # CTR mode
3325 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
3327 # slightly weird: doesn't have a 5-bit "mode" field like others
3328 search
= int(self
.insn
.prefix
.rm
.branch
.mode
.sel
)
3331 if table
is not None:
3332 for (value
, mask
, field
) in table
:
3333 if field
.startswith("rsvd"):
3335 if ((value
& mask
) == (search
& mask
)):
3336 return getattr(rm
, field
)
3340 def __getattr__(self
, key
):
3341 if key
.startswith(f
"_{self.__class__.__name__}__"):
3342 return super().__getattribute
__(key
)
3344 return getattr(self
.rm
, key
)
3346 def __setattr__(self
, key
, value
):
3347 if key
.startswith(f
"_{self.__class__.__name__}__"):
3348 return super().__setattr
__(key
, value
)
3351 if not hasattr(rm
, key
):
3352 raise AttributeError(key
)
3354 return setattr(rm
, key
, value
)
3357 class SVP64Instruction(PrefixedInstruction
):
3358 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3359 class Prefix(PrefixedInstruction
.Prefix
):
3361 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3365 def select(self
, record
):
3366 return RMSelector(insn
=self
, record
=record
)
3371 for idx
in range(64):
3372 bit
= int(self
[idx
])
3374 return "".join(map(str, bits
))
3377 def assemble(cls
, record
, arguments
=None, specifiers
=None):
3378 insn
= super().assemble(record
=record
, arguments
=arguments
)
3380 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3381 for specifier
in specifiers
:
3382 specifier
.assemble(insn
=insn
)
3384 insn
.prefix
.PO
= 0x1
3385 insn
.prefix
.id = 0x3
3389 def disassemble(self
, record
,
3391 style
=Style
.NORMAL
):
3393 if style
<= Style
.SHORT
:
3396 blob
= insn
.bytes(byteorder
=byteorder
)
3397 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3400 blob_prefix
= blob(self
.prefix
)
3401 blob_suffix
= blob(self
.suffix
)
3403 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3404 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3407 assert record
.svp64
is not None
3409 name
= f
"sv.{record.name}"
3411 rm
= self
.select(record
=record
)
3413 # convert specifiers to /x/y/z (sorted lexicographically)
3414 specifiers
= sorted(rm
.specifiers(record
=record
))
3415 if specifiers
: # if any add one extra to get the extra "/"
3416 specifiers
= ([""] + specifiers
)
3417 specifiers
= "/".join(specifiers
)
3419 # convert operands to " ,x,y,z"
3420 operands
= tuple(map(_operator
.itemgetter(1),
3421 self
.spec_dynamic_operands(record
=record
, style
=style
)))
3422 operands
= ",".join(operands
)
3423 if len(operands
) > 0: # if any separate with a space
3424 operands
= (" " + operands
)
3426 if style
<= Style
.LEGACY
:
3427 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3428 suffix
= WordInstruction
.integer(value
=int(self
.suffix
))
3429 yield from suffix
.disassemble(record
=record
,
3430 byteorder
=byteorder
, style
=style
)
3432 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3434 yield f
"{blob_suffix}"
3436 if style
>= Style
.VERBOSE
:
3438 binary
= self
.binary
3439 spec
= self
.spec(record
=record
, prefix
="sv.")
3441 yield f
"{indent}spec"
3442 yield f
"{indent}{indent}{spec}"
3443 yield f
"{indent}pcode"
3444 for stmt
in record
.mdwn
.pcode
:
3445 yield f
"{indent}{indent}{stmt}"
3446 yield f
"{indent}binary"
3447 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3448 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3449 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3450 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3451 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3452 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3453 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3454 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3455 yield f
"{indent}opcodes"
3456 for opcode
in record
.opcodes
:
3457 yield f
"{indent}{indent}{opcode!r}"
3458 for operand
in self
.operands(record
=record
):
3459 yield from operand
.disassemble(insn
=self
,
3460 style
=style
, indent
=indent
)
3462 yield f
"{indent}{indent}{str(rm)}"
3463 for line
in rm
.disassemble(style
=style
):
3464 yield f
"{indent}{indent}{line}"
3468 def operands(cls
, record
):
3469 for operand
in super().operands(record
=record
):
3470 parent
= operand
.__class
__
3471 name
= f
"SVP64{parent.__name__}"
3472 bases
= (SVP64Operand
, parent
)
3473 child
= type(name
, bases
, {})
3474 yield child(**dict(operand
))
3477 def parse(stream
, factory
):
3479 return ("TODO" not in frozenset(entry
.values()))
3481 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3482 entries
= _csv
.DictReader(lines
)
3483 entries
= filter(match
, entries
)
3484 return tuple(map(factory
, entries
))
3487 class MarkdownDatabase
:
3490 for (name
, desc
) in _ISA():
3493 (dynamic
, *static
) = desc
.regs
3494 operands
.extend(dynamic
)
3495 operands
.extend(static
)
3496 pcode
= PCode(filter(str.strip
, desc
.pcode
))
3497 operands
= Operands(insn
=name
, operands
=operands
)
3498 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3500 self
.__db
= dict(sorted(db
.items()))
3502 return super().__init
__()
3505 yield from self
.__db
.items()
3507 def __contains__(self
, key
):
3508 return self
.__db
.__contains
__(key
)
3510 def __getitem__(self
, key
):
3511 return self
.__db
.__getitem
__(key
)
3514 class FieldsDatabase
:
3517 df
= _DecodeFields()
3519 for (form
, fields
) in df
.instrs
.items():
3520 if form
in {"DQE", "TX"}:
3524 db
[_Form
[form
]] = Fields(fields
)
3528 return super().__init
__()
3530 def __getitem__(self
, key
):
3531 return self
.__db
.__getitem
__(key
)
3535 def __init__(self
, root
, mdwndb
):
3536 # The code below groups the instructions by name:section.
3537 # There can be multiple names for the same instruction.
3538 # The point is to capture different opcodes for the same instruction.
3540 records
= _collections
.defaultdict(set)
3541 path
= (root
/ "insndb.csv")
3542 with
open(path
, "r", encoding
="UTF-8") as stream
:
3543 for section
in sorted(parse(stream
, Section
.CSV
)):
3544 path
= (root
/ section
.csv
)
3546 section
.Mode
.INTEGER
: IntegerOpcode
,
3547 section
.Mode
.PATTERN
: PatternOpcode
,
3549 factory
= _functools
.partial(PPCRecord
.CSV
,
3550 opcode_cls
=opcode_cls
)
3551 with
open(path
, "r", encoding
="UTF-8") as stream
:
3552 for insn
in parse(stream
, factory
):
3553 for name
in insn
.names
:
3554 records
[name
].add(insn
)
3555 sections
[name
] = section
3557 items
= sorted(records
.items())
3559 for (name
, multirecord
) in items
:
3560 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3562 def exact_match(name
):
3563 record
= records
.get(name
)
3569 if not name
.endswith("l"):
3571 alias
= exact_match(name
[:-1])
3574 record
= records
[alias
]
3575 if "lk" not in record
.flags
:
3576 raise ValueError(record
)
3580 if not name
.endswith("a"):
3582 alias
= LK_match(name
[:-1])
3585 record
= records
[alias
]
3586 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3587 raise ValueError(record
)
3588 if "AA" not in mdwndb
[name
].operands
:
3589 raise ValueError(record
)
3593 if not name
.endswith("."):
3595 alias
= exact_match(name
[:-1])
3598 record
= records
[alias
]
3599 if record
.Rc
is _RCOE
.NONE
:
3600 raise ValueError(record
)
3604 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3605 for (name
, _
) in mdwndb
:
3606 if name
.startswith("sv."):
3609 for match
in matches
:
3611 if alias
is not None:
3615 section
= sections
[alias
]
3616 record
= records
[alias
]
3617 db
[name
] = (section
, record
)
3619 self
.__db
= dict(sorted(db
.items()))
3621 return super().__init
__()
3623 @_functools.lru_cache(maxsize
=512, typed
=False)
3624 def __getitem__(self
, key
):
3625 return self
.__db
.get(key
, (None, None))
3628 class SVP64Database
:
3629 def __init__(self
, root
, ppcdb
):
3631 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3632 for (prefix
, _
, names
) in _os
.walk(root
):
3633 prefix
= _pathlib
.Path(prefix
)
3634 for name
in filter(lambda name
: pattern
.match(name
), names
):
3635 path
= (prefix
/ _pathlib
.Path(name
))
3636 with
open(path
, "r", encoding
="UTF-8") as stream
:
3637 db
.update(parse(stream
, SVP64Record
.CSV
))
3638 db
= {record
.name
:record
for record
in db
}
3640 self
.__db
= dict(sorted(db
.items()))
3641 self
.__ppcdb
= ppcdb
3643 return super().__init
__()
3645 def __getitem__(self
, key
):
3646 (_
, record
) = self
.__ppcdb
[key
]
3650 for name
in record
.names
:
3651 record
= self
.__db
.get(name
, None)
3652 if record
is not None:
3658 class Records(tuple):
3659 def __new__(cls
, records
):
3660 return super().__new
__(cls
, sorted(records
))
3664 def __init__(self
, root
):
3665 root
= _pathlib
.Path(root
)
3666 mdwndb
= MarkdownDatabase()
3667 fieldsdb
= FieldsDatabase()
3668 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3669 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3673 opcodes
= _collections
.defaultdict(
3674 lambda: _collections
.defaultdict(set))
3676 for (name
, mdwn
) in mdwndb
:
3677 if name
.startswith("sv."):
3679 (section
, ppc
) = ppcdb
[name
]
3682 svp64
= svp64db
[name
]
3683 fields
= fieldsdb
[ppc
.form
]
3684 record
= Record(name
=name
,
3685 section
=section
, ppc
=ppc
, svp64
=svp64
,
3686 mdwn
=mdwn
, fields
=fields
)
3688 names
[record
.name
] = record
3689 opcodes
[section
][record
.PO
].add(record
)
3691 self
.__db
= Records(db
)
3692 self
.__names
= dict(sorted(names
.items()))
3693 self
.__opcodes
= dict(sorted(opcodes
.items()))
3695 return super().__init
__()
3698 return repr(self
.__db
)
3701 yield from self
.__db
3703 @_functools.lru_cache(maxsize
=None)
3704 def __contains__(self
, key
):
3705 return self
.__getitem
__(key
) is not None
3707 @_functools.lru_cache(maxsize
=None)
3708 def __getitem__(self
, key
):
3709 if isinstance(key
, SVP64Instruction
):
3712 if isinstance(key
, Instruction
):
3715 sections
= sorted(self
.__opcodes
)
3716 for section
in sections
:
3717 group
= self
.__opcodes
[section
]
3718 for record
in group
[PO
]:
3719 if record
.match(key
=key
):
3724 elif isinstance(key
, str):
3725 return self
.__names
.get(key
)
3727 raise ValueError("instruction or name expected")
3730 class Walker(mdis
.walker
.Walker
):
3731 @mdis.dispatcher
.Hook(Database
)
3732 def dispatch_database(self
, node
):
3733 yield from self(tuple(node
))