2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
17 To use the following registers:
20 > Memory mapped mode should continue to fetch data and fill the fifo even if the Core
22 * Done Status polling mode.
23 > This could not be replicated since the tof flag is set.
24 Memory mapped mode with dcyc =10 creates an extra cycle after Dummy phase.
25 > Data Read phase is on posedge and Data write is on negdege
26 -- send the received arid and bid's so that DMA can identify. duplicate instead of extend
31 import Semi_FIFOF :: *;
32 import AXI4_Lite_Types :: *;
33 import AXI4_Lite_Fabric :: *;
36 import SpecialFIFOs::*;
38 import DefaultValue :: *;
39 `include "instance_defines.bsv"
43 import UniqueWrappers :: * ;
46 (*always_ready, always_enabled*)
48 /*(* always_ready, result="clk_o" *) */
49 interface Get#(Bit#(1)) clk_o;
50 /*(* always_ready, result="io_o" *) */
51 interface Get#(Bit#(4)) io_out;
52 /*(* always_ready, result="io0_sdio_ctrl" *) */
53 method Bit#(9) io0_sdio_ctrl;
54 /*(* always_ready, result="io1_sdio_ctrl" *) */
55 method Bit#(9) io1_sdio_ctrl;
56 /*(* always_ready, result="io2_sdio_ctrl" *) */
57 method Bit#(9) io2_sdio_ctrl;
58 /*(* always_ready, result="io3_sdio_ctrl" *) */
59 method Bit#(9) io3_sdio_ctrl;
60 /*(* always_ready, result="io_enable" *)*/
61 interface Get#(Bit#(4)) io_out_en;
62 /*(* always_ready, always_enabled *) */
63 //method Action io_i ((* port="io_i" *) Bit#(4) io_in); // in
64 interface Put#(Bit#(4)) io_in;
65 /*(* always_ready, result="ncs_o" *) */
66 interface Get#(Bit#(1)) ncs_o;
70 interface QSPI_out out;
71 interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
72 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready
74 method Phase curphase;
78 function Reg#(t) readOnlyReg(t r);
79 return (interface Reg;
81 method Action _write(t x) = noAction;
85 function Reg#(t) conditionalWrite(Reg#(t) r, Bool a);
86 return (interface Reg;
87 method t _read = r._read;
88 method Action _write(t x);
95 function Reg#(t) clearSideEffect(Reg#(t) r, Action a, Action b)
96 provisos( Literal#(t),Eq#(t));
97 return (interface Reg;
98 method t _read = r._read;
99 method Action _write(t x);
109 function Reg#(Bit#(32)) writeSideEffect(Reg#(Bit#(32)) r, Action a);
110 return (interface Reg;
111 method Bit#(32) _read = r._read;
112 method Action _write(Bit#(32) x);
119 function Reg#(Bit#(n)) writeCCREffect(Reg#(Bit#(n)) r, Action a, Action b);
120 return (interface Reg;
121 method Bit#(n) _read = r._read;
122 method Action _write(Bit#(n) x);
124 `ifdef verbose1 $display("x: %h",x); `endif
125 if(x[11:10]==0 && (x[27:26] == 'b00 || x[27:26]=='b01 || x[25:24]=='b0) && x[9:8]!=0) begin // no address required and nodata from firmware (i.e. no write)
128 if(x[27:26]=='b11) //Memory Mapped Mode
134 typedef enum {Instruction_phase=0,
136 AlternateByte_phase=2,
140 Idle=6} Phase deriving (Bits,Eq,FShow);
143 module mkmqspi(Ifc_mqspi);
145 AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
146 /*************** List of implementation defined Registers *****************/
147 Reg#(bit) rg_clk <-mkReg(1);
148 Reg#(Bit#(8)) rg_clk_counter<-mkReg(0);
149 MIMOConfiguration cfg=defaultValue;
151 MIMO#(4,4,16,Bit#(8)) fifo <-mkMIMO(cfg);
152 Reg#(Phase) rg_phase <-mkReg(Idle);
153 Reg#(Phase) rg_phase_delayed <-mkReg(Idle);
154 Reg#(Bit#(4)) rg_output <-mkReg(0);
155 Reg#(Bit#(4)) rg_output_en <-mkReg(0);
156 Reg#(Bool) rg_input_en <-mkReg(False);
157 Wire#(Bit#(4)) rg_input <-mkDWire(0);
158 Reg#(Bit#(32)) rg_count_bits <-mkReg(0); // count bits to be transfered
159 Reg#(Bit#(32)) rg_count_bytes <-mkReg(0); // count bytes to be transfered
160 Wire#(Bool) wr_sdr_clock <-mkDWire(False); // use this to trigger posedge of sclk
161 Reg#(Bool) wr_sdr_delayed <- mkReg(False);
162 Reg#(Bool) wr_instruction_written<-mkDReg(False); // this wire is se when the instruction is written by the AXI Master
163 Reg#(Bool) wr_address_written<-mkDReg(False); // this wire is set when the address is written by the AXI Master
164 Reg#(Bool) wr_read_request_from_AXI<-mkDReg(False); // this wire is set when the address is written by the AXI Master
165 Reg#(Bool) wr_data_written<-mkDReg(False); // this wire is set when the data is written by the AXI Master
166 Reg#(Bool) instruction_sent<-mkReg(False); // This register is set when the instruction has been sent once to the flash
167 Reg#(Bit#(1)) ncs <-mkReg(1); // this is the chip select
168 Reg#(Bit#(1)) delay_ncs <-mkReg(1); // this is the chip select
169 Wire#(Bool) wr_status_read<-mkDWire(False); // this wire is set when the status register is written
170 Wire#(Bool) wr_data_read<-mkDWire(False); // this wire is set when the data register is written
171 Reg#(Bool) half_cycle_delay<-mkReg(False);
172 Reg#(Bit#(16)) timecounter<-mkReg(0);
173 Reg#(Bool) read_true <- mkReg(False);
174 Reg#(Bool) first_read <- mkReg(False);
175 /*************** End of implementation defined Registers *****************/
177 /*************** List of QSPI defined Registers *****************/
178 Reg#(Bit#(1)) sr_busy <-mkConfigReg(0); // set when the operation is in progress.
179 Reg#(Bit#(5)) sr_flevel <-mkReg(0); // FIFO Level. Number of valid bytes held in the FIFO. 0: empty
180 Reg#(Bit#(1)) sr_tof <-mkReg(0); // set when the timeout occurs.
181 Reg#(Bit#(1)) sr_smf <-mkReg(0); // set when the unmasked receieved data matches psmar.
182 Reg#(Bit#(1)) sr_ftf <-mkReg(0); // set when the FIFO threshold is reached.
183 Reg#(Bit#(1)) sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
184 Reg#(Bit#(1)) delay_sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
185 Reg#(Bit#(1)) sr_tef <-mkReg(0); // set when an error occurs on transfer.
186 Reg#(Bit#(32)) sr = concatReg9(readOnlyReg(19'd0),readOnlyReg(sr_flevel),readOnlyReg(2'd0),readOnlyReg(sr_busy),readOnlyReg(sr_tof),readOnlyReg(sr_smf),readOnlyReg(sr_ftf),readOnlyReg(sr_tcf),readOnlyReg(sr_tef));
189 Reg#(Bit#(8)) prescaler<-mkReg(0);
190 Reg#(Bit#(8)) cr_prescaler=conditionalWrite(prescaler,sr_busy==0); // prescaler register part of the control register.
191 Reg#(Bit#(1)) pmm <-mkReg(0);
192 Reg#(Bit#(1)) cr_pmm =conditionalWrite(pmm,sr_busy==0); // polling match mode. 0: AND match and 1: OR match.
193 Reg#(Bit#(1)) apms <-mkReg(0);
194 Reg#(Bit#(1)) cr_apms =conditionalWrite(apms,sr_busy==0); // automatic poll mode stop. 1: stop when match. 0: stopped by disabling qspi.
195 Reg#(Bit#(1)) cr_toie <-mkReg(0); // enabled interrupt on time-out.
196 Reg#(Bit#(1)) cr_smie <-mkReg(0); // enables status match interrupt.
197 Reg#(Bit#(1)) cr_ftie <-mkReg(0); // enables interrupt on FIFO threshold.
198 Reg#(Bit#(1)) cr_tcie <-mkReg(0); // enables interrupt on completion of transfer.
199 Reg#(Bit#(1)) cr_teie <-mkReg(0); // enables interrupt on error of transfer.
200 Reg#(Bit#(4)) cr_fthres<-mkReg(0); // defines the number of bytes in the FIFO that will cause the FTF in sr to be raised.
201 Reg#(Bit#(1)) fsel<-mkReg(0);
202 Reg#(Bit#(1)) cr_fsel=conditionalWrite(fsel,sr_busy==0); // used for flash memory selection TODO: Not required.
203 Reg#(Bit#(1)) dfm<-mkReg(0);
204 Reg#(Bit#(1)) cr_dfm =conditionalWrite(dfm,sr_busy==0); // used for dual flash mode TODO: Not required.
205 Reg#(Bit#(1)) sshift<-mkReg(0);
206 Reg#(Bit#(1)) cr_sshift =conditionalWrite(sshift,sr_busy==0); // sample shift to account for delays from the flash. TODO: Might not be required.
207 Reg#(Bit#(1)) tcen<-mkReg(0);
208 Reg#(Bit#(1)) cr_tcen =conditionalWrite(tcen,sr_busy==0); // enables the timeout counter.
209 Reg#(Bit#(1)) cr_dmaen <- mkReg(0); // enables the dma transfer.
210 Reg#(Bit#(1)) cr_abort <- mkReg(0); // this bit aborts the ongoing transaction.
211 Reg#(Bit#(1)) cr_en <-mkReg(0); // this bit enables the qspi.
212 Reg#(Bit#(32)) cr=concatReg19(cr_prescaler,cr_pmm,cr_apms,readOnlyReg(1'b0),cr_toie,cr_smie,cr_ftie,cr_tcie,cr_teie,readOnlyReg(4'd0),cr_fthres,cr_fsel,cr_dfm,readOnlyReg(1'b0),cr_sshift,cr_tcen,cr_dmaen,cr_abort,cr_en);
214 Reg#(Bit#(5)) fsize<-mkReg(0);
215 Reg#(Bit#(5)) dcr_fsize =conditionalWrite(fsize,sr_busy==0); // flash memory size.
216 Reg#(Bit#(3)) csht <-mkReg(0);
217 Reg#(Bit#(3)) dcr_csht = conditionalWrite(csht,sr_busy==0); // chip select high time.
218 Reg#(Bit#(1)) ckmode <-mkReg(0);
219 Reg#(Bit#(1)) dcr_ckmode =conditionalWrite(ckmode,sr_busy==0); // mode 0 or mode 3.
220 Reg#(Bit#(8)) dcr_mode_byte <- mkReg(0);
221 Reg#(Bit#(32)) dcr = concatReg7(readOnlyReg(3'd0),dcr_mode_byte,dcr_fsize,readOnlyReg(5'd0),dcr_csht,readOnlyReg(7'd0),dcr_ckmode);
222 Reg#(Bit#(32)) rg_mode_bytes = concatReg2(dcr_mode_byte,readOnlyReg(24'd0));
223 Reg#(Bit#(5)) rg_mode_byte_counter <- mkReg('d31);
225 Reg#(Bit#(1)) fcr_ctof <-mkReg(0); // writing 1 clears the sr_tof flag.
226 Reg#(Bit#(1)) fcr_csmf <-mkReg(0); // writing 1 clears the sr_smf flag.
227 Reg#(Bit#(1)) fcr_ctcf <-mkReg(0); // writing 1 clears the sr_tcf flag.
228 Reg#(Bit#(1)) fcr_ctef <-mkReg(0); // writing 1 clears the sr_tef flag.
229 Reg#(Bit#(32)) fcr=concatReg6(readOnlyReg(27'd0),clearSideEffect(fcr_ctof,sr_tof._write(0),noAction),clearSideEffect(fcr_csmf,sr_smf._write(0),noAction),readOnlyReg(1'b0),clearSideEffect(fcr_ctcf,sr_tcf._write(0),delay_sr_tcf._write(0)),clearSideEffect(fcr_ctef,sr_tef._write(0),noAction));
231 Reg#(Bit#(32)) data_length<-mkReg(0);
232 Reg#(Bit#(32)) dlr=conditionalWrite(data_length,sr_busy==0); // data length register
234 Reg#(Bit#(1)) ddrm<-mkReg(0);
235 Reg#(Bit#(1)) ccr_ddrm =conditionalWrite(ddrm,sr_busy==0); // double data rate mode.
236 Reg#(Bit#(1)) dhhc <-mkReg(0);
237 Reg#(Bit#(1)) ccr_dhhc =conditionalWrite(dhhc,sr_busy==0); // delay output by 1/4 in DDR mode. TODO: Not required.
238 Reg#(Bit#(1)) sioo <-mkReg(0);
239 Reg#(Bit#(1)) ccr_sioo =conditionalWrite(sioo,sr_busy==0); // send instruction based on mode selected.
240 Reg#(Bit#(2)) fmode <-mkReg(0);
241 Reg#(Bit#(2)) ccr_fmode =conditionalWrite(fmode,sr_busy==0); // 00: indirect Read, 01: indirect Write, 10: Auto polling, 11: MMapped.
242 Reg#(Bit#(2)) dmode <-mkReg(0);
243 Reg#(Bit#(2)) ccr_dmode =conditionalWrite(dmode,sr_busy==0); // data mode. 01: single line, 10: two line, 11: four lines.
244 Reg#(Bit#(5)) dcyc <-mkReg(0);
245 Reg#(Bit#(5)) ccr_dcyc =conditionalWrite(dcyc,sr_busy==0); // number of dummy cycles.
246 Reg#(Bit#(2)) absize <-mkReg(0);
247 Reg#(Bit#(2)) ccr_absize=conditionalWrite(absize,sr_busy==0); // number of alternate byte sizes.
248 Reg#(Bit#(2)) abmode <-mkReg(0);
249 Reg#(Bit#(2)) ccr_abmode=conditionalWrite(abmode,sr_busy==0); // alternate byte mode.
250 Reg#(Bit#(2)) adsize <-mkReg(0);
251 Reg#(Bit#(2)) ccr_adsize=conditionalWrite(adsize,sr_busy==0); // address size.
252 Reg#(Bit#(2)) admode <-mkReg(0);
253 Reg#(Bit#(2)) ccr_admode=conditionalWrite(admode,sr_busy==0); // address mode.
254 Reg#(Bit#(2)) imode <-mkReg(0);
255 Reg#(Bit#(2)) ccr_imode =conditionalWrite(imode,sr_busy==0); // instruction mode.
256 Reg#(Bit#(8)) instruction <-mkReg(0);
257 Reg#(Bit#(8)) ccr_instruction =conditionalWrite(instruction,sr_busy==0); // instruction to be sent externally.
258 Reg#(Bit#(1)) ccr_dummy_confirmation <- mkReg(0); //Programming Dummy confirmation bit needed by Micron model to trigger XIP mode
259 Reg#(Bit#(1)) ccr_dummy_bit <- mkReg(0); //Dummy bit to be sent
260 Reg#(Bit#(32)) ccr =writeCCREffect(concatReg14(ccr_ddrm,ccr_dhhc,ccr_dummy_bit,ccr_sioo,ccr_fmode,ccr_dmode,ccr_dummy_confirmation,ccr_dcyc,ccr_absize,ccr_abmode,ccr_adsize,ccr_admode,ccr_imode,ccr_instruction),wr_instruction_written._write(True),first_read._write(True));
262 Reg#(Bit#(32)) mm_data_length <-mkConfigReg(0);
263 Reg#(Bit#(28)) mm_address <-mkConfigReg(0);
264 Reg#(Bit#(28)) rg_prev_addr <- mkConfigReg(0);
265 Reg#(Bit#(32)) rg_address <-mkReg(0);
266 Reg#(Bit#(32)) ar =conditionalWrite(writeSideEffect(rg_address,wr_address_written._write(True)),sr_busy==0 && ccr_fmode!='b11); // address register
268 Reg#(Bit#(32)) rg_alternatebyte_reg<-mkReg(0);
269 Reg#(Bit#(32)) abr=conditionalWrite(rg_alternatebyte_reg,sr_busy==0); // alternate byte register
271 Reg#(Bit#(32)) rg_data <-mkReg(0);
272 Reg#(Bit#(32)) dr =writeSideEffect(rg_data,wr_data_written._write(True)); // data register
274 Reg#(Bit#(32)) rg_psmkr <-mkReg(0);
275 Reg#(Bit#(32)) psmkr =conditionalWrite(rg_psmkr,sr_busy==0); // polling status mask register
277 Reg#(Bit#(32)) rg_psmar <-mkReg(0);
278 Reg#(Bit#(32)) psmar =conditionalWrite(rg_psmar,sr_busy==0); // polling statue match register
280 Reg#(Bit#(16)) pir_interval <-mkReg(0); // polling interval
281 Reg#(Bit#(32)) pir =conditionalWrite(concatReg2(readOnlyReg(16'd0),pir_interval),sr_busy==0); // polling interval register
283 Reg#(Bit#(16)) lptr_timeout <-mkReg(0); // timeout period
284 Reg#(Bit#(32)) lptr =conditionalWrite(concatReg2(readOnlyReg(16'd0),lptr_timeout),sr_busy==0); // low power timeout register.
285 Reg#(Bool) thres <- mkReg(False);
286 Reg#(Bit#(32)) sdio0r <- mkReg(32'h00000073);
287 Reg#(Bit#(32)) sdio1r <- mkReg(32'h00000073);
288 Reg#(Bit#(32)) sdio2r <- mkReg(32'h00000073);
289 Reg#(Bit#(32)) sdio3r <- mkReg(32'h00000073);
290 Reg#(Bool) rg_request_ready <- mkReg(True);
291 Bool ddr_clock = ((wr_sdr_clock&&!wr_sdr_delayed)||(!wr_sdr_clock&&wr_sdr_delayed));
292 Bool transfer_cond = (sr_busy==1 && cr_abort==0 && cr_en==1);
293 Bool clock_cond = ((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1));
294 Bool qspi_flush = (cr_abort==1 || cr_en==0);
295 /*************** End of QSPI defined Registers *****************/
296 function Reg#(Bit#(32)) access_register(Bit#(8) address);
297 Reg#(Bit#(32)) register=(
316 default: readOnlyReg(0);
322 /* This function defines the next phase that needs to be executed. indicates if
323 the operation is over and also the value of rg_count_bits for the next phase*/
324 function Tuple3#(Bit#(32),Bit#(1),Phase) phase_change(Phase current_phase, Bit#(32) count_val, Bit#(1) smf);
325 Phase next_phase=Idle;
326 if(current_phase==Idle)
327 next_phase=Instruction_phase;
328 if(current_phase==Instruction_phase)
329 next_phase=Address_phase;
330 if(current_phase==Address_phase)
331 next_phase=AlternateByte_phase;
332 if(current_phase==AlternateByte_phase)
333 next_phase=Dummy_phase;
334 if(current_phase==Dummy_phase)
335 next_phase=(ccr_fmode=='b00)?DataWrite_phase:DataRead_phase;
336 if(current_phase==DataRead_phase)begin
337 if(ccr_fmode=='b01 || ccr_fmode=='b10) // indirect modes
339 else if(ccr_fmode=='b10) // auto-status polling mode
343 next_phase=Dummy_phase;
345 next_phase=DataRead_phase; //Memory Mapped mode
347 if(current_phase==DataWrite_phase)
350 if(next_phase==Instruction_phase && (ccr_imode==0||(ccr_sioo==1 && instruction_sent))) // if single instruction mode or no instruction mode
351 next_phase=Address_phase;
352 if(next_phase==Address_phase && ccr_admode==0)
353 next_phase=AlternateByte_phase;
354 if(next_phase==AlternateByte_phase && ccr_abmode==0)
355 next_phase=Dummy_phase;
356 if(next_phase==Dummy_phase && ccr_dcyc==0)
357 next_phase=ccr_fmode==0?DataWrite_phase:DataRead_phase;
358 if(next_phase==Dummy_phase && (ccr_fmode=='b10 && pir_interval==0))begin // TODO Check if this is correct or needs more logic.
359 next_phase=Instruction_phase;
361 if((next_phase==DataWrite_phase || next_phase==DataRead_phase) && ccr_dmode==0 && ccr_fmode!='b11)begin
362 if(ccr_fmode=='b01 || ccr_fmode=='b00)
364 else if(ccr_fmode=='b10)
368 next_phase=Dummy_phase;
371 if(next_phase==Instruction_phase)begin
374 if(next_phase==Address_phase)begin
375 count_val=(ccr_fmode=='b11)?32:(case(ccr_adsize) 0:8; 1:16; 2:24; 3:32; endcase);
377 if(next_phase==AlternateByte_phase)begin
378 count_val=(case(ccr_absize) 0:8; 1:16; 2:24; 3:32; endcase);
380 if(next_phase==Dummy_phase)begin
381 count_val=(ccr_fmode=='b10)? zeroExtend(pir_interval):zeroExtend(ccr_dcyc);
383 if(next_phase==DataWrite_phase)begin
386 if(next_phase==DataRead_phase)begin
390 if(current_phase!=Idle && next_phase==Idle && (ccr_fmode=='b00 || ccr_fmode=='b01))begin // only in indirect mode raise completion of transfer TODO remove ccr_fmode=='b11 from this line.
393 return tuple3(count_val,tcf,next_phase);
396 Wrapper3#(Phase,Bit#(32),Bit#(1),Tuple3#(Bit#(32),Bit#(1),Phase)) change_phase<-mkUniqueWrapper3(phase_change);
397 /* This rule receives the write request from the AXI and updates the relevant
398 QSPI register set using the lower 12 bits as address map */
399 rule rl_write_request_from_AXI;
400 let aw <- pop_o (s_xactor.o_wr_addr);
401 let w <- pop_o (s_xactor.o_wr_data);
402 AXI4_Lite_Resp axi4_bresp = AXI4_LITE_OKAY;
403 if(ccr_fmode=='b11 && aw.awaddr[7:0]==`DR) begin //Undefined behavior when written into integral fields in CR, CCR!!!
404 axi4_bresp = AXI4_LITE_SLVERR;
405 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because store in memory mapped mode and not clearing Interrupt Flags"); `endif
407 `ifdef verbose $display($time,"\tReceived AXI write request to Address: %h Data: %h Size: %h",aw.awaddr,w.wdata,aw.awsize); `endif
408 if(aw.awaddr[7:0]==`DR)begin
409 if(aw.awsize==0)begin
410 dr[7:0]<=w.wdata[7:0];
411 Vector#(4,Bit#(8)) temp=newVector();
412 temp[0]=w.wdata[7:0];
413 if(fifo.enqReadyN(1))
416 else if(aw.awsize==1)begin
417 dr[15:0]<=w.wdata[15:0];
418 Vector#(4,Bit#(8)) temp = newVector();
419 temp[0]=w.wdata[7:0];
420 temp[1]=w.wdata[15:8];
421 if(fifo.enqReadyN(2))
424 else if(aw.awsize==2)begin
426 Vector#(4,Bit#(8)) temp = newVector();
427 temp[3]=w.wdata[31:24];
428 temp[2]=w.wdata[23:16];
429 temp[1]=w.wdata[15:8];
430 temp[0]=w.wdata[7:0];
431 if(fifo.enqReadyN(4))
435 axi4_bresp = AXI4_LITE_SLVERR;
436 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because DR awsize is 64-bit"); `endif
440 let reg1=access_register(aw.awaddr[7:0]);
441 `ifdef verbose $display("Write Reg access: %h Write Data: %h Size: %h",aw.awaddr[7:0],w.wdata,aw.awsize); `endif
442 //Byte and Half-Word Writes are not permitted in ConfigReg Space
443 if(aw.awsize==2) // 32 bits
446 axi4_bresp = AXI4_LITE_SLVERR;
447 `ifdef verbose $display("Sending SLVERR because Accessed register's awsize was different"); `endif
451 let b = AXI4_Lite_Wr_Resp {bresp: axi4_bresp, buser: aw.awuser};
452 s_xactor.i_wr_resp.enq (b);
455 /* This rule receives the read request from the AXI and responds with the relevant
456 QSPI register set using the lower 12 bits as address map */
457 (*descending_urgency="rl_read_request_from_AXI,rl_write_request_from_AXI"*) //experimental
458 rule rl_read_request_from_AXI(rg_request_ready==True);
459 let axir<- pop_o(s_xactor.o_rd_addr);
460 Bool request_ready = True;
461 `ifdef verbose $display($time,"\tReceived AXI read request to Address: %h Size: %h",axir.araddr,axir.arsize); `endif
462 if((axir.araddr[27:0]>=`STARTMM && axir.araddr[27:0]<=`ENDMM) && axir.araddr[31]==1'b1)begin // memory mapped space
464 wr_read_request_from_AXI<=True; //Could this lead to some error? Need to think about this, without fail
465 AXI4_Lite_Resp axi4_rresp = AXI4_LITE_OKAY;
466 mm_address<=truncate(axir.araddr);
467 Bit#(4) data_length = axir.arsize==0?1:axir.arsize==1?2:axir.arsize==2?4:8;
468 mm_data_length<= zeroExtend(data_length);
469 Bit#(28) address_limit = 1 << dcr_fsize;
471 //It is forbidden to access the flash bank area before the SPI is properly configured -- fmode is '11??
472 //If not sending a SLVERR now if the mode is not memory mapped and if an access is made outside allowed
473 if(ccr_fmode!='b11 || axir.araddr[27:0] > address_limit) begin
474 `ifdef verbose $display("Sending Slave Error ccr_fmode: %h mm_address: %h address_limit: %h dcr_fsize: %h",ccr_fmode,mm_address,address_limit, dcr_fsize); `endif
475 axi4_rresp = AXI4_LITE_SLVERR;
476 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: 0 , ruser: 0};
477 s_xactor.i_rd_data.enq(r);
478 axi4_rresp = AXI4_LITE_SLVERR;
479 rg_phase <= Idle; //Will this work?
482 ncs <= 1; //Just resetting all the parameters, just in case. Should Ask Neel
485 else if(sr_busy==1 ||thres) begin //Bus is busy with Memory mapped maybe?
486 `ifdef verbose $display($time,"sr_busy: %d, thres: %d rg_prev_addr: %h axir.araddr: %h fifo_count: %d", sr_busy, thres, rg_prev_addr, axir.araddr, fifo.count); `endif
487 Bit#(28) eff_addr = rg_prev_addr + zeroExtend(data_length);
488 if((eff_addr!= truncate(axir.araddr)) || pack(fifo.count)==0 || ccr_dummy_bit==1'b1) begin
489 `ifdef verbose $display($time,"Not Equal eff_addr: %h mm_address : %h axir.araddr: %h rg_prev_addr: %h data_length : %h sum : %h fifo.count: %h ccr_dummy_bit: %h",eff_addr,mm_address,axir.araddr,rg_prev_addr,data_length,rg_prev_addr+zeroExtend(data_length),pack(fifo.count),ccr_dummy_bit); `endif
495 //$display($time,"Setting Thres to FALSE");
497 request_ready = False;
499 else if(!first_read) begin
500 request_ready = True;
501 rg_prev_addr <= truncate(axir.araddr);
503 if(axir.arsize==0) begin // 8 bits
504 if(fifo.deqReadyN(1))begin
505 let temp=fifo.first[0];
506 reg1=duplicate(temp);
510 else if(axir.arsize==1) begin // 16 bits
511 if(fifo.deqReadyN(2)) begin
512 let temp={fifo.first[0],fifo.first[1]};
513 reg1=duplicate(temp);
517 else if(axir.arsize==2) begin // 32 bits
518 if(fifo.deqReadyN(4)) begin
519 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
520 reg1=duplicate(temp);
525 axi4_rresp = AXI4_LITE_SLVERR;
526 `ifdef verbose $display("Sending Response to the core: reg1: %h", reg1); `endif
527 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: duplicate(reg1) , ruser: 0};
528 s_xactor.i_rd_data.enq(r);
533 let reg1=access_register(axir.araddr[7:0]);
534 `ifdef verbose $display("Reg Read Access: %h arsize: %h",axir.araddr[7:0], axir.arsize); `endif
535 if(axir.araddr[7:0]==`SR)
536 wr_status_read<=True;
537 if(axir.araddr[7:0]==`DR)begin // accessing the data register for read.
538 `ifdef verbose $display("Accessed DR fifo_count : %d axi.arsize: %d", fifo.count, axir.arsize); `endif
541 if(axir.arsize==0) begin // 8 bits
542 if(fifo.deqReadyN(1))begin
543 let temp=fifo.first[0];
544 reg1=duplicate(temp);
548 else if(axir.arsize==1) begin // 16 bits
549 if(fifo.deqReadyN(2)) begin
550 let temp={fifo.first[0],fifo.first[1]};
551 reg1=duplicate(temp);
555 else /*if(axir.arsize==2)*/ begin // 32 bits -- Even if the request is a long int, respond with int since that's the max we can do
556 if(fifo.deqReadyN(4)) begin
557 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
558 reg1=duplicate(temp);
563 `ifdef verbose $display("Sending Response : reg1: %x", reg1); `endif
564 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(reg1) ,ruser: 0};
565 request_ready = True;
566 s_xactor.i_rd_data.enq(r);
568 rg_request_ready <= request_ready;
569 `ifdef verbose $display($time,"QSPI: Is Request ready? : %h",request_ready); `endif
573 rule timeout_counter;
574 if(cr_tcen==1 && sr_tof==0) // timecounter is enabled
575 if(timecounter==lptr_timeout[15:0])begin
580 timecounter<=timecounter+1;
583 rule delayed_sr_tcf_signal(transfer_cond &&
584 ((ccr_ddrm==1 && ddr_clock && (ccr_admode!=0 || ccr_dmode!=0)) || wr_sdr_clock));
585 sr_tcf<=delay_sr_tcf;
588 rule delayed_ncs_generation;
593 wr_sdr_delayed <= wr_sdr_clock;
597 /* This rule generates the clk signal. The Prescaler register defines the
598 division factor wrt to the Global clock. The prescaler will only work when the
599 chip select is low i.e when the operation has been initiated. */
600 rule rl_generate_clk_from_master;
601 if(delay_ncs==1)begin
604 `ifdef verbose1 $display("dcr_ckmode: %h",dcr_ckmode); `endif
607 let half_clock_value=cr_prescaler>>1;
608 if(cr_prescaler[0]==0)begin // odd division
609 if(rg_clk_counter<=half_clock_value)
613 if(rg_clk_counter==cr_prescaler)
616 rg_clk_counter<=rg_clk_counter+1;
617 if(rg_clk_counter == half_clock_value || rg_clk_counter==cr_prescaler)begin
618 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
621 else begin // even division
622 if(rg_clk_counter==half_clock_value)begin
625 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
627 else if(delay_ncs==0)
628 rg_clk_counter<=rg_clk_counter+1;
633 /* update the status flag on each cycle */
634 rule rl_update_fifo_level;
635 sr_flevel<=pack(fifo.count);
637 /* set the fifo threshold flag when the FIFO level is equal to the FTHRESH value */
638 (*preempts="rl_set_busy_signal,rl_update_threshold_flag"*)
639 rule rl_update_threshold_flag;
640 if(ccr_fmode=='b00)begin// indirect write mode
641 sr_ftf<=pack(16-pack(fifo.count)>={1'b0,cr_fthres}+1);
643 else if(ccr_fmode=='b01) begin
644 sr_ftf<=pack(pack(fifo.count)>=({1'b0,cr_fthres}+1));
645 `ifdef verbose1 $display("fifo count: %d fthres: %d",fifo.count,cr_fthres); `endif
647 else if(ccr_fmode=='b10 && wr_status_read)begin // auto_status polling mode
650 else if(ccr_fmode=='b10 && wr_data_read)begin // auto_status polling mode
653 else if(ccr_fmode=='b11 && pack(fifo.count)>={1'b0,cr_fthres}+1) begin
656 rg_phase<=Idle; // Will this work?
658 rg_request_ready <= True;
659 // $display($time,"THRES is being set to TRUE kyaaaa?");
663 /* If abort is raised or the QSPI is disabled go back to Idle Phase*/
664 //(*descending_urgency = "if_abort,rl_read_request_from_AXI"*)
665 //(*descending_urgency = "if_abort,rl_write_request_from_AXI"*)
666 (*preempts = "if_abort,rl_update_threshold_flag"*)
667 rule if_abort(qspi_flush);
668 //$display("Received Abort or Disable request, going to idle");
675 instruction_sent <= False;
676 half_cycle_delay <= False;
677 fifo.clear(); //What if its already empty? clearing the fifo, so doesn't matter
680 /*operate the busy signal in different mode */
681 rule rl_reset_busy_signal(sr_busy==1);
686 else if(ccr_fmode=='b00 || ccr_fmode=='b01)begin // indirect write or read mode;
687 if(/*fifo.count==0 &&*/ sr_tcf==1)begin // if FIFO is empty and the transaction is complete
692 else if(ccr_fmode=='b10)begin // automatic polling mode
698 else if(ccr_fmode=='b11)begin
699 if(sr_tof==1 || cr_en==0 || cr_abort==1) begin// timeout event
705 (*descending_urgency="rl_set_busy_signal,rl_read_request_from_AXI"*)
706 (*descending_urgency="rl_set_busy_signal,rl_write_request_from_AXI"*)
707 rule rl_set_busy_signal(sr_busy==0 && rg_phase==Idle && cr_abort==0 && cr_en==1);
709 instruction_sent<=False;
710 `ifdef verbose1 $display($time,"\tWaiting for change in phase wr_read_request_from_AXI: %b ccr_fmode: %h thres: %h",wr_read_request_from_AXI,ccr_fmode,thres); `endif
711 if(wr_instruction_written)begin
714 rg_phase<=Instruction_phase;
717 else if((wr_address_written && ccr_admode!=0 && (ccr_fmode=='b01 || ccr_dmode=='d0 || ccr_fmode=='b10))|| (wr_data_written && ccr_admode!=0 && ccr_dmode!=0 && ccr_fmode=='b00))begin
718 sr_busy<=1; // start some transaction
719 `ifdef verbose $display("Address Written and going to Some mode"); `endif
721 let {x,y,z}<-change_phase.func(rg_phase,0,0);
725 `ifdef verbose $display("Mode is :",fshow(z),"Count_bits : %d",x); `endif
726 if(z==DataRead_phase)
729 else if(wr_read_request_from_AXI && ccr_fmode=='b11 && !thres)begin // memory-mapped mode.
730 `ifdef verbose $display("Entering Memory mapped mode"); `endif
733 let {x,y,z}<-change_phase.func(rg_phase,0,0);
737 `ifdef verbose $display("rg_phase :",fshow(z)); `endif
738 if(z==DataRead_phase)
743 /* This rule generates the error signal interrupt in different scenarios */
744 rule set_error_signal;
745 Bit#(32) actual_address=1<<(dcr_fsize);
746 if(wr_address_written && ar>actual_address && (ccr_fmode=='b00 || ccr_fmode=='b01))
748 else if(wr_address_written && ar+dlr>actual_address &&(ccr_fmode=='b00 || ccr_fmode=='b01))
750 else if(wr_address_written)
754 /* Rule to transfer the instruction of 8-bits outside. THe size of instruction is fixed
755 to 8 bits by protocol. Instruction phase will always be in SDR mode */
756 rule rl_transfer_instruction(rg_phase==Instruction_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
757 Bool end_of_phase=False;
758 let reverse_instruction=ccr_instruction;
759 let count_val=rg_count_bits;
760 `ifdef verbose1 $display("Executing Instruction Phase SPI Mode: %b Count_bits: %d InstructionReverse: %h",ccr_imode,rg_count_bits,reverse_instruction); `endif
762 if(ccr_imode=='b01)begin // single spi mode;
764 rg_output<={1'b1,1'b0,1'b0,reverse_instruction[rg_count_bits-1]};
765 if(rg_count_bits==1)begin// end of instruction stream
769 count_val=rg_count_bits-1;
771 else if (ccr_imode=='b10)begin // dual mode;
773 rg_output<={1'b1,1'b0,reverse_instruction[rg_count_bits-1:rg_count_bits-2]};
774 if(rg_count_bits==2)begin// end of instruction stream
778 count_val=rg_count_bits-2;
780 else if (ccr_imode=='b11)begin // quad mode;
782 rg_output<=reverse_instruction[rg_count_bits-1:rg_count_bits-4];
783 if(rg_count_bits==4)begin// end of instruction stream
787 count_val=rg_count_bits-4;
789 if(end_of_phase || ccr_imode==0)begin // end of instruction or no instruction phase
790 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
791 instruction_sent<=True;
797 half_cycle_delay<=True;
798 if(z==DataRead_phase)
802 rg_count_bits<=count_val;
803 rg_output_en<=enable_o;
806 /* Rule to transfer the address bits of address outside. The size of address is
807 defined by the ccr_adsize register in ccr */
808 rule rl_transfer_address(rg_phase==Address_phase && transfer_cond && clock_cond && !qspi_flush);
809 if(half_cycle_delay) begin
810 half_cycle_delay<=False;
811 read_true <= True; //A workaround for the delay .. For DDR mode, the clock should be pushed one cycle and not half
816 Bool end_of_phase=False;
818 let count_val=rg_count_bits;
819 Bit#(32) address=(ccr_fmode=='b11)?zeroExtend(mm_address):ar;
820 rg_prev_addr <= truncate(address);
821 `ifdef verbose1 $display($time,"Executing Address Phase SPI Mode: %b Address Size: %d Count_bits: %d Address: %b",ccr_admode,ccr_adsize,rg_count_bits,address); `endif
822 if(ccr_admode=='b01)begin // single spi mode;
824 rg_output<={1'b1,1'b0,1'b0,address[rg_count_bits-1]};
825 `ifdef verbose $display($time,"Single: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
826 if(rg_count_bits==1)begin// end of address stream
830 count_val=rg_count_bits-1;
832 else if (ccr_admode=='b10)begin // dual mode;
834 rg_output<={1'b1,1'b0,address[rg_count_bits-1:rg_count_bits-2]};
835 `ifdef verbose $display($time,"Double: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
836 if(rg_count_bits==2)begin// end of address stream
840 count_val=rg_count_bits-2;
842 else if (ccr_admode=='b11)begin // quad mode;
844 rg_output<=address[rg_count_bits-1:rg_count_bits-4];
845 `ifdef verbose $display($time,"Quad: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
846 if(rg_count_bits==4)begin// end of address stream
850 count_val=rg_count_bits-4;
852 if(end_of_phase || ccr_admode==0)begin // end of address phase
853 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
858 if(z==DataRead_phase)
862 rg_count_bits<=count_val;
863 rg_output_en<=enable_o;
867 /* Rule to transfer the alternate bytes. The size of alternate bytes is
868 defined by the ccr_absize register in ccr */
869 rule rl_transfer_alternatebytes(rg_phase==AlternateByte_phase && transfer_cond && clock_cond && !qspi_flush);
870 Bool end_of_phase=False;
871 let count_val=rg_count_bits;
872 `ifdef verbose1 $display("Executing AltByte Phase SPI Mode: %b AltByte Size: %d Count_bits: %d AltByte: %b",ccr_abmode,ccr_absize,rg_count_bits,abr); `endif
874 if(ccr_abmode=='b01)begin // single spi mode;
876 rg_output<={1'b1,1'b0,1'b0,abr[rg_count_bits-1]};
877 if(rg_count_bits==1)begin// end of instruction stream
881 count_val=rg_count_bits-1;
883 else if (ccr_abmode=='b10)begin // dual mode;
885 rg_output<={1'b1,1'b0,abr[rg_count_bits-1:rg_count_bits-2]};
886 if(rg_count_bits==2)begin// end of instruction stream
890 count_val=rg_count_bits-2;
892 else if (ccr_abmode=='b11)begin // quad mode;
894 rg_output<=abr[rg_count_bits-1:rg_count_bits-4];
895 if(rg_count_bits==4)begin// end of instruction stream
899 count_val=rg_count_bits-4;
901 if(end_of_phase || ccr_abmode==0)begin // end of alternate byte phase
902 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
907 if(z==DataRead_phase)
908 read_true <= True;end
910 rg_count_bits<=count_val;
911 rg_output_en<=enable_o;
915 rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
916 let {x,y,z} <- change_phase.func(rg_phase,rg_count_bits,0);
917 Bit#(5) count_val = rg_mode_byte_counter;
918 Bit#(4) enable_o = rg_output_en;
919 `ifdef verbose $display("\t Executing Dummy Phase: rg_mode_bytes: %b rg_mode_byte_counter: %d",rg_mode_bytes, rg_mode_byte_counter); `endif
920 if(ccr_dmode==1) begin
921 if(ccr_dummy_confirmation==1) begin
922 //rg_output_en <= 4'b1101;
924 rg_output <= {1'b1,1'b0,1'b0,rg_mode_bytes[rg_mode_byte_counter]};
926 count_val = count_val - 1;
931 //rg_output_en <= 4'b1101;
933 rg_output <= {1'b1,1'b0,1'b0,1'b0};
936 else if(ccr_dmode==2) begin
937 if(ccr_dummy_confirmation==1) begin
938 //rg_output_en <= 4'b1111;
940 rg_output <= {1'b1,1'b0,rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-1]};
942 count_val = count_val - 2;
947 //rg_output_en <= 4'b1100;
949 rg_output <= {1'b1,1'b0,1'b0,1'b0};
953 if(ccr_dummy_confirmation==1) begin
954 //rg_output_en <= 4'b1111;
956 rg_output <= rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-3];
958 count_val = count_val - 4;
963 //rg_output_en <= 4'b0000;
967 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
970 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
971 if(z==DataRead_phase)
975 rg_mode_byte_counter <= 'd-1; //All ones
977 half_cycle_delay<=True;
980 rg_count_bits<=rg_count_bits-1;
981 rg_mode_byte_counter <= count_val;
982 rg_output_en <= enable_o;
987 /* Rule to transfer the dummy_cycles. The size of dummy cycles is
988 defined by the ccr_dcyc register in ccr. The number of dummy cycles should be calculated of
989 the complete cycle even in DDR mode hence using sdr clock*/
990 /* rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
991 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,0);
992 `ifdef verbose $display($time,"Executing Dummy Phase, Dummy_confirmation_bit : %d dummy_bit : %d", ccr_dummy_confirmation, ccr_dummy_bit); `endif
993 if(ccr_dmode==1) begin
994 if(ccr_dummy_confirmation==1) begin
995 rg_output_en <= 4'b1101;
996 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
997 ccr_dummy_confirmation<=0;
1000 rg_output_en <= 4'b1101;
1001 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1004 else if(ccr_dmode==2) begin
1005 if(ccr_dummy_confirmation==1) begin
1006 rg_output_en <= 4'b1101;
1007 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
1008 ccr_dummy_confirmation <= 0;
1011 rg_output_en <= 4'b1100;
1012 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1016 if(ccr_dummy_confirmation==1) begin
1017 `ifdef verbose $display("Data going to output %d", ccr_dummy_bit); `endif
1019 rg_output[0] <= ccr_dummy_bit;
1020 ccr_dummy_confirmation<=0;
1025 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
1028 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
1029 if(z==DataRead_phase)
1034 half_cycle_delay<=True;
1037 rg_count_bits<=rg_count_bits-1;
1041 /* read data from the flash memory and store it in the DLR register. Simulataneously
1042 put Bytes in the FIFO*/
1043 (*descending_urgency="rl_data_read_phase,rl_read_request_from_AXI"*)
1044 (*descending_urgency="rl_data_read_phase,rl_write_request_from_AXI"*)
1045 rule rl_data_read_phase(rg_phase==DataRead_phase /*&& ccr_fmode!='b11*/ && transfer_cond && clock_cond && !qspi_flush);
1047 if(half_cycle_delay || read_true) begin
1048 half_cycle_delay<=False;
1052 Bit#(32) data_reg=dr;
1053 Bit#(32) count_byte=rg_count_bytes;
1054 Bit#(32) count_bits=rg_count_bits;
1055 Bit#(32) data_length1=(ccr_fmode=='b11)?mm_data_length:dlr;
1056 `ifdef verbose1 $display($time,"Executing DataRead Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b ccr_ddrm: %b",ccr_dmode,data_length1,rg_count_bits,rg_input,ccr_ddrm); `endif
1057 /* write incoming bit to the data register */
1058 if(ccr_dmode==1)begin // single line mode;
1059 data_reg=data_reg<<1;
1060 data_reg[0]=rg_input[1];
1061 `ifdef verbose $display($time,"Single data_reg : %b",data_reg); `endif
1062 count_bits=count_bits+1;
1063 rg_output_en <= 4'b1101;
1064 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1067 else if(ccr_dmode==2)begin // dual line mode;
1068 rg_output_en <= 4'b1100;
1069 data_reg=data_reg<<2;
1070 data_reg[1:0]=rg_input[1:0];
1071 `ifdef verbose $display($time,"Dual data_reg : %b",data_reg); `endif
1072 count_bits=count_bits+1;
1073 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1075 else if(ccr_dmode==3) begin// quad line mode;
1076 rg_output_en <= 4'b0000;
1077 data_reg=data_reg<<4;
1078 data_reg[3:0]=rg_input;
1079 `ifdef verbose $display($time,"Quad data_reg : %b",data_reg); `endif
1080 count_bits=count_bits+1;
1083 /* write the last successfully received byte into the FIFO */
1084 if(ccr_dmode==1)begin// single line mode
1085 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[2:0]=='b111) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1087 if(rg_count_bits[2:0]=='b111)begin // multiple of eight bits have been read.
1088 `ifdef verbose1 $display("Enquing FIFO"); `endif
1089 Vector#(4,Bit#(8)) temp = newVector();
1090 temp[0]=data_reg[7:0];
1091 `ifdef verbose $display($time,"Single Enqueing FIFO : data is %h",temp[0]); `endif
1094 count_byte=count_byte+1;
1097 else if(ccr_dmode==2) begin // dual line mode
1098 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[1:0]=='b11) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1100 if(rg_count_bits[1:0]=='b11)begin // multiple of eight bits have been read.
1101 `ifdef verbose1 $display("Enquing FIFO"); `endif
1102 Vector#(4,Bit#(8)) temp = newVector();
1103 temp[0]=data_reg[7:0];
1104 `ifdef verbose $display($time,"Dual Enqueing FIFO : data is %h",temp[0]); `endif
1107 count_byte=count_byte+1;
1110 else if(ccr_dmode==3) begin // quad line mode
1111 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[0]=='b1) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1113 if(rg_count_bits[0]=='b1)begin // multiple of eight bits have been read.
1114 `ifdef verbose1 $display("Enquing FIFO"); `endif
1115 Vector#(4,Bit#(8)) temp = newVector();
1116 temp[0]=data_reg[7:0];
1117 `ifdef verbose $display($time,"Quad Enqueing FIFO : data is %h",temp[0]); `endif
1120 count_byte=count_byte+1;
1125 `ifdef verbose $display("count_byte: %d data_length1: %d",count_byte,data_length1); `endif
1126 /* condition for termination of dataread_phase */
1127 if(data_length1!='hFFFFFFFF)begin // if limit is not undefined
1128 if(count_byte==data_length1)begin // if limit has bee reached.
1129 `ifdef verbose $display($time,"Limit has reached: rg_count_bytes %h data_length %h",count_byte,data_length); `endif
1130 if(ccr_fmode=='b10)begin // auto-status polling mode
1131 if(cr_pmm==0)begin // ANDed mode
1132 if((psmar&psmkr) == (psmkr&dr)) // is the unmasked bits match
1137 else begin// ORed mode
1147 else if(ccr_fmode=='b11)begin// memory mapped mode
1148 if(first_read) begin
1149 `ifdef verbose $display("Sending response back to the proc data_reg: %h",data_reg); `endif
1150 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(data_reg) , ruser: 0};
1151 s_xactor.i_rd_data.enq(r);
1152 first_read <= False;
1153 //rg_request_ready <= True;
1156 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf);
1157 /* if(z==DataRead_phase)
1158 read_true <= True;*/
1160 `ifdef verbose $display("rg_phase:",fshow(z),"sr_tcf: %d",y); `endif
1161 sr_tcf<=y; // set completion of transfer flag
1166 rg_count_bytes<=count_byte;
1167 rg_count_bits<=count_bits;
1170 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1171 Bit#(32) new_limit=1<<(dcr_fsize);
1172 `ifdef verbose1 $display("Sending completion -- newlimit : %h",new_limit); `endif
1173 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1174 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf&cr_apms);
1176 if(z==DataRead_phase)
1178 sr_tcf<=y; // set completion of transfer flag
1183 rg_count_bytes<=count_byte;
1184 rg_count_bits<=count_bits;
1187 else begin // keep looping untill abort signal is not raised.
1188 rg_count_bytes<=count_byte;
1189 rg_count_bits<=count_bits;
1196 /* write data from the FIFO to the FLASH. Simulataneously*/
1197 (*descending_urgency="rl_data_write_phase,rl_read_request_from_AXI"*)
1198 (*descending_urgency="rl_data_write_phase,rl_write_request_from_AXI"*)
1199 rule rl_data_write_phase(rg_phase==DataWrite_phase && transfer_cond && clock_cond && !qspi_flush);
1200 if(half_cycle_delay)
1201 half_cycle_delay<=False;
1203 Bit#(8) data_reg=fifo.first()[0];
1204 Bit#(32) count_byte=rg_count_bytes;
1205 Bit#(32) count_bits=rg_count_bits;
1207 /* write incoming bit to the data register */
1208 if(ccr_dmode==1)begin // single line mode;
1210 rg_output<={1'b1,1'b0,1'b0,data_reg[rg_count_bits-1]};
1211 count_bits=count_bits-1;
1213 else if(ccr_dmode==2)begin // dual line mode;
1215 rg_output<={1'b1,1'b0,data_reg[rg_count_bits-1:rg_count_bits-2]};
1216 count_bits=count_bits-2;
1218 else if(ccr_dmode==3) begin// quad line mode;
1220 rg_output<=data_reg[rg_count_bits-1:rg_count_bits-4];
1221 count_bits=count_bits-4;
1223 `ifdef verbose1 $display("Executing DataWrite Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b Enable: %b",ccr_dmode,dlr,rg_count_bits,rg_input,enable_o); `endif
1225 /* write the last successfully received byte into the FIFO */
1226 if(ccr_dmode==1)begin// single line mode
1227 if(rg_count_bits==1)begin // multiple of eight bits have been read.
1229 count_byte=count_byte+1;
1233 else if(ccr_dmode==2) begin // dual line mode
1234 if(rg_count_bits==2)begin // multiple of eight bits have been read.
1236 count_byte=count_byte+1;
1240 else if(ccr_dmode==3) begin // quad line mode
1241 if(rg_count_bits==4)begin // multiple of eight bits have been read.
1243 count_byte=count_byte+1;
1248 /* condition for termination of dataread_phase */
1249 if(dlr!='hFFFFFFFF)begin // if limit is not undefined
1250 if(rg_count_bytes==dlr)begin // if limit has bee reached.
1252 sr_tcf<=1; // set completion of transfer flag
1257 rg_count_bytes<=count_byte;
1258 rg_count_bits<=count_bits;
1261 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1262 Bit#(32) new_limit=1<<(dcr_fsize);
1263 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1265 sr_tcf<=1; // set completion of transfer flag
1270 rg_count_bytes<=count_byte;
1271 rg_count_bits<=count_bits;
1274 else begin // keep looping untill abort signal is not raised.
1275 rg_count_bytes<=count_byte;
1276 rg_count_bits<=count_bits;
1278 rg_output_en<=enable_o;
1282 rule display_all_Registers;
1283 `ifdef verbose1 $display($time,"\tPhase: ",fshow(rg_phase)," CR WRitten %d",wr_instruction_written, "Address Written: %d",wr_address_written); `endif
1284 `ifdef verbose1 $display($time,"\tCR: %h\tDCR: %h\tSR: %h\tFCR: %h",cr,dcr,sr,fcr); `endif
1285 `ifdef verbose1 $display($time,"\tDLR: %h\tCCR: %h\tAR: %h\tABR: %h",dlr,ccr,ar,abr); `endif
1286 `ifdef verbose1 $display($time,"\tDR: %h\tPSMKR: %h\tPSMAR: %h\tPIR: %h",dr,psmkr,psmar,pir,"\n"); `endif
1290 rule delay_phase(((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1)));
1291 rg_phase_delayed<=rg_phase;
1295 interface QSPI_out out;
1296 method Bit#(9) io0_sdio_ctrl;
1299 method Bit#(9) io1_sdio_ctrl;
1302 method Bit#(9) io2_sdio_ctrl;
1305 method Bit#(9) io3_sdio_ctrl;
1308 interface clk_o = interface Get
1309 method ActionValue#(Bit#(1)) get;
1310 return delay_ncs==1?dcr_ckmode:rg_clk;
1313 interface io_out = interface Get
1314 method ActionValue#(Bit#(4)) get;
1318 interface io_out_en = interface Get
1319 method ActionValue#(Bit#(4)) get;
1320 return rg_output_en;
1323 interface io_in = interface Put
1324 method Action put(Bit#(4) in);
1328 interface ncs_o = interface Get
1329 method ActionValue#(Bit#(1)) get;
1335 interface slave= s_xactor.axi_side;
1337 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5=request_ready
1338 return {pack(rg_request_ready),sr_tef&cr_teie, sr_tcf&cr_tcie, sr_ftf&cr_ftie, sr_smf&cr_smie , sr_tof&cr_toie};
1340 `ifdef simulate method curphase = rg_phase_delayed; `endif