src/scoreboard/fu_dep_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class DepCell(Elaboratable):
   8     """ FU Dependency Cell
   9     """
  10     def __init__(self, llen=1):
  11         self.llen = llen
  12         # inputs
  13         self.pend_i = Signal(llen, reset_less=True)    # pending bit in (left)
  14         self.issue_i = Signal(llen, reset_less=True)   # Issue in (top)
  15         self.go_i = Signal(llen, reset_less=True)      # Go read/write in (left)
  16         self.die_i = Signal(llen, reset_less=True)     # Go die in (left)
  17
  18         # wait
  19         self.wait_o = Signal(llen, reset_less=True)  # wait out (right)
  20
  21     def elaborate(self, platform):
  22         m = Module()
  23         m.submodules.l = l = SRLatch(sync=False, llen=self.llen) # async latch
  24
  25         # reset on go HI, set on dest and issue
  26         m.d.comb += l.s.eq(self.issue_i & self.pend_i)
  27         m.d.comb += l.r.eq(self.go_i | self.die_i)
  28
  29         # wait out
  30         m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
  31
  32         return m
  33
  34     def __iter__(self):
  35         yield self.pend_i
  36         yield self.issue_i
  37         yield self.go_i
  38         yield self.die_i
  39         yield self.wait_o
  40
  41     def ports(self):
  42         return list(self)
  43
  44
  45 class FUDependenceCell(Elaboratable):
  46     """ implements 11.4.7 mitch alsup dependence cell, p27
  47     """
  48     def __init__(self, n_fu=1):
  49         self.n_fu = n_fu
  50         # inputs
  51         self.rd_pend_i = Signal(n_fu, reset_less=True) # read pend in (left)
  52         self.wr_pend_i = Signal(n_fu, reset_less=True) # write pend in (left)
  53         self.issue_i = Signal(n_fu, reset_less=True)    # Issue in (top)
  54
  55         self.go_wr_i = Signal(n_fu, reset_less=True) # Go Write in (left)
  56         self.go_rd_i = Signal(n_fu, reset_less=True)  # Go Read in (left)
  57         self.go_die_i = Signal(n_fu, reset_less=True) # Go Die in (left)
  58
  59         # outputs (latched rd/wr wait)
  60         self.rd_wait_o = Signal(n_fu, reset_less=True) # read wait out (right)
  61         self.wr_wait_o = Signal(n_fu, reset_less=True) # write wait out (right)
  62
  63     def elaborate(self, platform):
  64         m = Module()
  65         m.submodules.rd_c = rd_c = DepCell(self.n_fu)
  66         m.submodules.wr_c = wr_c = DepCell(self.n_fu)
  67
  68         # connect issue
  69         for c in [rd_c, wr_c]:
  70             m.d.comb += c.issue_i.eq(self.issue_i)
  71             m.d.comb += c.die_i.eq(self.go_die_i)
  72
  73         # connect go_rd / go_wr
  74         m.d.comb += wr_c.go_i.eq(self.go_wr_i)
  75         m.d.comb += rd_c.go_i.eq(self.go_rd_i)
  76
  77         # connect pend_i
  78         m.d.comb += wr_c.pend_i.eq(self.wr_pend_i)
  79         m.d.comb += rd_c.pend_i.eq(self.rd_pend_i)
  80
  81         # connect output
  82         m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
  83         m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
  84
  85         return m
  86
  87     def __iter__(self):
  88         yield self.rd_pend_i
  89         yield self.wr_pend_i
  90         yield self.issue_i
  91         yield self.go_wr_i
  92         yield self.go_rd_i
  93         yield self.go_die_i
  94         yield self.rd_wait_o
  95         yield self.wr_wait_o
  96
  97     def ports(self):
  98         return list(self)
  99
 100
 101 def dcell_sim(dut):
 102     yield dut.dest_i.eq(1)
 103     yield dut.issue_i.eq(1)
 104     yield
 105     yield dut.issue_i.eq(0)
 106     yield
 107     yield dut.src1_i.eq(1)
 108     yield dut.issue_i.eq(1)
 109     yield
 110     yield dut.issue_i.eq(0)
 111     yield
 112     yield dut.go_rd_i.eq(1)
 113     yield
 114     yield dut.go_rd_i.eq(0)
 115     yield
 116     yield dut.go_wr_i.eq(1)
 117     yield
 118     yield dut.go_wr_i.eq(0)
 119     yield
 120
 121 def test_dcell():
 122     dut = FUDependenceCell()
 123     vl = rtlil.convert(dut, ports=dut.ports())
 124     with open("test_fu_dcell.il", "w") as f:
 125         f.write(vl)
 126
 127     run_simulation(dut, dcell_sim(dut), vcd_name='test_fu_dcell.vcd')
 128
 129 if __name__ == '__main__':
 130     test_dcell()