src/scoreboard/fu_dep_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class DepCell(Elaboratable):
   8     """ FU Dependency Cell
   9     """
  10     def __init__(self):
  11         # inputs
  12         self.pend_i = Signal(reset_less=True)    # pending bit in (left)
  13         self.issue_i = Signal(reset_less=True)   # Issue in (top)
  14         self.go_i = Signal(reset_less=True)      # Go read/write in (left)
  15         self.die_i = Signal(reset_less=True)     # Go die in (left)
  16
  17         # wait
  18         self.wait_o = Signal(reset_less=True)  # wait out (right)
  19
  20     def elaborate(self, platform):
  21         m = Module()
  22         m.submodules.l = l = SRLatch(sync=False) # async latch
  23
  24         # reset on go HI, set on dest and issue
  25         m.d.comb += l.s.eq(self.issue_i & self.pend_i)
  26         m.d.comb += l.r.eq(self.go_i | self.die_i)
  27
  28         # wait out
  29         m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
  30
  31         return m
  32
  33     def __iter__(self):
  34         yield self.pend_i
  35         yield self.issue_i
  36         yield self.go_i
  37         yield self.die_i
  38         yield self.wait_o
  39
  40     def ports(self):
  41         return list(self)
  42
  43
  44 class FUDependenceCell(Elaboratable):
  45     """ implements 11.4.7 mitch alsup dependence cell, p27
  46     """
  47     def __init__(self):
  48         # inputs
  49         self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
  50         self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
  51         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  52
  53         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
  54         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
  55         self.go_die_i = Signal(reset_less=True) # Go Die in (left)
  56
  57         # outputs (latched rd/wr wait)
  58         self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
  59         self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63         m.submodules.rd_c = rd_c = DepCell()
  64         m.submodules.wr_c = wr_c = DepCell()
  65
  66         # connect issue
  67         for c in [rd_c, wr_c]:
  68             m.d.comb += c.issue_i.eq(self.issue_i)
  69             m.d.comb += c.die_i.eq(self.go_die_i)
  70
  71         # connect go_rd / go_wr
  72         m.d.comb += wr_c.go_i.eq(self.go_wr_i)
  73         m.d.comb += rd_c.go_i.eq(self.go_rd_i)
  74
  75         # connect pend_i
  76         m.d.comb += wr_c.pend_i.eq(self.wr_pend_i)
  77         m.d.comb += rd_c.pend_i.eq(self.rd_pend_i)
  78
  79         # connect output
  80         m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
  81         m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
  82
  83         return m
  84
  85     def __iter__(self):
  86         yield self.rd_pend_i
  87         yield self.wr_pend_i
  88         yield self.issue_i
  89         yield self.go_wr_i
  90         yield self.go_rd_i
  91         yield self.go_die_i
  92         yield self.rd_wait_o
  93         yield self.wr_wait_o
  94
  95     def ports(self):
  96         return list(self)
  97
  98
  99 def dcell_sim(dut):
 100     yield dut.dest_i.eq(1)
 101     yield dut.issue_i.eq(1)
 102     yield
 103     yield dut.issue_i.eq(0)
 104     yield
 105     yield dut.src1_i.eq(1)
 106     yield dut.issue_i.eq(1)
 107     yield
 108     yield dut.issue_i.eq(0)
 109     yield
 110     yield dut.go_rd_i.eq(1)
 111     yield
 112     yield dut.go_rd_i.eq(0)
 113     yield
 114     yield dut.go_wr_i.eq(1)
 115     yield
 116     yield dut.go_wr_i.eq(0)
 117     yield
 118
 119 def test_dcell():
 120     dut = FUDependenceCell()
 121     vl = rtlil.convert(dut, ports=dut.ports())
 122     with open("test_fu_dcell.il", "w") as f:
 123         f.write(vl)
 124
 125     run_simulation(dut, dcell_sim(dut), vcd_name='test_fu_dcell.vcd')
 126
 127 if __name__ == '__main__':
 128     test_dcell()