1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Array
, Const
, Record
, Elaboratable
4 from nmigen
.lib
.coding
import Decoder
6 from .shadow_fn
import ShadowFn
9 class RegDecode(Elaboratable
):
10 """ decodes registers into unary
14 * :wid: register file width
16 def __init__(self
, wid
):
20 self
.enable_i
= Signal(reset_less
=True) # enable decoders
21 self
.dest_i
= Signal(max=wid
, reset_less
=True) # Dest R# in
22 self
.src1_i
= Signal(max=wid
, reset_less
=True) # oper1 R# in
23 self
.src2_i
= Signal(max=wid
, reset_less
=True) # oper2 R# in
26 self
.dest_o
= Signal(wid
, reset_less
=True) # Dest unary out
27 self
.src1_o
= Signal(wid
, reset_less
=True) # oper1 unary out
28 self
.src2_o
= Signal(wid
, reset_less
=True) # oper2 unary out
30 def elaborate(self
, platform
):
32 m
.submodules
.dest_d
= dest_d
= Decoder(self
.reg_width
)
33 m
.submodules
.src1_d
= src1_d
= Decoder(self
.reg_width
)
34 m
.submodules
.src2_d
= src2_d
= Decoder(self
.reg_width
)
36 # dest decoder: write-pending
37 for d
, i
, o
in [(dest_d
, self
.dest_i
, self
.dest_o
),
38 (src1_d
, self
.src1_i
, self
.src1_o
),
39 (src2_d
, self
.src2_i
, self
.src2_o
)]:
41 m
.d
.comb
+= d
.n
.eq(~self
.enable_i
)
59 class IssueUnit(Elaboratable
):
60 """ implements 11.4.14 issue unit, p50
64 * :wid: register file width
65 * :n_insns: number of instructions in this issue unit.
67 def __init__(self
, wid
, n_insns
):
69 self
.n_insns
= n_insns
72 self
.store_i
= Signal(reset_less
=True) # instruction is a store
73 self
.dest_i
= Signal(wid
, reset_less
=True) # Dest R in (unary)
75 self
.g_wr_pend_i
= Signal(wid
, reset_less
=True) # write pending vector
77 self
.insn_i
= Signal(n_insns
, reset_less
=True, name
="insn_i")
78 self
.busy_i
= Array(Signal(reset_less
=True, name
="busy_i") \
79 for i
in range(n_insns
))
82 self
.fn_issue_o
= Array(Signal(reset_less
=True, name
="fn_issue_o") \
83 for i
in range(n_insns
))
84 self
.g_issue_o
= Signal(reset_less
=True)
86 def elaborate(self
, platform
):
93 waw_stall
= Signal(reset_less
=True)
94 fu_stall
= Signal(reset_less
=True)
95 pend
= Signal(self
.reg_width
, reset_less
=True)
97 # dest decoder: write-pending
98 m
.d
.comb
+= pend
.eq(self
.dest_i
& self
.g_wr_pend_i
& (~self
.store_i
))
99 m
.d
.comb
+= waw_stall
.eq(pend
.bool())
102 for i
in range(self
.n_insns
):
103 ib_l
.append(self
.insn_i
[i
] & self
.busy_i
[i
])
104 m
.d
.comb
+= fu_stall
.eq(Cat(*ib_l
).bool())
105 m
.d
.comb
+= self
.g_issue_o
.eq(~
(waw_stall | fu_stall
))
106 for i
in range(self
.n_insns
):
107 m
.d
.comb
+= self
.fn_issue_o
[i
].eq(self
.g_issue_o
& self
.insn_i
[i
])
116 yield self
.g_wr_pend_i
117 yield from self
.insn_i
118 yield from self
.busy_i
119 yield from self
.fn_issue_o
126 class IntFPIssueUnit(Elaboratable
):
127 def __init__(self
, wid
, n_int_insns
, n_fp_insns
):
128 self
.i
= IssueUnit(wid
, n_int_insns
)
129 self
.f
= IssueUnit(wid
, n_fp_insns
)
130 self
.issue_o
= Signal(reset_less
=True)
133 self
.int_write_pending_i
= self
.i
.g_wr_pend_i
134 self
.fp_write_pending_i
= self
.f
.g_wr_pend_i
135 self
.int_write_pending_i
.name
= 'int_write_pending_i'
136 self
.fp_write_pending_i
.name
= 'fp_write_pending_i'
138 def elaborate(self
, platform
):
140 m
.submodules
.intissue
= self
.i
141 m
.submodules
.fpissue
= self
.f
143 m
.d
.comb
+= self
.issue_o
.eq(self
.i
.g_issue_o | self
.f
.g_issue_o
)
153 def issue_unit_sim(dut
):
154 yield dut
.dest_i
.eq(1)
155 yield dut
.issue_i
.eq(1)
157 yield dut
.issue_i
.eq(0)
159 yield dut
.src1_i
.eq(1)
160 yield dut
.issue_i
.eq(1)
164 yield dut
.issue_i
.eq(0)
166 yield dut
.go_rd_i
.eq(1)
168 yield dut
.go_rd_i
.eq(0)
170 yield dut
.go_wr_i
.eq(1)
172 yield dut
.go_wr_i
.eq(0)
175 def test_issue_unit():
176 dut
= IssueUnit(32, 3)
177 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
178 with
open("test_issue_unit.il", "w") as f
:
181 dut
= IntFPIssueUnit(32, 3, 3)
182 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
183 with
open("test_intfp_issue_unit.il", "w") as f
:
186 run_simulation(dut
, issue_unit_sim(dut
), vcd_name
='test_issue_unit.vcd')
188 if __name__
== '__main__':