1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Elaboratable
4 from nmutil
.latch
import SRLatch
5 from nmigen
.lib
.coding
import Decoder
8 class ShadowFn(Elaboratable
):
9 """ implements shadowing 11.5.1, p55, just the individual shadow function
14 self
.issue_i
= Signal(reset_less
=True)
15 self
.shadow_i
= Signal(reset_less
=True)
16 self
.s_fail_i
= Signal(reset_less
=True)
17 self
.s_good_i
= Signal(reset_less
=True)
20 self
.shadow_o
= Signal(reset_less
=True)
21 self
.recover_o
= Signal(reset_less
=True)
23 def elaborate(self
, platform
):
25 m
.submodules
.sl
= sl
= SRLatch(sync
=False)
27 m
.d
.comb
+= sl
.s
.eq(self
.shadow_i
& self
.issue_i
)
28 m
.d
.comb
+= sl
.r
.eq(self
.s_good_i
)
29 m
.d
.comb
+= self
.recover_o
.eq(sl
.q
& self
.s_fail_i
)
30 m
.d
.comb
+= self
.shadow_o
.eq(sl
.q
)
46 def shadow_fn_unit_sim(dut
):
47 yield dut
.dest_i
.eq(1)
48 yield dut
.issue_i
.eq(1)
50 yield dut
.issue_i
.eq(0)
52 yield dut
.src1_i
.eq(1)
53 yield dut
.issue_i
.eq(1)
57 yield dut
.issue_i
.eq(0)
59 yield dut
.go_read_i
.eq(1)
61 yield dut
.go_read_i
.eq(0)
63 yield dut
.go_write_i
.eq(1)
65 yield dut
.go_write_i
.eq(0)
69 def test_shadow_fn_unit():
71 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
72 with
open("test_shadow_fn_unit.il", "w") as f
:
75 run_simulation(dut
, shadow_fn_unit_sim(dut
),
76 vcd_name
='test_shadow_fn_unit.vcd')
78 if __name__
== '__main__':