src/simsoctb.v

   1 // Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2 // Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3
   4 `timescale 1 ns / 1 ns
   5
   6 module simsoctb;
   7   // GSR & PUR init requires for Lattice models
   8   GSR GSR_INST (
   9     .GSR(1'b1)
  10   );
  11   PUR PUR_INST (
  12     .PUR (1'b1)
  13   );
  14
  15   reg clkin;
  16   wire sync;
  17   wire sync2x;
  18   wire dramsync;
  19   wire init;
  20
  21   // Generate 100 Mhz clock
  22   always
  23     begin
  24       clkin = 1;
  25       #5;
  26       clkin = 0;
  27       #5;
  28     end
  29
  30   // DDR3 init
  31   wire dram_ck;
  32   wire dram_cke;
  33   wire dram_we_n;
  34   wire dram_cs_n;
  35   wire dram_ras_n;
  36   wire dram_cas_n;
  37   wire [15:0] dram_dq;
  38   inout wire [1:0] dram_dqs;
  39   inout wire [1:0] dram_dqs_n;
  40   wire [13:0] dram_a;
  41   wire [2:0] dram_ba;
  42   wire [1:0] dram_dm;
  43   wire dram_odt;
  44   wire [1:0] dram_tdqs_n;
  45   wire dram_rst;
  46
  47   ddr3 #(
  48     .check_strict_timing(0)
  49   ) ram_chip (
  50     .rst_n(dram_rst),
  51     .ck(dram_ck),
  52     .ck_n(~dram_ck),
  53     .cke(dram_cke),
  54     .cs_n(~dram_cs_n),
  55     .ras_n(dram_ras_n),
  56     .cas_n(dram_cas_n),
  57     .we_n(dram_we_n),
  58     .dm_tdqs(dram_dm),
  59     .ba(dram_ba),
  60     .addr(dram_a),
  61     .dq(dram_dq),
  62     .dqs(dram_dqs),
  63     .dqs_n(dram_dqs_n),
  64     .tdqs_n(dram_tdqs_n),
  65     .odt(dram_odt)
  66   );
  67
  68   assign dram_dqs_n = (dram_dqs != 2'hz) ? ~dram_dqs : 2'hz;
  69
  70   // uart, LEDs, switches
  71   wire uart_tx ;
  72   reg uart_rx = 0;
  73   wire led_0;
  74   wire led_1;
  75   wire led_2;
  76   wire led_3;
  77   wire led_4;
  78   wire led_5;
  79   wire led_6;
  80   wire led_7;
  81   reg switch_0 = 0;
  82   reg switch_1 = 0;
  83   reg switch_2 = 0;
  84   reg switch_3 = 0;
  85   reg switch_4 = 0;
  86   reg switch_5 = 0;
  87   reg switch_6 = 0;
  88   reg switch_7 = 0;
  89
  90   //defparam ram_chip.
  91
  92   top simsoctop (
  93     .ddr3_0__rst__io(dram_rst),
  94     .ddr3_0__dq__io(dram_dq),
  95     .ddr3_0__dqs__p(dram_dqs),
  96     .ddr3_0__clk__p(dram_ck),
  97     .ddr3_0__clk_en__io(dram_cke),
  98     .ddr3_0__cs__io(dram_cs_n),
  99     .ddr3_0__we__io(dram_we_n),
 100     .ddr3_0__ras__io(dram_ras_n),
 101     .ddr3_0__cas__io(dram_cas_n),
 102     .ddr3_0__a__io(dram_a),
 103     .ddr3_0__ba__io(dram_ba),
 104     .ddr3_0__dm__io(dram_dm),
 105     .ddr3_0__odt__io(dram_odt),
 106     .uart_0__rx__io(uart_rx),
 107     .uart_0__tx__io(uart_tx),
 108     .led_0__io(led_0),
 109     .led_1__io(led_1),
 110     .led_2__io(led_2),
 111     .led_3__io(led_3),
 112     .led_4__io(led_4),
 113     .led_5__io(led_5),
 114     .led_6__io(led_6),
 115     .led_7__io(led_7),
 116     .switch_0__io(switch_0),
 117     .switch_1__io(switch_1),
 118     .switch_2__io(switch_2),
 119     .switch_3__io(switch_3),
 120     .switch_4__io(switch_4),
 121     .switch_5__io(switch_5),
 122     .switch_6__io(switch_6),
 123     .switch_7__io(switch_7),
 124     .clk100_0__p(clkin),
 125     .rst_0__io(1'b0)
 126   );
 127
 128   initial
 129     begin
 130       $dumpfile("simsoc.fst");
 131       $dumpvars(0, clkin);
 132       $dumpvars(0, dram_rst);
 133       $dumpvars(0, dram_dq);
 134       $dumpvars(0, dram_dqs);
 135       $dumpvars(0, dram_ck);
 136       $dumpvars(0, dram_cke);
 137       $dumpvars(0, dram_cs_n);
 138       $dumpvars(0, dram_we_n);
 139       $dumpvars(0, dram_ras_n);
 140       $dumpvars(0, dram_cas_n);
 141       $dumpvars(0, dram_a);
 142       $dumpvars(0, dram_ba);
 143       $dumpvars(0, dram_dm);
 144       $dumpvars(0, dram_odt);
 145       $dumpvars(0, uart_tx);
 146       $dumpvars(0, uart_rx);
 147       $dumpvars(0, simsoctop);
 148       $dumpvars(0, ram_chip);
 149     end
 150
 151   initial
 152     begin
 153       // run for a set time period then exit
 154       #120000000;
 155
 156       $finish;
 157     end
 158
 159 endmodule