4 from nmigen
.compat
.sim
import run_simulation
6 from soc
.TLB
.TLB
import TLB
8 from soc
.TestUtil
.test_helper
import assert_op
, assert_eq
10 # self.supermode = Signal(1) # Supervisor Mode
11 # self.super_access = Signal(1) # Supervisor Access
12 # self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
13 # self.xwr = Signal(3) # Execute, Write, Read
14 # self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
15 #self.address_L1 = Signal(range(L1_size))
16 # self.asid = Signal(asid_size) # Address Space IDentifier (ASID)
17 # self.vma = Signal(vma_size) # Virtual Memory Address (VMA)
18 # self.pte_in = Signal(pte_size) # To be saved Page Table Entry (PTE)
20 # self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
21 # self.perm_valid = Signal(1) # Denotes if the permissions are correct
22 # self.pte_out = Signal(pte_size) # PTE that was mapped to by the VMA
27 # Checks the data state of the CAM entry
29 # dut: The CamEntry being tested
30 # d (Data): The expected data
31 # op (Operation): (0 => ==), (1 => !=)
34 def check_hit(dut
, d
):
36 #assert_eq("hit", hit_d, d)
39 def tst_command(dut
, cmd
, xwr
, cycles
):
40 yield dut
.command
.eq(cmd
)
42 for i
in range(0, cycles
):
46 def tst_write_L1(dut
, vma
, address_L1
, asid
, pte_in
):
47 yield dut
.address_L1
.eq(address_L1
)
48 yield dut
.asid
.eq(asid
)
50 yield dut
.pte_in
.eq(pte_in
)
51 yield from tst_command(dut
, COMMAND_WRITE_L1
, 7, 2)
54 def tst_search(dut
, vma
, found
):
56 yield from tst_command(dut
, COMMAND_READ
, 7, 1)
57 yield from check_hit(dut
, found
)
61 yield dut
.supermode
.eq(0)
62 yield dut
.super_access
.eq(0)
64 yield dut
.address_L1
.eq(0)
67 yield dut
.pte_in
.eq(0)
72 yield dut
.mode
.eq(0xF) # enable TLB
74 yield from tst_write_L1(dut
, 0xFEEDFACE, 0, 0xFFFF, 0xF0F0)
75 yield from tst_search(dut
, 0xFEEDFACE, 1)
76 yield from tst_search(dut
, 0xFACEFEED, 0)
80 dut
= TLB(15, 36, 64, 8)
81 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_tlb.vcd")
82 print("TLB Unit Test Success")
85 if __name__
== "__main__":