src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9
  10
  11 def wait_busy(port, no=False,debug=None):
  12     cnt = 0
  13     while True:
  14         busy = yield port.busy_o
  15         print("busy", no, busy, cnt, debug)
  16         if bool(busy) == no:
  17             break
  18         yield
  19         cnt += 1
  20
  21
  22
  23 def wait_addr(port,debug=None):
  24     cnt = 0
  25     while True:
  26         addr_ok = yield port.addr_ok_o
  27         print("addrok", addr_ok,cnt,debug)
  28         if addr_ok:
  29             break
  30         yield
  31         cnt += 1
  32
  33
  34 def wait_ldok(port):
  35     cnt = 0
  36     while True:
  37         ldok = yield port.ld.ok
  38         exc_happened = yield port.exc_o.happened
  39         print("ldok", ldok, "exception", exc_happened, "count", cnt)
  40         cnt += 1
  41         if ldok or exc_happened:
  42             break
  43         yield
  44
  45
  46 def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
  47
  48     # have to wait until not busy
  49     yield from wait_busy(port1, no=False)    # wait until not busy
  50
  51     # set up a ST on the port.  address first:
  52     yield port1.is_dcbz_i.eq(is_dcbz)  # reset dcbz too
  53     yield port1.is_st_i.eq(1)  # indicate ST
  54     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  55     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  56
  57     yield port1.addr.data.eq(addr)  # set address
  58     yield port1.addr.ok.eq(1)  # set ok
  59     yield Settle()
  60     yield from wait_addr(port1)             # wait until addr ok
  61     # yield # not needed, just for checking
  62     # yield # not needed, just for checking
  63     # assert "ST" for one cycle (required by the API)
  64     yield port1.st.data.eq(data)
  65     yield port1.st.ok.eq(1)
  66     yield
  67     yield port1.st.ok.eq(0)
  68     yield from wait_busy(port1, True)    # wait while busy
  69
  70     # can go straight to reset.
  71     yield port1.is_st_i.eq(0)  # end
  72     yield port1.addr.ok.eq(0)  # set !ok
  73     yield port1.is_dcbz_i.eq(0)  # reset dcbz too
  74
  75
  76 # copy of pi_st removed
  77
  78 def pi_ld(port1, addr, datalen, msr_pr=0):
  79
  80     # have to wait until not busy
  81     yield from wait_busy(port1, no=False)    # wait until not busy
  82
  83     # set up a LD on the port.  address first:
  84     yield port1.is_ld_i.eq(1)  # indicate LD
  85     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
  86     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  87
  88     yield port1.addr.data.eq(addr)  # set address
  89     yield port1.addr.ok.eq(1)  # set ok
  90     yield Settle()
  91     yield from wait_addr(port1)             # wait until addr ok
  92     yield
  93     yield from wait_ldok(port1)             # wait until ld ok
  94     data = yield port1.ld.data
  95     exc_happened = yield port1.exc_o.happened
  96
  97     # cleanup
  98     yield port1.is_ld_i.eq(0)  # end
  99     yield port1.addr.ok.eq(0)  # set !ok
 100     if exc_happened:
 101         return 0
 102
 103     yield from wait_busy(port1, no=False)    # wait while not busy
 104
 105     return data
 106
 107
 108 def pi_ldst(arg, dut, msr_pr=0):
 109
 110     # do two half-word stores at consecutive addresses, then two loads
 111     addr1 = 0x04
 112     addr2 = addr1 + 0x2
 113     data = 0xbeef
 114     data2 = 0xf00f
 115     #data = 0x4
 116     yield from pi_st(dut, addr1, data, 2, msr_pr)
 117     yield from pi_st(dut, addr2, data2, 2, msr_pr)
 118     result = yield from pi_ld(dut, addr1, 2, msr_pr)
 119     result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 120     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 121     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 122
 123     # now load both in a 32-bit load to make sure they're really consecutive
 124     data3 = data | (data2 << 16)
 125     result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 126     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 127
 128
 129 def tst_config_pi(testcls, ifacetype):
 130     """set up a configureable memory test of type ifacetype
 131     """
 132     dut = Module()
 133     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 134                          imem_ifacetype='',
 135                          addr_wid=48,
 136                          mask_wid=8,
 137                          reg_wid=64)
 138     cmpi = ConfigMemoryPortInterface(pspec)
 139     dut.submodules.pi = cmpi.pi
 140     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 141         dut.submodules.lsmem = cmpi.lsmem.lsi
 142     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 143     with open("test_pi_%s.il" % ifacetype, "w") as f:
 144         f.write(vl)
 145
 146     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 147                    vcd_name='test_pi_%s.vcd' % ifacetype)
 148
 149
 150 class TestPIMem(unittest.TestCase):
 151
 152     def test_pi_mem(self):
 153         tst_config_pi(self, 'testpi')
 154
 155     def test_pi2ls(self):
 156         tst_config_pi(self, 'testmem')
 157
 158     def test_pi2ls_bare_wb(self):
 159         tst_config_pi(self, 'test_bare_wb')
 160
 161
 162 if __name__ == '__main__':
 163     unittest.main()