src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9
  10
  11 def wait_busy(port, no=False,debug=None):
  12     cnt = 0
  13     while True:
  14         busy = yield port.busy_o
  15         print("busy", no, busy, cnt, debug)
  16         if bool(busy) == no:
  17             break
  18         yield
  19         cnt += 1
  20
  21
  22
  23 def wait_addr(port,debug=None):
  24     cnt = 0
  25     while True:
  26         addr_ok = yield port.addr_ok_o
  27         print("addrok", addr_ok,cnt,debug)
  28         if addr_ok:
  29             break
  30         yield
  31         cnt += 1
  32
  33
  34 def wait_ldok(port):
  35     cnt = 0
  36     while True:
  37         ldok = yield port.ld.ok
  38         exc_happened = yield port.exc_o.happened
  39         print("ldok", ldok, "exception", exc_happened, "count", cnt)
  40         cnt += 1
  41         if ldok or exc_happened:
  42             break
  43         yield
  44
  45
  46 def pi_st(port1, addr, data, datalen, msr_pr=0):
  47
  48     # have to wait until not busy
  49     yield from wait_busy(port1, no=False)    # wait until not busy
  50
  51     # set up a ST on the port.  address first:
  52     yield port1.is_st_i.eq(1)  # indicate ST
  53     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  54     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  55
  56     yield port1.addr.data.eq(addr)  # set address
  57     yield port1.addr.ok.eq(1)  # set ok
  58     yield Settle()
  59     yield from wait_addr(port1)             # wait until addr ok
  60     # yield # not needed, just for checking
  61     # yield # not needed, just for checking
  62     # assert "ST" for one cycle (required by the API)
  63     yield port1.st.data.eq(data)
  64     yield port1.st.ok.eq(1)
  65     yield
  66     yield port1.st.ok.eq(0)
  67     yield from wait_busy(port1, True)    # wait while busy
  68
  69 # copy of pi_st
  70 def pi_dcbz(port1, addr, data, datalen, msr_pr=0):
  71
  72     # have to wait until not busy
  73     yield from wait_busy(port1, no=False,debug="busy")    # wait until not busy
  74
  75     # set up a ST on the port.  address first:
  76     yield port1.is_st_i.eq(1)  # indicate ST
  77     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  78     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  79
  80     yield port1.is_dcbz.eq(1) # set dcbz
  81
  82     yield port1.addr.data.eq(addr)  # set address
  83     yield port1.addr.ok.eq(1)  # set ok
  84     yield Settle()
  85     yield from wait_addr(port1,debug="addr")             # wait until addr ok
  86     # yield # not needed, just for checking
  87     # yield # not needed, just for checking
  88     # assert "ST" for one cycle (required by the API)
  89     yield port1.st.data.eq(data)
  90     yield port1.st.ok.eq(1)
  91     yield
  92     yield port1.st.ok.eq(0)
  93     yield from wait_busy(port1, no=True, debug="not_busy")    # wait while busy
  94
  95     # can go straight to reset.
  96     yield port1.is_st_i.eq(0)  # end
  97     yield port1.addr.ok.eq(0)  # set !ok
  98     yield port1.is_dcbz.eq(0)  # reset dcbz too
  99
 100
 101 def pi_ld(port1, addr, datalen, msr_pr=0):
 102
 103     # have to wait until not busy
 104     yield from wait_busy(port1, no=False)    # wait until not busy
 105
 106     # set up a LD on the port.  address first:
 107     yield port1.is_ld_i.eq(1)  # indicate LD
 108     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
 109     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
 110
 111     yield port1.addr.data.eq(addr)  # set address
 112     yield port1.addr.ok.eq(1)  # set ok
 113     yield Settle()
 114     yield from wait_addr(port1)             # wait until addr ok
 115     yield
 116     yield from wait_ldok(port1)             # wait until ld ok
 117     data = yield port1.ld.data
 118     exc_happened = yield port1.exc_o.happened
 119
 120     # cleanup
 121     yield port1.is_ld_i.eq(0)  # end
 122     yield port1.addr.ok.eq(0)  # set !ok
 123     if exc_happened:
 124         return 0
 125
 126     yield from wait_busy(port1, no=False)    # wait while not busy
 127
 128     return data
 129
 130
 131 def pi_ldst(arg, dut, msr_pr=0):
 132
 133     # do two half-word stores at consecutive addresses, then two loads
 134     addr1 = 0x04
 135     addr2 = addr1 + 0x2
 136     data = 0xbeef
 137     data2 = 0xf00f
 138     #data = 0x4
 139     yield from pi_st(dut, addr1, data, 2, msr_pr)
 140     yield from pi_st(dut, addr2, data2, 2, msr_pr)
 141     result = yield from pi_ld(dut, addr1, 2, msr_pr)
 142     result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 143     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 144     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 145
 146     # now load both in a 32-bit load to make sure they're really consecutive
 147     data3 = data | (data2 << 16)
 148     result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 149     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 150
 151
 152 def tst_config_pi(testcls, ifacetype):
 153     """set up a configureable memory test of type ifacetype
 154     """
 155     dut = Module()
 156     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 157                          imem_ifacetype='',
 158                          addr_wid=48,
 159                          mask_wid=8,
 160                          reg_wid=64)
 161     cmpi = ConfigMemoryPortInterface(pspec)
 162     dut.submodules.pi = cmpi.pi
 163     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 164         dut.submodules.lsmem = cmpi.lsmem.lsi
 165     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 166     with open("test_pi_%s.il" % ifacetype, "w") as f:
 167         f.write(vl)
 168
 169     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 170                    vcd_name='test_pi_%s.vcd' % ifacetype)
 171
 172
 173 class TestPIMem(unittest.TestCase):
 174
 175     def test_pi_mem(self):
 176         tst_config_pi(self, 'testpi')
 177
 178     def test_pi2ls(self):
 179         tst_config_pi(self, 'testmem')
 180
 181     def test_pi2ls_bare_wb(self):
 182         tst_config_pi(self, 'test_bare_wb')
 183
 184
 185 if __name__ == '__main__':
 186     unittest.main()