src/soc/config/test/test_pi2ls.py

   1 from nmigen import Signal, Module, Record
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.compat.sim import run_simulation, Settle
   4 from nmutil.formaltest import FHDLTestCase
   5 from nmigen.cli import rtlil
   6 import unittest
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.config.loadstore import ConfigMemoryPortInterface
   9
  10
  11 def wait_busy(port, no=False):
  12     while True:
  13         busy = yield port.busy_o
  14         print("busy", no, busy)
  15         if bool(busy) == no:
  16             break
  17         yield
  18
  19
  20 def wait_addr(port):
  21     while True:
  22         addr_ok = yield port.addr_ok_o
  23         print("addrok", addr_ok)
  24         if addr_ok:
  25             break
  26         yield
  27
  28
  29 def wait_ldok(port):
  30     cnt = 0
  31     while True:
  32         ldok = yield port.ld.ok
  33         exc_happened = yield port.exc_o.happened
  34         print("ldok", ldok, "exception", exc_happened, "count", cnt)
  35         cnt += 1
  36         if ldok or exc_happened:
  37             break
  38         yield
  39
  40
  41 def pi_st(port1, addr, data, datalen, msr_pr=0):
  42
  43     # have to wait until not busy
  44     yield from wait_busy(port1, no=False)    # wait until not busy
  45
  46     # set up a ST on the port.  address first:
  47     yield port1.is_st_i.eq(1)  # indicate ST
  48     yield port1.data_len.eq(datalen)  # ST length (1/2/4/8)
  49     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  50
  51     yield port1.addr.data.eq(addr)  # set address
  52     yield port1.addr.ok.eq(1)  # set ok
  53     yield Settle()
  54     yield from wait_addr(port1)             # wait until addr ok
  55     # yield # not needed, just for checking
  56     # yield # not needed, just for checking
  57     # assert "ST" for one cycle (required by the API)
  58     yield port1.st.data.eq(data)
  59     yield port1.st.ok.eq(1)
  60     yield
  61     yield port1.st.ok.eq(0)
  62     yield from wait_busy(port1, True)    # wait while busy
  63
  64     # can go straight to reset.
  65     yield port1.is_st_i.eq(0)  # end
  66     yield port1.addr.ok.eq(0)  # set !ok
  67
  68
  69 def pi_ld(port1, addr, datalen, msr_pr=0):
  70
  71     # have to wait until not busy
  72     yield from wait_busy(port1, no=False)    # wait until not busy
  73
  74     # set up a LD on the port.  address first:
  75     yield port1.is_ld_i.eq(1)  # indicate LD
  76     yield port1.data_len.eq(datalen)  # LD length (1/2/4/8)
  77     yield port1.msr_pr.eq(msr_pr)  # MSR PR bit (1==>virt, 0==>real)
  78
  79     yield port1.addr.data.eq(addr)  # set address
  80     yield port1.addr.ok.eq(1)  # set ok
  81     yield Settle()
  82     yield from wait_addr(port1)             # wait until addr ok
  83     yield
  84     yield from wait_ldok(port1)             # wait until ld ok
  85     data = yield port1.ld.data
  86     exc_happened = yield port1.exc_o.happened
  87
  88     # cleanup
  89     yield port1.is_ld_i.eq(0)  # end
  90     yield port1.addr.ok.eq(0)  # set !ok
  91     if exc_happened:
  92         return 0
  93
  94     yield from wait_busy(port1, no=False)    # wait while not busy
  95
  96     return data
  97
  98
  99 def pi_ldst(arg, dut, msr_pr=0):
 100
 101     # do two half-word stores at consecutive addresses, then two loads
 102     addr1 = 0x04
 103     addr2 = addr1 + 0x2
 104     data = 0xbeef
 105     data2 = 0xf00f
 106     #data = 0x4
 107     yield from pi_st(dut, addr1, data, 2, msr_pr)
 108     yield from pi_st(dut, addr2, data2, 2, msr_pr)
 109     result = yield from pi_ld(dut, addr1, 2, msr_pr)
 110     result2 = yield from pi_ld(dut, addr2, 2, msr_pr)
 111     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 112     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 113
 114     # now load both in a 32-bit load to make sure they're really consecutive
 115     data3 = data | (data2 << 16)
 116     result3 = yield from pi_ld(dut, addr1, 4, msr_pr)
 117     arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3))
 118
 119
 120 def tst_config_pi(testcls, ifacetype):
 121     """set up a configureable memory test of type ifacetype
 122     """
 123     dut = Module()
 124     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
 125                          imem_ifacetype='',
 126                          addr_wid=48,
 127                          mask_wid=8,
 128                          reg_wid=64)
 129     cmpi = ConfigMemoryPortInterface(pspec)
 130     dut.submodules.pi = cmpi.pi
 131     if hasattr(cmpi, 'lsmem'):  # hmmm not happy about this
 132         dut.submodules.lsmem = cmpi.lsmem.lsi
 133     vl = rtlil.convert(dut, ports=[])  # dut.ports())
 134     with open("test_pi_%s.il" % ifacetype, "w") as f:
 135         f.write(vl)
 136
 137     run_simulation(dut, {"sync": pi_ldst(testcls, cmpi.pi.pi)},
 138                    vcd_name='test_pi_%s.vcd' % ifacetype)
 139
 140
 141 class TestPIMem(unittest.TestCase):
 142
 143     def test_pi_mem(self):
 144         tst_config_pi(self, 'testpi')
 145
 146     def test_pi2ls(self):
 147         tst_config_pi(self, 'testmem')
 148
 149     def test_pi2ls_bare_wb(self):
 150         tst_config_pi(self, 'test_bare_wb')
 151
 152
 153 if __name__ == '__main__':
 154     unittest.main()