src/soc/experiment/compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Cat, Const
  14 from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT)
  15
  16 from nmutil.latch import SRLatch, latchregister
  17 from nmutil.iocontrol import RecordObject
  18 from nmutil.util import rising_edge
  19
  20 from soc.fu.regspec import RegSpec, RegSpecALUAPI
  21
  22
  23 def find_ok(fields):
  24     """find_ok helper function - finds field ending in "_ok"
  25     """
  26     for field_name in fields:
  27         if field_name.endswith("_ok"):
  28             return field_name
  29     return None
  30
  31
  32 def go_record(n, name):
  33     r = Record([('go_i', n, DIR_FANIN),
  34                 ('rel_o', n, DIR_FANOUT)], name=name)
  35     r.go_i.reset_less = True
  36     r.rel_o.reset_less = True
  37     return r
  38
  39
  40 # see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  41
  42 class CompUnitRecord(RegSpec, RecordObject):
  43     """CompUnitRecord
  44
  45     base class for Computation Units, to provide a uniform API
  46     and allow "record.connect" etc. to be used, particularly when
  47     it comes to connecting multiple Computation Units up as a block
  48     (very laborious)
  49
  50     LDSTCompUnitRecord should derive from this class and add the
  51     additional signals it requires
  52
  53     :subkls:      the class (not an instance) needed to construct the opcode
  54     :rwid:        either an integer (specifies width of all regs) or a "regspec"
  55
  56     see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  57     """
  58
  59     def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
  60         RegSpec.__init__(self, rwid, n_src, n_dst)
  61         print ("name", name)
  62         RecordObject.__init__(self)
  63         self._subkls = subkls
  64         n_src, n_dst = self._n_src, self._n_dst
  65
  66         # create source operands
  67         src = []
  68         for i in range(n_src):
  69             j = i + 1  # name numbering to match src1/src2
  70             sname = "src%d_i" % j
  71             rw = self._get_srcwid(i)
  72             sreg = Signal(rw, name=sname, reset_less=True)
  73             setattr(self, sname, sreg)
  74             src.append(sreg)
  75         self._src_i = src
  76
  77         # create dest operands
  78         dst = []
  79         for i in range(n_dst):
  80             j = i + 1  # name numbering to match dest1/2...
  81             dname = "dest%d_o" % j
  82             rw = self._get_dstwid(i)
  83             # dreg = Data(rw, name=name) XXX ??? output needs to be a Data type?
  84             dreg = Signal(rw, name=dname, reset_less=True)
  85             setattr(self, dname, dreg)
  86             dst.append(dreg)
  87         self._dest = dst
  88
  89         # operation / data input
  90         self.oper_i = subkls(name="oper_i_%s" % name)  # operand
  91
  92         # create read/write and other scoreboard signalling
  93         self.rd = go_record(n_src, name="cu_rd")  # read in, req out
  94         self.wr = go_record(n_dst, name="cu_wr")  # write in, req out
  95         # read / write mask
  96         self.rdmaskn = Signal(n_src, name="cu_rdmaskn_i", reset_less=True)
  97         self.wrmask = Signal(n_dst, name="cu_wrmask_o", reset_less=True)
  98
  99         # fn issue in
 100         self.issue_i = Signal(name="cu_issue_i", reset_less=True)
 101         # shadow function, defaults to ON
 102         self.shadown_i = Signal(name="cu_shadown_i", reset=1)
 103         # go die (reset)
 104         self.go_die_i = Signal(name="cu_go_die_i")
 105
 106         # output (busy/done)
 107         self.busy_o = Signal(name="cu_busy_o", reset_less=True)  # fn busy out
 108         self.done_o = Signal(name="cu_done_o", reset_less=True)
 109         self.alu_done_o = Signal(name="cu_alu_done_o", reset_less=True)
 110
 111
 112 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 113     def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None):
 114         """MultiCompUnit
 115
 116         * :rwid:        width of register latches (TODO: allocate per regspec)
 117         * :alu:         ALU (pipeline, FSM) - must conform to nmutil Pipe API
 118         * :opsubsetkls: subset of Decode2ExecuteType
 119         * :n_src:       number of src operands
 120         * :n_dst:       number of destination operands
 121         """
 122         RegSpecALUAPI.__init__(self, rwid, alu)
 123         self.alu_name = name or "alu"
 124         self.opsubsetkls = opsubsetkls
 125         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst,
 126                                       name=name)
 127         n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst
 128         print("n_src %d n_dst %d" % (self.n_src, self.n_dst))
 129
 130         # convenience names for src operands
 131         for i in range(n_src):
 132             j = i + 1  # name numbering to match src1/src2
 133             name = "src%d_i" % j
 134             setattr(self, name, getattr(cu, name))
 135
 136         # convenience names for dest operands
 137         for i in range(n_dst):
 138             j = i + 1  # name numbering to match dest1/2...
 139             name = "dest%d_o" % j
 140             setattr(self, name, getattr(cu, name))
 141
 142         # more convenience names
 143         self.rd = cu.rd
 144         self.wr = cu.wr
 145         self.rdmaskn = cu.rdmaskn
 146         self.wrmask = cu.wrmask
 147         self.alu_done_o = cu.alu_done_o
 148         self.go_rd_i = self.rd.go_i  # temporary naming
 149         self.go_wr_i = self.wr.go_i  # temporary naming
 150         self.rd_rel_o = self.rd.rel_o  # temporary naming
 151         self.req_rel_o = self.wr.rel_o  # temporary naming
 152         self.issue_i = cu.issue_i
 153         self.shadown_i = cu.shadown_i
 154         self.go_die_i = cu.go_die_i
 155
 156         # operation / data input
 157         self.oper_i = cu.oper_i
 158         self.src_i = cu._src_i
 159
 160         self.busy_o = cu.busy_o
 161         self.dest = cu._dest
 162         self.o_data = self.dest[0]  # Dest out
 163         self.done_o = cu.done_o
 164
 165     def _mux_op(self, m, sl, op_is_imm, imm, i):
 166         # select imm if opcode says so. however also change the latch
 167         # to trigger *from* the opcode latch instead.
 168         src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
 169         src_sel = Signal(reset_less=True)
 170         m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, sl[i][2]))
 171         m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
 172         # overwrite 1st src-latch with immediate-muxed stuff
 173         sl[i][0] = src_or_imm
 174         sl[i][2] = src_sel
 175         sl[i][3] = ~op_is_imm  # change rd.rel[i] gate condition
 176
 177     def elaborate(self, platform):
 178         m = Module()
 179         # add the ALU to the MultiCompUnit only if it is a "real" ALU
 180         # see AllFunctionUnits as to why: a FunctionUnitBaseMulti
 181         # only has one "real" ALU but multiple pseudo front-ends,
 182         # aka "ReservationStations" (ALUProxy "fronts")
 183         if isinstance(self.alu, Elaboratable):
 184             setattr(m.submodules, self.alu_name, self.alu)
 185         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 186         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 187         m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
 188         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 189         m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
 190         self.opc_l, self.src_l = opc_l, src_l
 191
 192         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
 193         # so combine it with go_rd_i.  if all bits are set we're good
 194         all_rd = Signal(reset_less=True)
 195         m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
 196                               (((~self.rd.rel_o) | self.rd.go_i).all()))
 197
 198         # generate read-done pulse
 199         all_rd_pulse = Signal(reset_less=True)
 200         m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd))
 201
 202         # create rising pulse from alu valid condition.
 203         alu_done = self.cu.alu_done_o
 204         alu_pulse = Signal(reset_less=True)
 205         alu_pulsem = Signal(self.n_dst, reset_less=True)
 206         m.d.comb += alu_done.eq(self.alu.n.o_valid)
 207         m.d.comb += alu_pulse.eq(rising_edge(m, alu_done))
 208         m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
 209
 210         # sigh bug where req_l gets both set and reset raised at same time
 211         prev_wr_go = Signal(self.n_dst)
 212         brd = Repl(self.busy_o, self.n_dst)
 213         m.d.sync += prev_wr_go.eq(self.wr.go_i & brd)
 214
 215         # write_requests all done
 216         # req_done works because any one of the last of the writes
 217         # is enough, when combined with when read-phase is done (rst_l.q)
 218         wr_any = Signal(reset_less=True)
 219         req_done = Signal(reset_less=True)
 220         m.d.comb += self.done_o.eq(self.busy_o & ~(self.wr.rel_o).bool())
 221         m.d.comb += wr_any.eq(self.wr.go_i.bool() | prev_wr_go.bool())
 222         m.d.comb += req_done.eq(wr_any & ~self.alu.n.i_ready & (req_l.q == 0))
 223         # argh, complicated hack: if there are no regs to write,
 224         # instead of waiting for regs that are never going to happen,
 225         # we indicate "done" when the ALU is "done"
 226         with m.If((self.wrmask == 0) &
 227                   self.alu.n.i_ready & self.alu.n.o_valid & self.busy_o):
 228             m.d.comb += req_done.eq(1)
 229
 230         # shadow/go_die
 231         reset = Signal(reset_less=True)
 232         rst_r = Signal(reset_less=True)  # reset latch off
 233         reset_w = Signal(self.n_dst, reset_less=True)
 234         reset_r = Signal(self.n_src, reset_less=True)
 235         m.d.comb += reset.eq(req_done | self.go_die_i)
 236         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
 237         m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
 238         m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
 239
 240         # read-done,wr-proceed latch
 241         m.d.sync += rok_l.s.eq(self.issue_i)  # set up when issue starts
 242         m.d.sync += rok_l.r.eq(self.alu.n.o_valid & self.busy_o)  # ALU done
 243
 244         # wr-done, back-to-start latch
 245         m.d.sync += rst_l.s.eq(all_rd)     # set when read-phase is fully done
 246         m.d.sync += rst_l.r.eq(rst_r)        # *off* on issue
 247
 248         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
 249         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
 250         m.d.sync += opc_l.r.eq(req_done)  # reset on ALU
 251
 252         # src operand latch (not using go_wr_i)
 253         m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~self.rdmaskn)
 254         m.d.sync += src_l.r.eq(reset_r)
 255
 256         # dest operand latch (not using issue_i)
 257         m.d.sync += req_l.s.eq(alu_pulsem & self.wrmask)
 258         m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
 259
 260         # pass operation to the ALU (sync: plenty time to wait for src reads)
 261         op = self.get_op()
 262         with m.If(self.issue_i):
 263             m.d.sync += op.eq(self.oper_i)
 264
 265         # and for each output from the ALU: capture when ALU output is valid
 266         drl = []
 267         wrok = []
 268         for i in range(self.n_dst):
 269             name = "data_r%d" % i
 270             lro = self.get_out(i)
 271             ok = Const(1, 1)
 272             data_r_ok = Const(1, 1)
 273             if isinstance(lro, Record):
 274                 data_r = Record.like(lro, name=name)
 275                 print("wr fields", i, lro, data_r.fields)
 276                 # bye-bye abstract interface design..
 277                 fname = find_ok(data_r.fields)
 278                 if fname:
 279                     ok = getattr(lro, fname)
 280                     data_r_ok = getattr(data_r, fname)
 281                 # write-ok based on incoming output *and* whether the latched
 282                 # data was ok.
 283                 # XXX fails - wrok.append((ok|data_r_ok) & self.busy_o)
 284                 wrok.append(ok & self.busy_o)
 285             else:
 286                 # really should retire this but it's part of unit tests
 287                 data_r = Signal.like(lro, name=name, reset_less=True)
 288                 wrok.append(ok & self.busy_o)
 289             with m.If(alu_pulse):
 290                 m.d.sync += data_r.eq(lro)
 291             with m.If(self.issue_i):
 292                 m.d.sync += data_r.eq(0)
 293             drl.append(data_r)
 294
 295         # ok, above we collated anything with an "ok" on the output side
 296         # now actually use those to create a write-mask.  this basically
 297         # is now the Function Unit API tells the Comp Unit "do not request
 298         # a regfile port because this particular output is not valid"
 299         m.d.comb += self.wrmask.eq(Cat(*wrok))
 300
 301         # create list of src/alu-src/src-latch.  override 1st and 2nd one below.
 302         # in the case, for ALU and Logical pipelines, we assume RB is the
 303         # 2nd operand in the input "regspec".  see for example
 304         # soc.fu.alu.pipe_data.ALUInputData
 305         sl = []
 306         print("src_i", self.src_i)
 307         for i in range(self.n_src):
 308             sl.append([self.src_i[i], self.get_in(i), src_l.q[i], Const(1, 1)])
 309
 310         # if the operand subset has "zero_a" we implicitly assume that means
 311         # src_i[0] is an INT reg type where zero can be multiplexed in, instead.
 312         # see https://bugs.libre-soc.org/show_bug.cgi?id=336
 313         if hasattr(op, "zero_a"):
 314             # select zero imm if opcode says so.  however also change the latch
 315             # to trigger *from* the opcode latch instead.
 316             self._mux_op(m, sl, op.zero_a, 0, 0)
 317
 318         # if the operand subset has "imm_data" we implicitly assume that means
 319         # "this is an INT ALU/Logical FU jobbie, RB is muxed with the immediate"
 320         if hasattr(op, "imm_data"):
 321             # select immediate if opcode says so. however also change the latch
 322             # to trigger *from* the opcode latch instead.
 323             op_is_imm = op.imm_data.ok
 324             imm = op.imm_data.data
 325             self._mux_op(m, sl, op_is_imm, imm, 1)
 326
 327         # create a latch/register for src1/src2 (even if it is a copy of imm)
 328         for i in range(self.n_src):
 329             src, alusrc, latch, _ = sl[i]
 330             reg = latchregister(m, src, alusrc, latch, name="src_r%d" % i)
 331             # rdmask stops src latches from being set.  clear all if not busy
 332             with m.If(~self.busy_o):
 333                 m.d.sync += reg.eq(0)
 334
 335         # -----
 336         # ALU connection / interaction
 337         # -----
 338
 339         # on a go_read, tell the ALU we're accepting data.
 340         m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
 341         m.d.comb += self.alu.p.i_valid.eq(alui_l.q)
 342         m.d.sync += alui_l.r.eq(self.alu.p.o_ready & alui_l.q)
 343         m.d.comb += alui_l.s.eq(all_rd_pulse)
 344
 345         # ALU output "ready" side.  alu "ready" indication stays hi until
 346         # ALU says "valid".
 347         m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
 348         m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
 349         m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
 350         m.d.comb += alu_l.s.eq(all_rd_pulse)
 351
 352         # -----
 353         # outputs
 354         # -----
 355
 356         slg = Cat(*map(lambda x: x[3], sl))  # get req gate conditions
 357         # all request signals gated by busy_o.  prevents picker problems
 358         m.d.comb += self.busy_o.eq(opc_l.q)  # busy out
 359
 360         # read-release gated by busy (and read-mask)
 361         bro = Repl(self.busy_o, self.n_src)
 362         m.d.comb += self.rd.rel_o.eq(src_l.q & bro & slg)
 363
 364         # write-release gated by busy and by shadow (and write-mask)
 365         brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
 366         m.d.comb += self.wr.rel_o.eq(req_l.q & brd)
 367
 368         # output the data from the latch on go_write
 369         for i in range(self.n_dst):
 370             with m.If(self.wr.go_i[i] & self.busy_o):
 371                 m.d.comb += self.dest[i].eq(drl[i])
 372
 373         return m
 374
 375     def get_fu_out(self, i):
 376         return self.dest[i]
 377
 378     def __iter__(self):
 379         yield self.rd.go_i
 380         yield self.wr.go_i
 381         yield self.issue_i
 382         yield self.shadown_i
 383         yield self.go_die_i
 384         yield from self.oper_i.ports()
 385         yield self.src1_i
 386         yield self.src2_i
 387         yield self.busy_o
 388         yield self.rd.rel_o
 389         yield self.wr.rel_o
 390         yield self.o_data
 391
 392     def ports(self):
 393         return list(self)