3 based on Anton Blanchard microwatt icache.vhdl
7 TODO (in no specific order):
8 * Add debug interface to inspect cache content
9 * Add snoop/invalidate path
10 * Add multi-hit error detection
11 * Pipelined bus interface (wb or axi)
12 * Maybe add parity? There's a few bits free in each BRAM row on Xilinx
13 * Add optimization: service hits on partially loaded lines
14 * Add optimization: (maybe) interrupt reload on fluch/redirect
15 * Check if playing with the geometry of the cache tags allow for more
16 efficient use of distributed RAM and less logic/muxes. Currently we
17 write TAG_BITS width which may not match full ram blocks and might
18 cause muxes to be inferred for "partial writes".
19 * Check if making the read size of PLRU a ROM helps utilization
22 from enum
import Enum
, unique
23 from nmigen
import (Module
, Signal
, Elaboratable
, Cat
, Array
, Const
, Repl
)
24 from nmigen
.cli
import main
, rtlil
25 from nmutil
.iocontrol
import RecordObject
26 from nmigen
.utils
import log2_int
27 from nmutil
.util
import Display
29 #from nmutil.plru import PLRU
30 from soc
.experiment
.cache_ram
import CacheRam
31 from soc
.experiment
.plru
import PLRU
33 from soc
.experiment
.mem_types
import (Fetch1ToICacheType
,
37 from soc
.experiment
.wb_types
import (WB_ADDR_BITS
, WB_DATA_BITS
,
38 WB_SEL_BITS
, WBAddrType
, WBDataType
,
39 WBSelType
, WBMasterOut
, WBSlaveOut
,
40 WBMasterOutVector
, WBSlaveOutVector
,
41 WBIOMasterOut
, WBIOSlaveOut
)
44 from nmigen_soc
.wishbone
.sram
import SRAM
45 from nmigen
import Memory
46 from nmutil
.util
import wrap
47 from nmigen
.cli
import main
, rtlil
49 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
51 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
56 # BRAM organisation: We never access more than wishbone_data_bits
57 # at a time so to save resources we make the array only that wide,
58 # and use consecutive indices for to make a cache "line"
60 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
61 ROW_SIZE
= WB_DATA_BITS
// 8
62 # Number of lines in a set
66 # L1 ITLB number of entries (direct mapped)
68 # L1 ITLB log_2(page_size)
70 # Number of real address bits that we store
72 # Non-zero to enable log data collection
75 ROW_SIZE_BITS
= ROW_SIZE
* 8
76 # ROW_PER_LINE is the number of row
77 # (wishbone) transactions in a line
78 ROW_PER_LINE
= LINE_SIZE
// ROW_SIZE
79 # BRAM_ROWS is the number of rows in
80 # BRAM needed to represent the full icache
81 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
82 # INSN_PER_ROW is the number of 32bit
83 # instructions per BRAM row
84 INSN_PER_ROW
= ROW_SIZE_BITS
// 32
86 print("ROW_SIZE", ROW_SIZE
)
87 print("ROW_SIZE_BITS", ROW_SIZE_BITS
)
88 print("ROW_PER_LINE", ROW_PER_LINE
)
89 print("BRAM_ROWS", BRAM_ROWS
)
90 print("INSN_PER_ROW", INSN_PER_ROW
)
92 # Bit fields counts in the address
94 # INSN_BITS is the number of bits to
95 # select an instruction in a row
96 INSN_BITS
= log2_int(INSN_PER_ROW
)
97 # ROW_BITS is the number of bits to
99 ROW_BITS
= log2_int(BRAM_ROWS
)
100 # ROW_LINEBITS is the number of bits to
101 # select a row within a line
102 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
103 # LINE_OFF_BITS is the number of bits for
104 # the offset in a cache line
105 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
106 # ROW_OFF_BITS is the number of bits for
107 # the offset in a row
108 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
109 # INDEX_BITS is the number of bits to
110 # select a cache line
111 INDEX_BITS
= log2_int(NUM_LINES
)
112 # SET_SIZE_BITS is the log base 2 of
114 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
115 # TAG_BITS is the number of bits of
116 # the tag part of the address
117 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
118 # TAG_WIDTH is the width in bits of each way of the tag RAM
119 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
121 # WAY_BITS is the number of bits to
123 WAY_BITS
= log2_int(NUM_WAYS
)
124 TAG_RAM_WIDTH
= TAG_BITS
* NUM_WAYS
127 # constant TLB_BITS : natural := log2(TLB_SIZE);
128 # constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
129 # constant TLB_PTE_BITS : natural := 64;
130 TLB_BITS
= log2_int(TLB_SIZE
)
131 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_BITS
)
135 print("INSN_BITS", INSN_BITS
)
136 print("ROW_BITS", ROW_BITS
)
137 print("ROW_LINE_BITS", ROW_LINE_BITS
)
138 print("LINE_OFF_BITS", LINE_OFF_BITS
)
139 print("ROW_OFF_BITS", ROW_OFF_BITS
)
140 print("INDEX_BITS", INDEX_BITS
)
141 print("SET_SIZE_BITS", SET_SIZE_BITS
)
142 print("TAG_BITS", TAG_BITS
)
143 print("WAY_BITS", WAY_BITS
)
144 print("TAG_RAM_WIDTH", TAG_RAM_WIDTH
)
145 print("TLB_BITS", TLB_BITS
)
146 print("TLB_EA_TAG_BITS", TLB_EA_TAG_BITS
)
147 print("TLB_PTE_BITS", TLB_PTE_BITS
)
152 # architecture rtl of icache is
153 #constant ROW_SIZE_BITS : natural := ROW_SIZE*8;
154 #-- ROW_PER_LINE is the number of row (wishbone
155 #-- transactions) in a line
156 #constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
157 #-- BRAM_ROWS is the number of rows in BRAM
158 #-- needed to represent the full
160 #constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
161 #-- INSN_PER_ROW is the number of 32bit instructions per BRAM row
162 #constant INSN_PER_ROW : natural := ROW_SIZE_BITS / 32;
163 #-- Bit fields counts in the address
165 #-- INSN_BITS is the number of bits to select
166 #-- an instruction in a row
167 #constant INSN_BITS : natural := log2(INSN_PER_ROW);
168 #-- ROW_BITS is the number of bits to select a row
169 #constant ROW_BITS : natural := log2(BRAM_ROWS);
170 #-- ROW_LINEBITS is the number of bits to
171 #-- select a row within a line
172 #constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
173 #-- LINE_OFF_BITS is the number of bits for the offset
175 #constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
176 #-- ROW_OFF_BITS is the number of bits for the offset in a row
177 #constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
178 #-- INDEX_BITS is the number of bits to select a cache line
179 #constant INDEX_BITS : natural := log2(NUM_LINES);
180 #-- SET_SIZE_BITS is the log base 2 of the set size
181 #constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
182 #-- TAG_BITS is the number of bits of the tag part of the address
183 #constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
184 #-- WAY_BITS is the number of bits to select a way
185 #constant WAY_BITS : natural := log2(NUM_WAYS);
187 #-- Example of layout for 32 lines of 64 bytes:
189 #-- .. tag |index| line |
191 #-- .. | | | |00| zero (2)
192 #-- .. | | |-| | INSN_BITS (1)
193 #-- .. | |---| | ROW_LINEBITS (3)
194 #-- .. | |--- - --| LINE_OFF_BITS (6)
195 #-- .. | |- --| ROW_OFF_BITS (3)
196 #-- .. |----- ---| | ROW_BITS (8)
197 #-- .. |-----| | INDEX_BITS (5)
198 #-- .. --------| | TAG_BITS (53)
199 # Example of layout for 32 lines of 64 bytes:
201 # .. tag |index| line |
203 # .. | | | |00| zero (2)
204 # .. | | |-| | INSN_BITS (1)
205 # .. | |---| | ROW_LINEBITS (3)
206 # .. | |--- - --| LINE_OFF_BITS (6)
207 # .. | |- --| ROW_OFF_BITS (3)
208 # .. |----- ---| | ROW_BITS (8)
209 # .. |-----| | INDEX_BITS (5)
210 # .. --------| | TAG_BITS (53)
212 #subtype row_t is integer range 0 to BRAM_ROWS-1;
213 #subtype index_t is integer range 0 to NUM_LINES-1;
214 #subtype way_t is integer range 0 to NUM_WAYS-1;
215 #subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
217 #-- The cache data BRAM organized as described above for each way
218 #subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
220 #-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
221 #-- not handle a clean (commented) definition of the cache tags as a 3d
222 #-- memory. For now, work around it by putting all the tags
223 #subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
224 # type cache_tags_set_t is array(way_t) of cache_tag_t;
225 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
226 #constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
227 #subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
228 #type cache_tags_array_t is array(index_t) of cache_tags_set_t;
230 return Array(Signal(TAG_RAM_WIDTH
, name
="cachetag_%d" %x) \
231 for x
in range(NUM_LINES
))
233 #-- The cache valid bits
234 #subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
235 #type cache_valids_t is array(index_t) of cache_way_valids_t;
236 #type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
237 def CacheValidBitsArray():
238 return Array(Signal(NUM_WAYS
, name
="cachevalid_%d" %x) \
239 for x
in range(NUM_LINES
))
241 def RowPerLineValidArray():
242 return Array(Signal(name
="rows_valid_%d" %x) \
243 for x
in range(ROW_PER_LINE
))
246 #attribute ram_style : string;
247 #attribute ram_style of cache_tags : signal is "distributed";
248 # TODO to be passed to nigmen as ram attributes
249 # attribute ram_style : string;
250 # attribute ram_style of cache_tags : signal is "distributed";
253 #subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
254 #type tlb_valids_t is array(tlb_index_t) of std_ulogic;
255 #subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
256 #type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
257 #subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
258 #type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
259 def TLBValidBitsArray():
260 return Array(Signal(name
="tlbvalid_%d" %x) \
261 for x
in range(TLB_SIZE
))
264 return Array(Signal(TLB_EA_TAG_BITS
, name
="tlbtag_%d" %x) \
265 for x
in range(TLB_SIZE
))
268 return Array(Signal(TLB_PTE_BITS
, name
="tlbptes_%d" %x) \
269 for x
in range(TLB_SIZE
))
272 #-- Cache RAM interface
273 #type cache_ram_out_t is array(way_t) of cache_row_t;
274 # Cache RAM interface
276 return Array(Signal(ROW_SIZE_BITS
, name
="cache_out_%d" %x) \
277 for x
in range(NUM_WAYS
))
279 #-- PLRU output interface
280 #type plru_out_t is array(index_t) of
281 # std_ulogic_vector(WAY_BITS-1 downto 0);
282 # PLRU output interface
284 return Array(Signal(WAY_BITS
, name
="plru_out_%d" %x) \
285 for x
in range(NUM_LINES
))
287 # -- Return the cache line index (tag index) for an address
288 # function get_index(addr: std_ulogic_vector(63 downto 0))
291 # return to_integer(unsigned(
292 # addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)
295 # Return the cache line index (tag index) for an address
297 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
299 # -- Return the cache row index (data memory) for an address
300 # function get_row(addr: std_ulogic_vector(63 downto 0))
303 # return to_integer(unsigned(
304 # addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)
307 # Return the cache row index (data memory) for an address
309 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
311 # -- Return the index of a row within a line
312 # function get_row_of_line(row: row_t) return row_in_line_t is
313 # variable row_v : unsigned(ROW_BITS-1 downto 0);
315 # row_v := to_unsigned(row, ROW_BITS);
316 # return row_v(ROW_LINEBITS-1 downto 0);
318 # Return the index of a row within a line
319 def get_row_of_line(row
):
320 return row
[:ROW_LINE_BITS
]
322 # -- Returns whether this is the last row of a line
323 # function is_last_row_addr(addr: wishbone_addr_type;
324 # last: row_in_line_t
329 # addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)
332 # Returns whether this is the last row of a line
333 def is_last_row_addr(addr
, last
):
334 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
336 # -- Returns whether this is the last row of a line
337 # function is_last_row(row: row_t;
338 # last: row_in_line_t) return boolean is
340 # return get_row_of_line(row) = last;
342 # Returns whether this is the last row of a line
343 def is_last_row(row
, last
):
344 return get_row_of_line(row
) == last
346 # -- Return the next row in the current cache line. We use a dedicated
347 # -- function in order to limit the size of the generated adder to be
348 # -- only the bits within a cache line (3 bits with default settings)
349 # function next_row(row: row_t) return row_t is
350 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
351 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
352 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
354 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
355 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
356 # row_v(ROW_LINEBITS-1 downto 0) :=
357 # std_ulogic_vector(unsigned(row_idx) + 1);
358 # return to_integer(unsigned(row_v));
360 # Return the next row in the current cache line. We use a dedicated
361 # function in order to limit the size of the generated adder to be
362 # only the bits within a cache line (3 bits with default settings)
364 row_v
= row
[0:ROW_LINE_BITS
] + 1
365 return Cat(row_v
[:ROW_LINE_BITS
], row
[ROW_LINE_BITS
:])
366 # -- Read the instruction word for the given address in the
367 # -- current cache row
368 # function read_insn_word(addr: std_ulogic_vector(63 downto 0);
369 # data: cache_row_t) return std_ulogic_vector is
370 # variable word: integer range 0 to INSN_PER_ROW-1;
372 # word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
373 # return data(31+word*32 downto word*32);
375 # Read the instruction word for the given address
376 # in the current cache row
377 def read_insn_word(addr
, data
):
378 word
= addr
[2:INSN_BITS
+2]
379 return data
.word_select(word
, 32)
381 # -- Get the tag value from the address
383 # addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)
385 # return cache_tag_t is
387 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
389 # Get the tag value from the address
391 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
393 # -- Read a tag from a tag memory row
394 # function read_tag(way: way_t; tagset: cache_tags_set_t)
395 # return cache_tag_t is
397 # return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
399 # Read a tag from a tag memory row
400 def read_tag(way
, tagset
):
401 return tagset
.word_select(way
, TAG_BITS
)
403 # -- Write a tag to tag memory row
404 # procedure write_tag(way: in way_t;
405 # tagset: inout cache_tags_set_t; tag: cache_tag_t) is
407 # tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
409 # Write a tag to tag memory row
410 def write_tag(way
, tagset
, tag
):
411 return read_tag(way
, tagset
).eq(tag
)
413 # -- Simple hash for direct-mapped TLB index
414 # function hash_ea(addr: std_ulogic_vector(63 downto 0))
415 # return tlb_index_t is
416 # variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
418 # hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
420 # TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto
421 # TLB_LG_PGSZ + TLB_BITS
424 # TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto
425 # TLB_LG_PGSZ + 2 * TLB_BITS
427 # return to_integer(unsigned(hash));
429 # Simple hash for direct-mapped TLB index
431 hsh
= addr
[TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_BITS
] ^ addr
[
432 TLB_LG_PGSZ
+ TLB_BITS
:TLB_LG_PGSZ
+ 2 * TLB_BITS
434 TLB_LG_PGSZ
+ 2 * TLB_BITS
:TLB_LG_PGSZ
+ 3 * TLB_BITS
440 # XXX put these assert statements in - as python asserts
442 # assert LINE_SIZE mod ROW_SIZE = 0;
443 # assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2"
444 # assert ispow2(NUM_LINES) report "NUM_LINES not power of 2"
445 # assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2"
446 # assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2"
447 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
448 # report "geometry bits don't add up"
449 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
450 # report "geometry bits don't add up"
451 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
452 # report "geometry bits don't add up"
453 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
454 # report "geometry bits don't add up"
456 # sim_debug: if SIM generate
459 # report "ROW_SIZE = " & natural'image(ROW_SIZE);
460 # report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
461 # report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
462 # report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
463 # report "INSN_BITS = " & natural'image(INSN_BITS);
464 # report "ROW_BITS = " & natural'image(ROW_BITS);
465 # report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
466 # report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
467 # report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
468 # report "INDEX_BITS = " & natural'image(INDEX_BITS);
469 # report "TAG_BITS = " & natural'image(TAG_BITS);
470 # report "WAY_BITS = " & natural'image(WAY_BITS);
475 # Cache reload state machine
482 # type reg_internal_t is record
483 # -- Cache hit state (Latches for 1 cycle BRAM access)
485 # hit_nia : std_ulogic_vector(63 downto 0);
486 # hit_smark : std_ulogic;
487 # hit_valid : std_ulogic;
489 # -- Cache miss state (reload state machine)
491 # wb : wishbone_master_out;
493 # store_index : index_t;
495 # store_tag : cache_tag_t;
496 # store_valid : std_ulogic;
497 # end_row_ix : row_in_line_t;
498 # rows_valid : row_per_line_valid_t;
501 # fetch_failed : std_ulogic;
503 class RegInternal(RecordObject
):
506 # Cache hit state (Latches for 1 cycle BRAM access)
507 self
.hit_way
= Signal(NUM_WAYS
)
508 self
.hit_nia
= Signal(64)
509 self
.hit_smark
= Signal()
510 self
.hit_valid
= Signal()
512 # Cache miss state (reload state machine)
513 self
.state
= Signal(State
, reset
=State
.IDLE
)
514 self
.wb
= WBMasterOut("wb")
515 self
.req_adr
= Signal(64)
516 self
.store_way
= Signal(NUM_WAYS
)
517 self
.store_index
= Signal(NUM_LINES
)
518 self
.store_row
= Signal(BRAM_ROWS
)
519 self
.store_tag
= Signal(TAG_BITS
)
520 self
.store_valid
= Signal()
521 self
.end_row_ix
= Signal(ROW_LINE_BITS
)
522 self
.rows_valid
= RowPerLineValidArray()
525 self
.fetch_failed
= Signal()
527 # -- 64 bit direct mapped icache. All instructions are 4B aligned.
531 # SIM : boolean := false;
532 # -- Line size in bytes
533 # LINE_SIZE : positive := 64;
534 # -- BRAM organisation: We never access more
535 # -- than wishbone_data_bits
536 # -- at a time so to save resources we make the
537 # -- array only that wide,
538 # -- and use consecutive indices for to make a cache "line"
540 # -- ROW_SIZE is the width in bytes of the BRAM (based on WB,
542 # ROW_SIZE : positive := wishbone_data_bits / 8;
543 # -- Number of lines in a set
544 # NUM_LINES : positive := 32;
546 # NUM_WAYS : positive := 4;
547 # -- L1 ITLB number of entries (direct mapped)
548 # TLB_SIZE : positive := 64;
549 # -- L1 ITLB log_2(page_size)
550 # TLB_LG_PGSZ : positive := 12;
551 # -- Number of real address bits that we store
552 # REAL_ADDR_BITS : positive := 56;
553 # -- Non-zero to enable log data collection
554 # LOG_LENGTH : natural := 0
557 # clk : in std_ulogic;
558 # rst : in std_ulogic;
560 # i_in : in Fetch1ToIcacheType;
561 # i_out : out IcacheToDecode1Type;
563 # m_in : in MmuToIcacheType;
565 # stall_in : in std_ulogic;
566 # stall_out : out std_ulogic;
567 # flush_in : in std_ulogic;
568 # inval_in : in std_ulogic;
570 # wishbone_out : out wishbone_master_out;
571 # wishbone_in : in wishbone_slave_out;
573 # log_out : out std_ulogic_vector(53 downto 0)
576 # 64 bit direct mapped icache. All instructions are 4B aligned.
577 class ICache(Elaboratable
):
578 """64 bit direct mapped icache. All instructions are 4B aligned."""
580 self
.i_in
= Fetch1ToICacheType(name
="i_in")
581 self
.i_out
= ICacheToDecode1Type(name
="i_out")
583 self
.m_in
= MMUToICacheType(name
="m_in")
585 self
.stall_in
= Signal()
586 self
.stall_out
= Signal()
587 self
.flush_in
= Signal()
588 self
.inval_in
= Signal()
590 self
.wb_out
= WBMasterOut(name
="wb_out")
591 self
.wb_in
= WBSlaveOut(name
="wb_in")
593 self
.log_out
= Signal(54)
596 # -- Generate a cache RAM for each way
597 # rams: for i in 0 to NUM_WAYS-1 generate
598 # signal do_read : std_ulogic;
599 # signal do_write : std_ulogic;
600 # signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
601 # signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
602 # signal dout : cache_row_t;
603 # signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
605 # way: entity work.cache_ram
607 # ROW_BITS => ROW_BITS,
608 # WIDTH => ROW_SIZE_BITS
613 # rd_addr => rd_addr,
616 # wr_addr => wr_addr,
617 # wr_data => wishbone_in.dat
621 # do_read <= not (stall_in or use_previous);
623 # if wishbone_in.ack = '1' and replace_way = i then
626 # cache_out(i) <= dout;
628 # std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
630 # std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
631 # for i in 0 to ROW_SIZE-1 loop
632 # wr_sel(i) <= do_write;
636 def rams(self
, m
, r
, cache_out_row
, use_previous
, replace_way
, req_row
):
639 wb_in
, stall_in
= self
.wb_in
, self
.stall_in
642 for i
in range(NUM_WAYS
):
643 do_read
= Signal(name
="do_rd_%d" % i
)
644 do_write
= Signal(name
="do_wr_%d" % i
)
645 rd_addr
= Signal(ROW_BITS
)
646 wr_addr
= Signal(ROW_BITS
)
647 d_out
= Signal(ROW_SIZE_BITS
, name
="d_out_%d" % i
)
648 wr_sel
= Signal(ROW_SIZE
)
650 way
= CacheRam(ROW_BITS
, ROW_SIZE_BITS
, True)
651 setattr(m
.submodules
, "cacheram_%d" % i
, way
)
653 comb
+= way
.rd_en
.eq(do_read
)
654 comb
+= way
.rd_addr
.eq(rd_addr
)
655 comb
+= d_out
.eq(way
.rd_data_o
)
656 comb
+= way
.wr_sel
.eq(wr_sel
)
657 comb
+= way
.wr_addr
.eq(wr_addr
)
658 comb
+= way
.wr_data
.eq(wb_in
.dat
)
660 comb
+= do_read
.eq(~
(stall_in | use_previous
))
661 comb
+= do_write
.eq(wb_in
.ack
& (replace_way
== i
))
663 with m
.If(r
.hit_way
== i
):
664 comb
+= cache_out_row
.eq(d_out
)
665 comb
+= rd_addr
.eq(req_row
)
666 comb
+= wr_addr
.eq(r
.store_row
)
667 comb
+= wr_sel
.eq(Repl(do_write
, ROW_SIZE
))
670 # maybe_plrus: if NUM_WAYS > 1 generate
672 # plrus: for i in 0 to NUM_LINES-1 generate
674 # signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
675 # signal plru_acc_en : std_ulogic;
676 # signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
679 # plru : entity work.plru
687 # acc_en => plru_acc_en,
694 # if get_index(r.hit_nia) = i then
695 # plru_acc_en <= r.hit_valid;
697 # plru_acc_en <= '0';
700 # std_ulogic_vector(to_unsigned(r.hit_way, WAY_BITS));
701 # plru_victim(i) <= plru_out;
705 def maybe_plrus(self
, m
, r
, plru_victim
):
708 with m
.If(NUM_WAYS
> 1):
709 for i
in range(NUM_LINES
):
710 plru_acc_i
= Signal(WAY_BITS
)
711 plru_acc_en
= Signal()
712 plru
= PLRU(WAY_BITS
)
713 setattr(m
.submodules
, "plru_%d" % i
, plru
)
715 comb
+= plru
.acc_i
.eq(plru_acc_i
)
716 comb
+= plru
.acc_en
.eq(plru_acc_en
)
719 with m
.If(get_index(r
.hit_nia
) == i
):
720 comb
+= plru
.acc_en
.eq(r
.hit_valid
)
722 comb
+= plru
.acc_i
.eq(r
.hit_way
)
723 comb
+= plru_victim
[i
].eq(plru
.lru_o
)
725 # -- TLB hit detection and real address generation
726 # itlb_lookup : process(all)
727 # variable pte : tlb_pte_t;
728 # variable ttag : tlb_tag_t;
730 # tlb_req_index <= hash_ea(i_in.nia);
731 # pte := itlb_ptes(tlb_req_index);
732 # ttag := itlb_tags(tlb_req_index);
733 # if i_in.virt_mode = '1' then
734 # real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
735 # i_in.nia(TLB_LG_PGSZ - 1 downto 0);
736 # if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then
737 # ra_valid <= itlb_valids(tlb_req_index);
741 # eaa_priv <= pte(3);
743 # real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
748 # -- no IAMR, so no KUEP support for now
749 # priv_fault <= eaa_priv and not i_in.priv_mode;
750 # access_ok <= ra_valid and not priv_fault;
752 # TLB hit detection and real address generation
753 def itlb_lookup(self
, m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
754 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
755 priv_fault
, access_ok
):
760 pte
= Signal(TLB_PTE_BITS
)
761 ttag
= Signal(TLB_EA_TAG_BITS
)
763 comb
+= tlb_req_index
.eq(hash_ea(i_in
.nia
))
764 comb
+= pte
.eq(itlb_ptes
[tlb_req_index
])
765 comb
+= ttag
.eq(itlb_tags
[tlb_req_index
])
767 with m
.If(i_in
.virt_mode
):
768 comb
+= real_addr
.eq(Cat(
769 i_in
.nia
[:TLB_LG_PGSZ
],
770 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
773 with m
.If(ttag
== i_in
.nia
[TLB_LG_PGSZ
+ TLB_BITS
:64]):
774 comb
+= ra_valid
.eq(itlb_valid_bits
[tlb_req_index
])
776 comb
+= eaa_priv
.eq(pte
[3])
779 comb
+= real_addr
.eq(i_in
.nia
[:REAL_ADDR_BITS
])
780 comb
+= ra_valid
.eq(1)
781 comb
+= eaa_priv
.eq(1)
783 # No IAMR, so no KUEP support for now
784 comb
+= priv_fault
.eq(eaa_priv
& ~i_in
.priv_mode
)
785 comb
+= access_ok
.eq(ra_valid
& ~priv_fault
)
788 # itlb_update: process(clk)
789 # variable wr_index : tlb_index_t;
791 # if rising_edge(clk) then
792 # wr_index := hash_ea(m_in.addr);
794 # (m_in.tlbie = '1' and m_in.doall = '1') then
795 # -- clear all valid bits
796 # for i in tlb_index_t loop
797 # itlb_valids(i) <= '0';
799 # elsif m_in.tlbie = '1' then
800 # -- clear entry regardless of hit or miss
801 # itlb_valids(wr_index) <= '0';
802 # elsif m_in.tlbld = '1' then
803 # itlb_tags(wr_index) <=
804 # m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS);
805 # itlb_ptes(wr_index) <= m_in.pte;
806 # itlb_valids(wr_index) <= '1';
811 def itlb_update(self
, m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
):
817 wr_index
= Signal(TLB_SIZE
)
818 sync
+= wr_index
.eq(hash_ea(m_in
.addr
))
820 with m
.If(m_in
.tlbie
& m_in
.doall
):
821 # Clear all valid bits
822 for i
in range(TLB_SIZE
):
823 sync
+= itlb_valid_bits
[i
].eq(0)
825 with m
.Elif(m_in
.tlbie
):
826 # Clear entry regardless of hit or miss
827 sync
+= itlb_valid_bits
[wr_index
].eq(0)
829 with m
.Elif(m_in
.tlbld
):
830 sync
+= itlb_tags
[wr_index
].eq(
831 m_in
.addr
[TLB_LG_PGSZ
+ TLB_BITS
:64]
833 sync
+= itlb_ptes
[wr_index
].eq(m_in
.pte
)
834 sync
+= itlb_valid_bits
[wr_index
].eq(1)
836 # -- Cache hit detection, output to fetch2 and other misc logic
837 # icache_comb : process(all)
838 # Cache hit detection, output to fetch2 and other misc logic
839 def icache_comb(self
, m
, use_previous
, r
, req_index
, req_row
,
840 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
841 cache_tags
, access_ok
, req_is_hit
,
842 req_is_miss
, replace_way
, plru_victim
, cache_out_row
):
843 # variable is_hit : std_ulogic;
844 # variable hit_way : way_t;
847 #comb += Display("ENTER icache_comb - use_previous:%x req_index:%x " \
848 # "req_row:%x req_tag:%x real_addr:%x req_laddr:%x " \
849 # "access_ok:%x req_is_hit:%x req_is_miss:%x " \
850 # "replace_way:%x", use_previous, req_index, req_row, \
851 # req_tag, real_addr, req_laddr, access_ok, \
852 # req_is_hit, req_is_miss, replace_way)
854 i_in
, i_out
, wb_out
= self
.i_in
, self
.i_out
, self
.wb_out
855 flush_in
, stall_out
= self
.flush_in
, self
.stall_out
858 hit_way
= Signal(NUM_WAYS
)
860 # -- i_in.sequential means that i_in.nia this cycle
861 # -- is 4 more than last cycle. If we read more
862 # -- than 32 bits at a time, had a cache hit last
863 # -- cycle, and we don't want the first 32-bit chunk
864 # -- then we can keep the data we read last cycle
865 # -- and just use that.
866 # if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
867 # use_previous <= i_in.sequential and r.hit_valid;
869 # use_previous <= '0';
871 # i_in.sequential means that i_in.nia this cycle is 4 more than
872 # last cycle. If we read more than 32 bits at a time, had a
873 # cache hit last cycle, and we don't want the first 32-bit chunk
874 # then we can keep the data we read last cycle and just use that.
875 with m
.If(i_in
.nia
[2:INSN_BITS
+2] != 0):
876 comb
+= use_previous
.eq(i_in
.sequential
& r
.hit_valid
)
878 # -- Extract line, row and tag from request
879 # req_index <= get_index(i_in.nia);
880 # req_row <= get_row(i_in.nia);
881 # req_tag <= get_tag(real_addr);
882 # Extract line, row and tag from request
883 comb
+= req_index
.eq(get_index(i_in
.nia
))
884 comb
+= req_row
.eq(get_row(i_in
.nia
))
885 comb
+= req_tag
.eq(get_tag(real_addr
))
887 # -- Calculate address of beginning of cache row, will be
888 # -- used for cache miss processing if needed
890 # (63 downto REAL_ADDR_BITS => '0') &
891 # real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
892 # (ROW_OFF_BITS-1 downto 0 => '0');
893 # Calculate address of beginning of cache row, will be
894 # used for cache miss processing if needed
895 comb
+= req_laddr
.eq(Cat(
896 Const(0b0, ROW_OFF_BITS
),
897 real_addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
],
901 # -- Test if pending request is a hit on any way
904 # for i in way_t loop
905 # if i_in.req = '1' and
906 # (cache_valids(req_index)(i) = '1' or
907 # (r.state = WAIT_ACK and
908 # req_index = r.store_index and
909 # i = r.store_way and
910 # r.rows_valid(req_row mod ROW_PER_LINE) = '1')) then
911 # if read_tag(i, cache_tags(req_index)) = req_tag then
917 # Test if pending request is a hit on any way
919 comb
+= hitcond
.eq((r
.state
== State
.WAIT_ACK
)
920 & (req_index
== r
.store_index
)
921 & r
.rows_valid
[req_row
% ROW_PER_LINE
])
923 cvb
= Signal(NUM_WAYS
)
924 ctag
= Signal(TAG_RAM_WIDTH
)
925 comb
+= ctag
.eq(cache_tags
[req_index
])
926 comb
+= cvb
.eq(cache_valid_bits
[req_index
])
927 for i
in range(NUM_WAYS
):
928 tagi
= Signal(TAG_BITS
, name
="ti%d" % i
)
929 comb
+= tagi
.eq(read_tag(i
, ctag
))
930 hit_test
= Signal(name
="hit_test%d" % i
)
931 comb
+= hit_test
.eq(i
== r
.store_way
)
932 with m
.If((cvb
[i
] |
(hitcond
& hit_test
)) & (tagi
== req_tag
)):
933 comb
+= hit_way
.eq(i
)
936 # -- Generate the "hit" and "miss" signals
937 # -- for the synchronous blocks
938 # if i_in.req = '1' and access_ok = '1' and flush_in = '0'
940 # req_is_hit <= is_hit;
941 # req_is_miss <= not is_hit;
944 # req_is_miss <= '0';
946 # req_hit_way <= hit_way;
947 # Generate the "hit" and "miss" signals
948 # for the synchronous blocks
949 with m
.If(i_in
.req
& access_ok
& ~flush_in
):
950 comb
+= req_is_hit
.eq(is_hit
)
951 comb
+= req_is_miss
.eq(~is_hit
)
954 comb
+= req_is_hit
.eq(0)
955 comb
+= req_is_miss
.eq(0)
957 # -- The way to replace on a miss
958 # if r.state = CLR_TAG then
960 # to_integer(unsigned(plru_victim(r.store_index)));
962 # replace_way <= r.store_way;
964 # The way to replace on a miss
965 with m
.If(r
.state
== State
.CLR_TAG
):
966 comb
+= replace_way
.eq(plru_victim
[r
.store_index
])
969 comb
+= replace_way
.eq(r
.store_way
)
971 # -- Output instruction from current cache row
973 # -- Note: This is a mild violation of our design principle of
974 # -- having pipeline stages output from a clean latch. In this
975 # -- case we output the result of a mux. The alternative would
976 # -- be output an entire row which I prefer not to do just yet
977 # -- as it would force fetch2 to know about some of the cache
978 # -- geometry information.
979 # i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
980 # i_out.valid <= r.hit_valid;
981 # i_out.nia <= r.hit_nia;
982 # i_out.stop_mark <= r.hit_smark;
983 # i_out.fetch_failed <= r.fetch_failed;
984 # Output instruction from current cache row
986 # Note: This is a mild violation of our design principle of
987 # having pipeline stages output from a clean latch. In this
988 # case we output the result of a mux. The alternative would
989 # be output an entire row which I prefer not to do just yet
990 # as it would force fetch2 to know about some of the cache
991 # geometry information.
992 #comb += Display("BEFORE read_insn_word - r.hit_nia:%x " \
993 # "r.hit_way:%x, cache_out[r.hit_way]:%x", r.hit_nia, \
994 # r.hit_way, cache_out[r.hit_way])
995 comb
+= i_out
.insn
.eq(read_insn_word(r
.hit_nia
, cache_out_row
))
996 comb
+= i_out
.valid
.eq(r
.hit_valid
)
997 comb
+= i_out
.nia
.eq(r
.hit_nia
)
998 comb
+= i_out
.stop_mark
.eq(r
.hit_smark
)
999 comb
+= i_out
.fetch_failed
.eq(r
.fetch_failed
)
1001 # -- Stall fetch1 if we have a miss on cache or TLB
1002 # -- or a protection fault
1003 # stall_out <= not (is_hit and access_ok);
1004 # Stall fetch1 if we have a miss on cache or TLB
1005 # or a protection fault
1006 comb
+= stall_out
.eq(~
(is_hit
& access_ok
))
1008 # -- Wishbone requests output (from the cache miss reload machine)
1009 # wishbone_out <= r.wb;
1010 # Wishbone requests output (from the cache miss reload machine)
1011 comb
+= wb_out
.eq(r
.wb
)
1014 # -- Cache hit synchronous machine
1015 # icache_hit : process(clk)
1016 # Cache hit synchronous machine
1017 def icache_hit(self
, m
, use_previous
, r
, req_is_hit
, req_hit_way
,
1018 req_index
, req_tag
, real_addr
):
1021 i_in
, stall_in
= self
.i_in
, self
.stall_in
1022 flush_in
= self
.flush_in
1025 # if rising_edge(clk) then
1026 # -- keep outputs to fetch2 unchanged on a stall
1027 # -- except that flush or reset sets valid to 0
1028 # -- If use_previous, keep the same data as last
1029 # -- cycle and use the second half
1030 # if stall_in = '1' or use_previous = '1' then
1031 # if rst = '1' or flush_in = '1' then
1032 # r.hit_valid <= '0';
1034 # keep outputs to fetch2 unchanged on a stall
1035 # except that flush or reset sets valid to 0
1036 # If use_previous, keep the same data as last
1037 # cycle and use the second half
1038 with m
.If(stall_in | use_previous
):
1039 with m
.If(flush_in
):
1040 sync
+= r
.hit_valid
.eq(0)
1042 # -- On a hit, latch the request for the next cycle,
1043 # -- when the BRAM data will be available on the
1044 # -- cache_out output of the corresponding way
1045 # r.hit_valid <= req_is_hit;
1046 # if req_is_hit = '1' then
1047 # r.hit_way <= req_hit_way;
1049 # On a hit, latch the request for the next cycle,
1050 # when the BRAM data will be available on the
1051 # cache_out output of the corresponding way
1052 sync
+= r
.hit_valid
.eq(req_is_hit
)
1054 with m
.If(req_is_hit
):
1055 sync
+= r
.hit_way
.eq(req_hit_way
)
1057 # report "cache hit nia:" & to_hstring(i_in.nia) &
1058 # " IR:" & std_ulogic'image(i_in.virt_mode) &
1059 # " SM:" & std_ulogic'image(i_in.stop_mark) &
1060 # " idx:" & integer'image(req_index) &
1061 # " tag:" & to_hstring(req_tag) &
1062 # " way:" & integer'image(req_hit_way) &
1063 # " RA:" & to_hstring(real_addr);
1064 sync
+= Display("cache hit nia:%x IR:%x SM:%x idx:%x " \
1065 "tag:%x way:%x RA:%x", i_in
.nia
, \
1066 i_in
.virt_mode
, i_in
.stop_mark
, req_index
, \
1067 req_tag
, req_hit_way
, real_addr
)
1073 # if stall_in = '0' then
1074 # -- Send stop marks and NIA down regardless of validity
1075 # r.hit_smark <= i_in.stop_mark;
1076 # r.hit_nia <= i_in.nia;
1078 with m
.If(~stall_in
):
1079 # Send stop marks and NIA down regardless of validity
1080 sync
+= r
.hit_smark
.eq(i_in
.stop_mark
)
1081 sync
+= r
.hit_nia
.eq(i_in
.nia
)
1085 # -- Cache miss/reload synchronous machine
1086 # icache_miss : process(clk)
1087 # Cache miss/reload synchronous machine
1088 def icache_miss(self
, m
, cache_valid_bits
, r
, req_is_miss
,
1089 req_index
, req_laddr
, req_tag
, replace_way
,
1090 cache_tags
, access_ok
, real_addr
):
1094 i_in
, wb_in
, m_in
= self
.i_in
, self
.wb_in
, self
.m_in
1095 stall_in
, flush_in
= self
.stall_in
, self
.flush_in
1096 inval_in
= self
.inval_in
1098 # variable tagset : cache_tags_set_t;
1099 # variable stbs_done : boolean;
1101 tagset
= Signal(TAG_RAM_WIDTH
)
1102 stbs_done
= Signal()
1105 # if rising_edge(clk) then
1106 # -- On reset, clear all valid bits to force misses
1108 # On reset, clear all valid bits to force misses
1109 # for i in index_t loop
1110 # cache_valids(i) <= (others => '0');
1115 # -- We only ever do reads on wishbone
1116 # r.wb.dat <= (others => '0');
1117 # r.wb.sel <= "11111111";
1120 # -- Not useful normally but helps avoiding
1121 # -- tons of sim warnings
1122 # r.wb.adr <= (others => '0');
1126 # -- Process cache invalidations
1127 # if inval_in = '1' then
1128 # for i in index_t loop
1129 # cache_valids(i) <= (others => '0');
1131 # r.store_valid <= '0';
1133 comb
+= r
.wb
.sel
.eq(-1)
1134 comb
+= r
.wb
.adr
.eq(r
.req_adr
[3:])
1136 # Process cache invalidations
1137 with m
.If(inval_in
):
1138 for i
in range(NUM_LINES
):
1139 sync
+= cache_valid_bits
[i
].eq(0)
1140 sync
+= r
.store_valid
.eq(0)
1142 # -- Main state machine
1144 # Main state machine
1145 with m
.Switch(r
.state
):
1148 with m
.Case(State
.IDLE
):
1149 # -- Reset per-row valid flags,
1150 # -- only used in WAIT_ACK
1151 # for i in 0 to ROW_PER_LINE - 1 loop
1152 # r.rows_valid(i) <= '0';
1154 # Reset per-row valid flags,
1155 # only used in WAIT_ACK
1156 for i
in range(ROW_PER_LINE
):
1157 sync
+= r
.rows_valid
[i
].eq(0)
1159 # -- We need to read a cache line
1160 # if req_is_miss = '1' then
1161 # report "cache miss nia:" & to_hstring(i_in.nia) &
1162 # " IR:" & std_ulogic'image(i_in.virt_mode) &
1163 # " SM:" & std_ulogic'image(i_in.stop_mark) &
1164 # " idx:" & integer'image(req_index) &
1165 # " way:" & integer'image(replace_way) &
1166 # " tag:" & to_hstring(req_tag) &
1167 # " RA:" & to_hstring(real_addr);
1168 # We need to read a cache line
1169 with m
.If(req_is_miss
):
1171 "cache miss nia:%x IR:%x SM:%x idx:%x " \
1172 " way:%x tag:%x RA:%x", i_in
.nia
, \
1173 i_in
.virt_mode
, i_in
.stop_mark
, req_index
, \
1174 replace_way
, req_tag
, real_addr
)
1176 # -- Keep track of our index and way for
1177 # -- subsequent stores
1178 # r.store_index <= req_index;
1179 # r.store_row <= get_row(req_laddr);
1180 # r.store_tag <= req_tag;
1181 # r.store_valid <= '1';
1183 # get_row_of_line(get_row(req_laddr)) - 1;
1184 # Keep track of our index and way
1185 # for subsequent stores
1186 sync
+= r
.store_index
.eq(req_index
)
1187 sync
+= r
.store_row
.eq(get_row(req_laddr
))
1188 sync
+= r
.store_tag
.eq(req_tag
)
1189 sync
+= r
.store_valid
.eq(1)
1190 sync
+= r
.end_row_ix
.eq(
1196 # -- Prep for first wishbone read. We calculate the
1197 # -- address of the start of the cache line and
1198 # -- start the WB cycle.
1199 # r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
1202 # Prep for first wishbone read.
1204 # address of the start of the cache line and
1205 # start the WB cycle.
1206 sync
+= r
.req_adr
.eq(req_laddr
)
1207 sync
+= r
.wb
.cyc
.eq(1)
1208 sync
+= r
.wb
.stb
.eq(1)
1210 # -- Track that we had one request sent
1211 # r.state <= CLR_TAG;
1212 # Track that we had one request sent
1213 sync
+= r
.state
.eq(State
.CLR_TAG
)
1216 # when CLR_TAG | WAIT_ACK =>
1217 with m
.Case(State
.CLR_TAG
, State
.WAIT_ACK
):
1218 # if r.state = CLR_TAG then
1219 with m
.If(r
.state
== State
.CLR_TAG
):
1220 # -- Get victim way from plru
1221 # r.store_way <= replace_way;
1222 # Get victim way from plru
1223 sync
+= r
.store_way
.eq(replace_way
)
1225 # -- Force misses on that way while
1226 # -- reloading that line
1227 # cache_valids(req_index)(replace_way) <= '0';
1228 # Force misses on that way while
1229 # realoading that line
1230 cv
= Signal(INDEX_BITS
)
1231 comb
+= cv
.eq(cache_valid_bits
[req_index
])
1232 comb
+= cv
.bit_select(replace_way
, 1).eq(0)
1233 sync
+= cache_valid_bits
[req_index
].eq(cv
)
1235 # -- Store new tag in selected way
1236 # for i in 0 to NUM_WAYS-1 loop
1237 # if i = replace_way then
1238 # tagset := cache_tags(r.store_index);
1239 # write_tag(i, tagset, r.store_tag);
1240 # cache_tags(r.store_index) <= tagset;
1243 for i
in range(NUM_WAYS
):
1244 with m
.If(i
== replace_way
):
1245 comb
+= tagset
.eq(cache_tags
[r
.store_index
])
1246 comb
+= write_tag(i
, tagset
, r
.store_tag
)
1247 sync
+= cache_tags
[r
.store_index
].eq(tagset
)
1249 # r.state <= WAIT_ACK;
1250 sync
+= r
.state
.eq(State
.WAIT_ACK
)
1253 # -- Requests are all sent if stb is 0
1254 # stbs_done := r.wb.stb = '0';
1255 # Requests are all sent if stb is 0
1256 stbs_zero
= Signal()
1257 comb
+= stbs_zero
.eq(r
.wb
.stb
== 0)
1258 comb
+= stbs_done
.eq(stbs_zero
)
1260 # -- If we are still sending requests,
1261 # -- was one accepted ?
1262 # if wishbone_in.stall = '0' and not stbs_done then
1263 # If we are still sending requests,
1265 with m
.If(~wb_in
.stall
& ~stbs_zero
):
1266 # -- That was the last word ? We are done sending.
1267 # -- Clear stb and set stbs_done so we can handle
1268 # -- an eventual last ack on the same cycle.
1269 # if is_last_row_addr(r.wb.adr, r.end_row_ix) then
1271 # stbs_done := true;
1273 # That was the last word ?
1274 # We are done sending.
1275 # Clear stb and set stbs_done
1277 # an eventual last ack on
1279 with m
.If(is_last_row_addr(r
.req_adr
, r
.end_row_ix
)):
1280 sync
+= Display("IS_LAST_ROW_ADDR " \
1281 "r.wb.addr:%x r.end_row_ix:%x " \
1282 "r.wb.stb:%x stbs_zero:%x " \
1283 "stbs_done:%x", r
.wb
.adr
, \
1284 r
.end_row_ix
, r
.wb
.stb
, \
1285 stbs_zero
, stbs_done
)
1286 sync
+= r
.wb
.stb
.eq(0)
1287 comb
+= stbs_done
.eq(1)
1289 # -- Calculate the next row address
1290 # r.wb.adr <= next_row_addr(r.wb.adr);
1291 # Calculate the next row address
1292 rarange
= Signal(LINE_OFF_BITS
- ROW_OFF_BITS
)
1294 r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
] + 1
1296 sync
+= r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
].eq(
1299 sync
+= Display("RARANGE r.wb.adr:%x stbs_zero:%x " \
1300 "stbs_done:%x", rarange
, stbs_zero
, \
1304 # -- Incoming acks processing
1305 # if wishbone_in.ack = '1' then
1306 # Incoming acks processing
1307 with m
.If(wb_in
.ack
):
1308 # r.rows_valid(r.store_row mod ROW_PER_LINE)
1310 sync
+= Display("WB_IN_ACK stbs_zero:%x " \
1312 stbs_zero
, stbs_done
)
1314 sync
+= r
.rows_valid
[r
.store_row
% ROW_PER_LINE
].eq(1)
1316 # -- Check for completion
1318 # is_last_row(r.store_row, r.end_row_ix) then
1319 # Check for completion
1320 with m
.If(stbs_done
&
1321 is_last_row(r
.store_row
, r
.end_row_ix
)):
1322 # -- Complete wishbone cycle
1324 # Complete wishbone cycle
1325 sync
+= r
.wb
.cyc
.eq(0)
1327 # -- Cache line is now valid
1328 # cache_valids(r.store_index)(replace_way) <=
1329 # r.store_valid and not inval_in;
1330 # Cache line is now valid
1331 cv
= Signal(INDEX_BITS
)
1332 comb
+= cv
.eq(cache_valid_bits
[r
.store_index
])
1333 comb
+= cv
.bit_select(replace_way
, 1).eq(
1334 r
.store_valid
& ~inval_in
1336 sync
+= cache_valid_bits
[r
.store_index
].eq(cv
)
1341 sync
+= r
.state
.eq(State
.IDLE
)
1344 # -- Increment store row counter
1345 # r.store_row <= next_row(r.store_row);
1346 # Increment store row counter
1347 sync
+= r
.store_row
.eq(next_row(r
.store_row
))
1352 # -- TLB miss and protection fault processing
1353 # if rst = '1' or flush_in = '1' or m_in.tlbld = '1' then
1354 # r.fetch_failed <= '0';
1355 # elsif i_in.req = '1' and access_ok = '0' and
1356 # stall_in = '0' then
1357 # r.fetch_failed <= '1';
1359 # TLB miss and protection fault processing
1360 with m
.If(flush_in | m_in
.tlbld
):
1361 sync
+= r
.fetch_failed
.eq(0)
1363 with m
.Elif(i_in
.req
& ~access_ok
& ~stall_in
):
1364 sync
+= r
.fetch_failed
.eq(1)
1368 # icache_log: if LOG_LENGTH > 0 generate
1369 def icache_log(self
, m
, req_hit_way
, ra_valid
, access_ok
,
1370 req_is_miss
, req_is_hit
, lway
, wstate
, r
):
1374 wb_in
, i_out
= self
.wb_in
, self
.i_out
1375 log_out
, stall_out
= self
.log_out
, self
.stall_out
1377 # -- Output data to logger
1378 # signal log_data : std_ulogic_vector(53 downto 0);
1380 # data_log: process(clk)
1381 # variable lway: way_t;
1382 # variable wstate: std_ulogic;
1383 # Output data to logger
1384 for i
in range(LOG_LENGTH
):
1385 # Output data to logger
1386 log_data
= Signal(54)
1387 lway
= Signal(NUM_WAYS
)
1391 # if rising_edge(clk) then
1392 # lway := req_hit_way;
1394 sync
+= lway
.eq(req_hit_way
)
1395 sync
+= wstate
.eq(0)
1397 # if r.state /= IDLE then
1400 with m
.If(r
.state
!= State
.IDLE
):
1401 sync
+= wstate
.eq(1)
1403 # log_data <= i_out.valid &
1406 # r.wb.adr(5 downto 3) &
1407 # r.wb.stb & r.wb.cyc &
1408 # wishbone_in.stall &
1411 # r.hit_nia(5 downto 2) &
1413 # std_ulogic_vector(to_unsigned(lway, 3)) &
1414 # req_is_hit & req_is_miss &
1417 sync
+= log_data
.eq(Cat(
1418 ra_valid
, access_ok
, req_is_miss
, req_is_hit
,
1419 lway
, wstate
, r
.hit_nia
[2:6],
1420 r
.fetch_failed
, stall_out
, wb_in
.stall
, r
.wb
.cyc
,
1421 r
.wb
.stb
, r
.wb
.adr
[3:6], wb_in
.ack
, i_out
.insn
,
1426 # log_out <= log_data;
1427 comb
+= log_out
.eq(log_data
)
1431 def elaborate(self
, platform
):
1436 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1437 cache_tags
= CacheTagArray()
1438 cache_valid_bits
= CacheValidBitsArray()
1440 # signal itlb_valids : tlb_valids_t;
1441 # signal itlb_tags : tlb_tags_t;
1442 # signal itlb_ptes : tlb_ptes_t;
1443 # attribute ram_style of itlb_tags : signal is "distributed";
1444 # attribute ram_style of itlb_ptes : signal is "distributed";
1445 itlb_valid_bits
= TLBValidBitsArray()
1446 itlb_tags
= TLBTagArray()
1447 itlb_ptes
= TLBPtesArray()
1448 # TODO to be passed to nmigen as ram attributes
1449 # attribute ram_style of itlb_tags : signal is "distributed";
1450 # attribute ram_style of itlb_ptes : signal is "distributed";
1452 # -- Privilege bit from PTE EAA field
1453 # signal eaa_priv : std_ulogic;
1454 # Privilege bit from PTE EAA field
1457 # signal r : reg_internal_t;
1460 # -- Async signals on incoming request
1461 # signal req_index : index_t;
1462 # signal req_row : row_t;
1463 # signal req_hit_way : way_t;
1464 # signal req_tag : cache_tag_t;
1465 # signal req_is_hit : std_ulogic;
1466 # signal req_is_miss : std_ulogic;
1467 # signal req_laddr : std_ulogic_vector(63 downto 0);
1468 # Async signal on incoming request
1469 req_index
= Signal(NUM_LINES
)
1470 req_row
= Signal(BRAM_ROWS
)
1471 req_hit_way
= Signal(NUM_WAYS
)
1472 req_tag
= Signal(TAG_BITS
)
1473 req_is_hit
= Signal()
1474 req_is_miss
= Signal()
1475 req_laddr
= Signal(64)
1477 # signal tlb_req_index : tlb_index_t;
1478 # signal real_addr : std_ulogic_vector(
1479 # REAL_ADDR_BITS - 1 downto 0
1481 # signal ra_valid : std_ulogic;
1482 # signal priv_fault : std_ulogic;
1483 # signal access_ok : std_ulogic;
1484 # signal use_previous : std_ulogic;
1485 tlb_req_index
= Signal(TLB_SIZE
)
1486 real_addr
= Signal(REAL_ADDR_BITS
)
1488 priv_fault
= Signal()
1489 access_ok
= Signal()
1490 use_previous
= Signal()
1492 # signal cache_out : cache_ram_out_t;
1493 cache_out_row
= Signal(ROW_SIZE_BITS
)
1495 # signal plru_victim : plru_out_t;
1496 # signal replace_way : way_t;
1497 plru_victim
= PLRUOut()
1498 replace_way
= Signal(NUM_WAYS
)
1500 # call sub-functions putting everything together, using shared
1501 # signals established above
1502 self
.rams(m
, r
, cache_out_row
, use_previous
, replace_way
, req_row
)
1503 self
.maybe_plrus(m
, r
, plru_victim
)
1504 self
.itlb_lookup(m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
1505 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
1506 priv_fault
, access_ok
)
1507 self
.itlb_update(m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
)
1508 self
.icache_comb(m
, use_previous
, r
, req_index
, req_row
,
1509 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
1510 cache_tags
, access_ok
, req_is_hit
, req_is_miss
,
1511 replace_way
, plru_victim
, cache_out_row
)
1512 self
.icache_hit(m
, use_previous
, r
, req_is_hit
, req_hit_way
,
1513 req_index
, req_tag
, real_addr
)
1514 self
.icache_miss(m
, cache_valid_bits
, r
, req_is_miss
, req_index
,
1515 req_laddr
, req_tag
, replace_way
, cache_tags
,
1516 access_ok
, real_addr
)
1517 #self.icache_log(m, log_out, req_hit_way, ra_valid, access_ok,
1518 # req_is_miss, req_is_hit, lway, wstate, r)
1526 # use ieee.std_logic_1164.all;
1529 # use work.common.all;
1530 # use work.wishbone_types.all;
1532 # entity icache_tb is
1535 # architecture behave of icache_tb is
1536 # signal clk : std_ulogic;
1537 # signal rst : std_ulogic;
1539 # signal i_out : Fetch1ToIcacheType;
1540 # signal i_in : IcacheToDecode1Type;
1542 # signal m_out : MmuToIcacheType;
1544 # signal wb_bram_in : wishbone_master_out;
1545 # signal wb_bram_out : wishbone_slave_out;
1547 # constant clk_period : time := 10 ns;
1549 # icache0: entity work.icache
1563 # wishbone_out => wb_bram_in,
1564 # wishbone_in => wb_bram_out
1567 # -- BRAM Memory slave
1568 # bram0: entity work.wishbone_bram_wrapper
1570 # MEMORY_SIZE => 1024,
1571 # RAM_INIT_FILE => "icache_test.bin"
1576 # wishbone_in => wb_bram_in,
1577 # wishbone_out => wb_bram_out
1580 # clk_process: process
1583 # wait for clk_period/2;
1585 # wait for clk_period/2;
1588 # rst_process: process
1591 # wait for 2*clk_period;
1599 # i_out.nia <= (others => '0');
1600 # i_out.stop_mark <= '0';
1602 # m_out.tlbld <= '0';
1603 # m_out.tlbie <= '0';
1604 # m_out.addr <= (others => '0');
1605 # m_out.pte <= (others => '0');
1607 # wait until rising_edge(clk);
1608 # wait until rising_edge(clk);
1609 # wait until rising_edge(clk);
1610 # wait until rising_edge(clk);
1613 # i_out.nia <= x"0000000000000004";
1615 # wait for 30*clk_period;
1616 # wait until rising_edge(clk);
1618 # assert i_in.valid = '1' severity failure;
1619 # assert i_in.insn = x"00000001"
1620 # report "insn @" & to_hstring(i_out.nia) &
1621 # "=" & to_hstring(i_in.insn) &
1622 # " expected 00000001"
1627 # wait until rising_edge(clk);
1631 # i_out.nia <= x"0000000000000008";
1632 # wait until rising_edge(clk);
1633 # wait until rising_edge(clk);
1634 # assert i_in.valid = '1' severity failure;
1635 # assert i_in.insn = x"00000002"
1636 # report "insn @" & to_hstring(i_out.nia) &
1637 # "=" & to_hstring(i_in.insn) &
1638 # " expected 00000002"
1640 # wait until rising_edge(clk);
1644 # i_out.nia <= x"0000000000000040";
1646 # wait for 30*clk_period;
1647 # wait until rising_edge(clk);
1649 # assert i_in.valid = '1' severity failure;
1650 # assert i_in.insn = x"00000010"
1651 # report "insn @" & to_hstring(i_out.nia) &
1652 # "=" & to_hstring(i_in.insn) &
1653 # " expected 00000010"
1656 # -- test something that aliases
1658 # i_out.nia <= x"0000000000000100";
1659 # wait until rising_edge(clk);
1660 # wait until rising_edge(clk);
1661 # assert i_in.valid = '0' severity failure;
1662 # wait until rising_edge(clk);
1664 # wait for 30*clk_period;
1665 # wait until rising_edge(clk);
1667 # assert i_in.valid = '1' severity failure;
1668 # assert i_in.insn = x"00000040"
1669 # report "insn @" & to_hstring(i_out.nia) &
1670 # "=" & to_hstring(i_in.insn) &
1671 # " expected 00000040"
1679 def icache_sim(dut
):
1684 yield i_in
.valid
.eq(0)
1685 yield i_out
.priv_mode
.eq(1)
1686 yield i_out
.req
.eq(0)
1687 yield i_out
.nia
.eq(0)
1688 yield i_out
.stop_mark
.eq(0)
1689 yield m_out
.tlbld
.eq(0)
1690 yield m_out
.tlbie
.eq(0)
1691 yield m_out
.addr
.eq(0)
1692 yield m_out
.pte
.eq(0)
1697 yield i_out
.req
.eq(1)
1698 yield i_out
.nia
.eq(Const(0x0000000000000004, 64))
1702 valid
= yield i_in
.valid
1703 nia
= yield i_out
.nia
1704 insn
= yield i_in
.insn
1705 print(f
"valid? {valid}")
1707 assert insn
== 0x00000001, \
1708 "insn @%x=%x expected 00000001" % (nia
, insn
)
1709 yield i_out
.req
.eq(0)
1713 yield i_out
.req
.eq(1)
1714 yield i_out
.nia
.eq(Const(0x0000000000000008, 64))
1717 valid
= yield i_in
.valid
1718 nia
= yield i_in
.nia
1719 insn
= yield i_in
.insn
1721 assert insn
== 0x00000002, \
1722 "insn @%x=%x expected 00000002" % (nia
, insn
)
1726 yield i_out
.req
.eq(1)
1727 yield i_out
.nia
.eq(Const(0x0000000000000040, 64))
1731 valid
= yield i_in
.valid
1732 nia
= yield i_out
.nia
1733 insn
= yield i_in
.insn
1735 assert insn
== 0x00000010, \
1736 "insn @%x=%x expected 00000010" % (nia
, insn
)
1738 # test something that aliases
1739 yield i_out
.req
.eq(1)
1740 yield i_out
.nia
.eq(Const(0x0000000000000100, 64))
1743 valid
= yield i_in
.valid
1748 insn
= yield i_in
.insn
1749 valid
= yield i_in
.valid
1750 insn
= yield i_in
.insn
1752 assert insn
== 0x00000040, \
1753 "insn @%x=%x expected 00000040" % (nia
, insn
)
1754 yield i_out
.req
.eq(0)
1758 def test_icache(mem
):
1761 memory
= Memory(width
=64, depth
=16*64, init
=mem
)
1762 sram
= SRAM(memory
=memory
, granularity
=8)
1766 m
.submodules
.icache
= dut
1767 m
.submodules
.sram
= sram
1769 m
.d
.comb
+= sram
.bus
.cyc
.eq(dut
.wb_out
.cyc
)
1770 m
.d
.comb
+= sram
.bus
.stb
.eq(dut
.wb_out
.stb
)
1771 m
.d
.comb
+= sram
.bus
.we
.eq(dut
.wb_out
.we
)
1772 m
.d
.comb
+= sram
.bus
.sel
.eq(dut
.wb_out
.sel
)
1773 m
.d
.comb
+= sram
.bus
.adr
.eq(dut
.wb_out
.adr
)
1774 m
.d
.comb
+= sram
.bus
.dat_w
.eq(dut
.wb_out
.dat
)
1776 m
.d
.comb
+= dut
.wb_in
.ack
.eq(sram
.bus
.ack
)
1777 m
.d
.comb
+= dut
.wb_in
.dat
.eq(sram
.bus
.dat_r
)
1783 sim
.add_sync_process(wrap(icache_sim(dut
)))
1784 with sim
.write_vcd('test_icache.vcd'):
1787 if __name__
== '__main__':
1789 vl
= rtlil
.convert(dut
, ports
=[])
1790 with
open("test_icache.il", "w") as f
:
1794 for i
in range(512):
1795 mem
.append((i
*2)|
((i
*2+1)<<32))