3 based on Anton Blanchard microwatt icache.vhdl
7 TODO (in no specific order):
8 * Add debug interface to inspect cache content
9 * Add snoop/invalidate path
10 * Add multi-hit error detection
11 * Pipelined bus interface (wb or axi)
12 * Maybe add parity? There's a few bits free in each BRAM row on Xilinx
13 * Add optimization: service hits on partially loaded lines
14 * Add optimization: (maybe) interrupt reload on fluch/redirect
15 * Check if playing with the geometry of the cache tags allow for more
16 efficient use of distributed RAM and less logic/muxes. Currently we
17 write TAG_BITS width which may not match full ram blocks and might
18 cause muxes to be inferred for "partial writes".
19 * Check if making the read size of PLRU a ROM helps utilization
22 from enum
import Enum
, unique
23 from nmigen
import (Module
, Signal
, Elaboratable
, Cat
, Array
, Const
)
24 from nmigen
.cli
import main
, rtlil
25 from nmutil
.iocontrol
import RecordObject
26 from nmigen
.utils
import log2_int
27 from nmutil
.util
import Display
29 #from nmutil.plru import PLRU
30 from soc
.experiment
.cache_ram
import CacheRam
31 from soc
.experiment
.plru
import PLRU
33 from soc
.experiment
.mem_types
import (Fetch1ToICacheType
,
37 from soc
.experiment
.wb_types
import (WB_ADDR_BITS
, WB_DATA_BITS
,
38 WB_SEL_BITS
, WBAddrType
, WBDataType
,
39 WBSelType
, WBMasterOut
, WBSlaveOut
,
40 WBMasterOutVector
, WBSlaveOutVector
,
41 WBIOMasterOut
, WBIOSlaveOut
)
44 from nmigen_soc
.wishbone
.sram
import SRAM
45 from nmigen
import Memory
46 from nmutil
.util
import wrap
47 from nmigen
.cli
import main
, rtlil
49 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
51 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
56 # BRAM organisation: We never access more than wishbone_data_bits
57 # at a time so to save resources we make the array only that wide,
58 # and use consecutive indices for to make a cache "line"
60 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
61 ROW_SIZE
= WB_DATA_BITS
// 8
62 # Number of lines in a set
66 # L1 ITLB number of entries (direct mapped)
68 # L1 ITLB log_2(page_size)
70 # Number of real address bits that we store
72 # Non-zero to enable log data collection
75 ROW_SIZE_BITS
= ROW_SIZE
* 8
76 # ROW_PER_LINE is the number of row
77 # (wishbone) transactions in a line
78 ROW_PER_LINE
= LINE_SIZE
// ROW_SIZE
79 # BRAM_ROWS is the number of rows in
80 # BRAM needed to represent the full icache
81 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
82 # INSN_PER_ROW is the number of 32bit
83 # instructions per BRAM row
84 INSN_PER_ROW
= ROW_SIZE_BITS
// 32
86 print("ROW_SIZE", ROW_SIZE
)
87 print("ROW_SIZE_BITS", ROW_SIZE_BITS
)
88 print("ROW_PER_LINE", ROW_PER_LINE
)
89 print("BRAM_ROWS", BRAM_ROWS
)
90 print("INSN_PER_ROW", INSN_PER_ROW
)
92 # Bit fields counts in the address
94 # INSN_BITS is the number of bits to
95 # select an instruction in a row
96 INSN_BITS
= log2_int(INSN_PER_ROW
)
97 # ROW_BITS is the number of bits to
99 ROW_BITS
= log2_int(BRAM_ROWS
)
100 # ROW_LINEBITS is the number of bits to
101 # select a row within a line
102 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
103 # LINE_OFF_BITS is the number of bits for
104 # the offset in a cache line
105 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
106 # ROW_OFF_BITS is the number of bits for
107 # the offset in a row
108 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
109 # INDEX_BITS is the number of bits to
110 # select a cache line
111 INDEX_BITS
= log2_int(NUM_LINES
)
112 # SET_SIZE_BITS is the log base 2 of
114 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
115 # TAG_BITS is the number of bits of
116 # the tag part of the address
117 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
118 # TAG_WIDTH is the width in bits of each way of the tag RAM
119 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
121 # WAY_BITS is the number of bits to
123 WAY_BITS
= log2_int(NUM_WAYS
)
124 TAG_RAM_WIDTH
= TAG_BITS
* NUM_WAYS
127 # constant TLB_BITS : natural := log2(TLB_SIZE);
128 # constant TLB_EA_TAG_BITS : natural := 64 - (TLB_LG_PGSZ + TLB_BITS);
129 # constant TLB_PTE_BITS : natural := 64;
130 TLB_BITS
= log2_int(TLB_SIZE
)
131 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_BITS
)
135 print("INSN_BITS", INSN_BITS
)
136 print("ROW_BITS", ROW_BITS
)
137 print("ROW_LINE_BITS", ROW_LINE_BITS
)
138 print("LINE_OFF_BITS", LINE_OFF_BITS
)
139 print("ROW_OFF_BITS", ROW_OFF_BITS
)
140 print("INDEX_BITS", INDEX_BITS
)
141 print("SET_SIZE_BITS", SET_SIZE_BITS
)
142 print("TAG_BITS", TAG_BITS
)
143 print("WAY_BITS", WAY_BITS
)
144 print("TAG_RAM_WIDTH", TAG_RAM_WIDTH
)
145 print("TLB_BITS", TLB_BITS
)
146 print("TLB_EA_TAG_BITS", TLB_EA_TAG_BITS
)
147 print("TLB_PTE_BITS", TLB_PTE_BITS
)
152 # architecture rtl of icache is
153 #constant ROW_SIZE_BITS : natural := ROW_SIZE*8;
154 #-- ROW_PER_LINE is the number of row (wishbone
155 #-- transactions) in a line
156 #constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
157 #-- BRAM_ROWS is the number of rows in BRAM
158 #-- needed to represent the full
160 #constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
161 #-- INSN_PER_ROW is the number of 32bit instructions per BRAM row
162 #constant INSN_PER_ROW : natural := ROW_SIZE_BITS / 32;
163 #-- Bit fields counts in the address
165 #-- INSN_BITS is the number of bits to select
166 #-- an instruction in a row
167 #constant INSN_BITS : natural := log2(INSN_PER_ROW);
168 #-- ROW_BITS is the number of bits to select a row
169 #constant ROW_BITS : natural := log2(BRAM_ROWS);
170 #-- ROW_LINEBITS is the number of bits to
171 #-- select a row within a line
172 #constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
173 #-- LINE_OFF_BITS is the number of bits for the offset
175 #constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
176 #-- ROW_OFF_BITS is the number of bits for the offset in a row
177 #constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
178 #-- INDEX_BITS is the number of bits to select a cache line
179 #constant INDEX_BITS : natural := log2(NUM_LINES);
180 #-- SET_SIZE_BITS is the log base 2 of the set size
181 #constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
182 #-- TAG_BITS is the number of bits of the tag part of the address
183 #constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
184 #-- WAY_BITS is the number of bits to select a way
185 #constant WAY_BITS : natural := log2(NUM_WAYS);
187 #-- Example of layout for 32 lines of 64 bytes:
189 #-- .. tag |index| line |
191 #-- .. | | | |00| zero (2)
192 #-- .. | | |-| | INSN_BITS (1)
193 #-- .. | |---| | ROW_LINEBITS (3)
194 #-- .. | |--- - --| LINE_OFF_BITS (6)
195 #-- .. | |- --| ROW_OFF_BITS (3)
196 #-- .. |----- ---| | ROW_BITS (8)
197 #-- .. |-----| | INDEX_BITS (5)
198 #-- .. --------| | TAG_BITS (53)
199 # Example of layout for 32 lines of 64 bytes:
201 # .. tag |index| line |
203 # .. | | | |00| zero (2)
204 # .. | | |-| | INSN_BITS (1)
205 # .. | |---| | ROW_LINEBITS (3)
206 # .. | |--- - --| LINE_OFF_BITS (6)
207 # .. | |- --| ROW_OFF_BITS (3)
208 # .. |----- ---| | ROW_BITS (8)
209 # .. |-----| | INDEX_BITS (5)
210 # .. --------| | TAG_BITS (53)
212 #subtype row_t is integer range 0 to BRAM_ROWS-1;
213 #subtype index_t is integer range 0 to NUM_LINES-1;
214 #subtype way_t is integer range 0 to NUM_WAYS-1;
215 #subtype row_in_line_t is unsigned(ROW_LINEBITS-1 downto 0);
217 #-- The cache data BRAM organized as described above for each way
218 #subtype cache_row_t is std_ulogic_vector(ROW_SIZE_BITS-1 downto 0);
220 #-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
221 #-- not handle a clean (commented) definition of the cache tags as a 3d
222 #-- memory. For now, work around it by putting all the tags
223 #subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
224 # type cache_tags_set_t is array(way_t) of cache_tag_t;
225 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
226 #constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
227 #subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
228 #type cache_tags_array_t is array(index_t) of cache_tags_set_t;
230 return Array(Signal(TAG_RAM_WIDTH
, name
="cachetag_%d" %x) \
231 for x
in range(NUM_LINES
))
233 #-- The cache valid bits
234 #subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
235 #type cache_valids_t is array(index_t) of cache_way_valids_t;
236 #type row_per_line_valid_t is array(0 to ROW_PER_LINE - 1) of std_ulogic;
237 def CacheValidBitsArray():
238 return Array(Signal(NUM_WAYS
, name
="cachevalid_%d" %x) \
239 for x
in range(NUM_LINES
))
241 def RowPerLineValidArray():
242 return Array(Signal(name
="rows_valid_%d" %x) \
243 for x
in range(ROW_PER_LINE
))
246 #attribute ram_style : string;
247 #attribute ram_style of cache_tags : signal is "distributed";
248 # TODO to be passed to nigmen as ram attributes
249 # attribute ram_style : string;
250 # attribute ram_style of cache_tags : signal is "distributed";
253 #subtype tlb_index_t is integer range 0 to TLB_SIZE - 1;
254 #type tlb_valids_t is array(tlb_index_t) of std_ulogic;
255 #subtype tlb_tag_t is std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
256 #type tlb_tags_t is array(tlb_index_t) of tlb_tag_t;
257 #subtype tlb_pte_t is std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
258 #type tlb_ptes_t is array(tlb_index_t) of tlb_pte_t;
259 def TLBValidBitsArray():
260 return Array(Signal(name
="tlbvalid_%d" %x) \
261 for x
in range(TLB_SIZE
))
264 return Array(Signal(TLB_EA_TAG_BITS
, name
="tlbtag_%d" %x) \
265 for x
in range(TLB_SIZE
))
268 return Array(Signal(TLB_PTE_BITS
, name
="tlbptes_%d" %x) \
269 for x
in range(TLB_SIZE
))
272 #-- Cache RAM interface
273 #type cache_ram_out_t is array(way_t) of cache_row_t;
274 # Cache RAM interface
276 return Array(Signal(ROW_SIZE_BITS
, name
="cache_out_%d" %x) \
277 for x
in range(NUM_WAYS
))
279 #-- PLRU output interface
280 #type plru_out_t is array(index_t) of
281 # std_ulogic_vector(WAY_BITS-1 downto 0);
282 # PLRU output interface
284 return Array(Signal(WAY_BITS
, name
="plru_out_%d" %x) \
285 for x
in range(NUM_LINES
))
287 # -- Return the cache line index (tag index) for an address
288 # function get_index(addr: std_ulogic_vector(63 downto 0))
291 # return to_integer(unsigned(
292 # addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS)
295 # Return the cache line index (tag index) for an address
297 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
299 # -- Return the cache row index (data memory) for an address
300 # function get_row(addr: std_ulogic_vector(63 downto 0))
303 # return to_integer(unsigned(
304 # addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS)
307 # Return the cache row index (data memory) for an address
309 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
311 # -- Return the index of a row within a line
312 # function get_row_of_line(row: row_t) return row_in_line_t is
313 # variable row_v : unsigned(ROW_BITS-1 downto 0);
315 # row_v := to_unsigned(row, ROW_BITS);
316 # return row_v(ROW_LINEBITS-1 downto 0);
318 # Return the index of a row within a line
319 def get_row_of_line(row
):
320 return row
[:ROW_LINE_BITS
]
322 # -- Returns whether this is the last row of a line
323 # function is_last_row_addr(addr: wishbone_addr_type;
324 # last: row_in_line_t
329 # addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)
332 # Returns whether this is the last row of a line
333 def is_last_row_addr(addr
, last
):
334 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
336 # -- Returns whether this is the last row of a line
337 # function is_last_row(row: row_t;
338 # last: row_in_line_t) return boolean is
340 # return get_row_of_line(row) = last;
342 # Returns whether this is the last row of a line
343 def is_last_row(row
, last
):
344 return get_row_of_line(row
) == last
346 # -- Return the next row in the current cache line. We use a dedicated
347 # -- function in order to limit the size of the generated adder to be
348 # -- only the bits within a cache line (3 bits with default settings)
349 # function next_row(row: row_t) return row_t is
350 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
351 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
352 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
354 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
355 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
356 # row_v(ROW_LINEBITS-1 downto 0) :=
357 # std_ulogic_vector(unsigned(row_idx) + 1);
358 # return to_integer(unsigned(row_v));
360 # Return the next row in the current cache line. We use a dedicated
361 # function in order to limit the size of the generated adder to be
362 # only the bits within a cache line (3 bits with default settings)
364 row_v
= row
[0:ROW_LINE_BITS
] + 1
365 return Cat(row_v
[:ROW_LINE_BITS
], row
[ROW_LINE_BITS
:])
366 # -- Read the instruction word for the given address in the
367 # -- current cache row
368 # function read_insn_word(addr: std_ulogic_vector(63 downto 0);
369 # data: cache_row_t) return std_ulogic_vector is
370 # variable word: integer range 0 to INSN_PER_ROW-1;
372 # word := to_integer(unsigned(addr(INSN_BITS+2-1 downto 2)));
373 # return data(31+word*32 downto word*32);
375 # Read the instruction word for the given address
376 # in the current cache row
377 def read_insn_word(addr
, data
):
378 word
= addr
[2:INSN_BITS
+2]
379 return data
.word_select(word
, 32)
381 # -- Get the tag value from the address
383 # addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)
385 # return cache_tag_t is
387 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
389 # Get the tag value from the address
391 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
393 # -- Read a tag from a tag memory row
394 # function read_tag(way: way_t; tagset: cache_tags_set_t)
395 # return cache_tag_t is
397 # return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
399 # Read a tag from a tag memory row
400 def read_tag(way
, tagset
):
401 return tagset
.word_select(way
, TAG_WIDTH
)[:TAG_BITS
]
403 # -- Write a tag to tag memory row
404 # procedure write_tag(way: in way_t;
405 # tagset: inout cache_tags_set_t; tag: cache_tag_t) is
407 # tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
409 # Write a tag to tag memory row
410 def write_tag(way
, tagset
, tag
):
411 return tagset
[way
* TAG_BITS
:(way
+ 1) * TAG_BITS
].eq(tag
)
413 # -- Simple hash for direct-mapped TLB index
414 # function hash_ea(addr: std_ulogic_vector(63 downto 0))
415 # return tlb_index_t is
416 # variable hash : std_ulogic_vector(TLB_BITS - 1 downto 0);
418 # hash := addr(TLB_LG_PGSZ + TLB_BITS - 1 downto TLB_LG_PGSZ)
420 # TLB_LG_PGSZ + 2 * TLB_BITS - 1 downto
421 # TLB_LG_PGSZ + TLB_BITS
424 # TLB_LG_PGSZ + 3 * TLB_BITS - 1 downto
425 # TLB_LG_PGSZ + 2 * TLB_BITS
427 # return to_integer(unsigned(hash));
429 # Simple hash for direct-mapped TLB index
431 hsh
= addr
[TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_BITS
] ^ addr
[
432 TLB_LG_PGSZ
+ TLB_BITS
:TLB_LG_PGSZ
+ 2 * TLB_BITS
434 TLB_LG_PGSZ
+ 2 * TLB_BITS
:TLB_LG_PGSZ
+ 3 * TLB_BITS
440 # assert LINE_SIZE mod ROW_SIZE = 0;
441 # assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2"
443 # assert ispow2(NUM_LINES) report "NUM_LINES not power of 2"
445 # assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2"
447 # assert ispow2(INSN_PER_ROW) report "INSN_PER_ROW not power of 2"
449 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
450 # report "geometry bits don't add up" severity FAILURE;
451 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
452 # report "geometry bits don't add up" severity FAILURE;
453 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
454 # report "geometry bits don't add up" severity FAILURE;
455 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
456 # report "geometry bits don't add up" severity FAILURE;
458 # sim_debug: if SIM generate
461 # report "ROW_SIZE = " & natural'image(ROW_SIZE);
462 # report "ROW_PER_LINE = " & natural'image(ROW_PER_LINE);
463 # report "BRAM_ROWS = " & natural'image(BRAM_ROWS);
464 # report "INSN_PER_ROW = " & natural'image(INSN_PER_ROW);
465 # report "INSN_BITS = " & natural'image(INSN_BITS);
466 # report "ROW_BITS = " & natural'image(ROW_BITS);
467 # report "ROW_LINEBITS = " & natural'image(ROW_LINEBITS);
468 # report "LINE_OFF_BITS = " & natural'image(LINE_OFF_BITS);
469 # report "ROW_OFF_BITS = " & natural'image(ROW_OFF_BITS);
470 # report "INDEX_BITS = " & natural'image(INDEX_BITS);
471 # report "TAG_BITS = " & natural'image(TAG_BITS);
472 # report "WAY_BITS = " & natural'image(WAY_BITS);
477 # Cache reload state machine
484 # type reg_internal_t is record
485 # -- Cache hit state (Latches for 1 cycle BRAM access)
487 # hit_nia : std_ulogic_vector(63 downto 0);
488 # hit_smark : std_ulogic;
489 # hit_valid : std_ulogic;
491 # -- Cache miss state (reload state machine)
493 # wb : wishbone_master_out;
495 # store_index : index_t;
497 # store_tag : cache_tag_t;
498 # store_valid : std_ulogic;
499 # end_row_ix : row_in_line_t;
500 # rows_valid : row_per_line_valid_t;
503 # fetch_failed : std_ulogic;
505 class RegInternal(RecordObject
):
508 # Cache hit state (Latches for 1 cycle BRAM access)
509 self
.hit_way
= Signal(NUM_WAYS
)
510 self
.hit_nia
= Signal(64)
511 self
.hit_smark
= Signal()
512 self
.hit_valid
= Signal()
514 # Cache miss state (reload state machine)
515 self
.state
= Signal(State
, reset
=State
.IDLE
)
516 self
.wb
= WBMasterOut("wb")
517 self
.req_adr
= Signal(64)
518 self
.store_way
= Signal(NUM_WAYS
)
519 self
.store_index
= Signal(NUM_LINES
)
520 self
.store_row
= Signal(BRAM_ROWS
)
521 self
.store_tag
= Signal(TAG_BITS
)
522 self
.store_valid
= Signal()
523 self
.end_row_ix
= Signal(ROW_LINE_BITS
)
524 self
.rows_valid
= RowPerLineValidArray()
527 self
.fetch_failed
= Signal()
529 # -- 64 bit direct mapped icache. All instructions are 4B aligned.
533 # SIM : boolean := false;
534 # -- Line size in bytes
535 # LINE_SIZE : positive := 64;
536 # -- BRAM organisation: We never access more
537 # -- than wishbone_data_bits
538 # -- at a time so to save resources we make the
539 # -- array only that wide,
540 # -- and use consecutive indices for to make a cache "line"
542 # -- ROW_SIZE is the width in bytes of the BRAM (based on WB,
544 # ROW_SIZE : positive := wishbone_data_bits / 8;
545 # -- Number of lines in a set
546 # NUM_LINES : positive := 32;
548 # NUM_WAYS : positive := 4;
549 # -- L1 ITLB number of entries (direct mapped)
550 # TLB_SIZE : positive := 64;
551 # -- L1 ITLB log_2(page_size)
552 # TLB_LG_PGSZ : positive := 12;
553 # -- Number of real address bits that we store
554 # REAL_ADDR_BITS : positive := 56;
555 # -- Non-zero to enable log data collection
556 # LOG_LENGTH : natural := 0
559 # clk : in std_ulogic;
560 # rst : in std_ulogic;
562 # i_in : in Fetch1ToIcacheType;
563 # i_out : out IcacheToDecode1Type;
565 # m_in : in MmuToIcacheType;
567 # stall_in : in std_ulogic;
568 # stall_out : out std_ulogic;
569 # flush_in : in std_ulogic;
570 # inval_in : in std_ulogic;
572 # wishbone_out : out wishbone_master_out;
573 # wishbone_in : in wishbone_slave_out;
575 # log_out : out std_ulogic_vector(53 downto 0)
578 # 64 bit direct mapped icache. All instructions are 4B aligned.
579 class ICache(Elaboratable
):
580 """64 bit direct mapped icache. All instructions are 4B aligned."""
582 self
.i_in
= Fetch1ToICacheType(name
="i_in")
583 self
.i_out
= ICacheToDecode1Type(name
="i_out")
585 self
.m_in
= MMUToICacheType(name
="m_in")
587 self
.stall_in
= Signal()
588 self
.stall_out
= Signal()
589 self
.flush_in
= Signal()
590 self
.inval_in
= Signal()
592 self
.wb_out
= WBMasterOut(name
="wb_out")
593 self
.wb_in
= WBSlaveOut(name
="wb_in")
595 self
.log_out
= Signal(54)
598 # -- Generate a cache RAM for each way
599 # rams: for i in 0 to NUM_WAYS-1 generate
600 # signal do_read : std_ulogic;
601 # signal do_write : std_ulogic;
602 # signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
603 # signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
604 # signal dout : cache_row_t;
605 # signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
607 # way: entity work.cache_ram
609 # ROW_BITS => ROW_BITS,
610 # WIDTH => ROW_SIZE_BITS
615 # rd_addr => rd_addr,
618 # wr_addr => wr_addr,
619 # wr_data => wishbone_in.dat
623 # do_read <= not (stall_in or use_previous);
625 # if wishbone_in.ack = '1' and replace_way = i then
628 # cache_out(i) <= dout;
630 # std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
632 # std_ulogic_vector(to_unsigned(r.store_row, ROW_BITS));
633 # for i in 0 to ROW_SIZE-1 loop
634 # wr_sel(i) <= do_write;
638 def rams(self
, m
, r
, cache_out
, use_previous
, replace_way
, req_row
):
641 wb_in
, stall_in
= self
.wb_in
, self
.stall_in
644 for i
in range(NUM_WAYS
):
645 do_read
= Signal(name
="do_rd_%d" % i
)
646 do_write
= Signal(name
="do_wr_%d" % i
)
647 rd_addr
= Signal(ROW_BITS
)
648 wr_addr
= Signal(ROW_BITS
)
649 d_out
= Signal(ROW_SIZE_BITS
, name
="d_out_%d" % i
)
650 wr_sel
= Signal(ROW_SIZE
)
652 way
= CacheRam(ROW_BITS
, ROW_SIZE_BITS
, True)
653 setattr(m
.submodules
, "cacheram_%d" % i
, way
)
655 comb
+= way
.rd_en
.eq(do_read
)
656 comb
+= way
.rd_addr
.eq(rd_addr
)
657 comb
+= d_out
.eq(way
.rd_data_o
)
658 comb
+= way
.wr_sel
.eq(wr_sel
)
659 comb
+= way
.wr_addr
.eq(wr_addr
)
660 comb
+= way
.wr_data
.eq(wb_in
.dat
)
662 comb
+= do_read
.eq(~
(stall_in | use_previous
))
664 with m
.If(wb_in
.ack
& (replace_way
== i
)):
665 comb
+= do_write
.eq(1)
667 comb
+= cache_out
[i
].eq(d_out
)
668 comb
+= rd_addr
.eq(req_row
)
669 comb
+= wr_addr
.eq(r
.store_row
)
670 for j
in range(ROW_SIZE
):
671 comb
+= wr_sel
[j
].eq(do_write
)
674 # maybe_plrus: if NUM_WAYS > 1 generate
676 # plrus: for i in 0 to NUM_LINES-1 generate
678 # signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
679 # signal plru_acc_en : std_ulogic;
680 # signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
683 # plru : entity work.plru
691 # acc_en => plru_acc_en,
698 # if get_index(r.hit_nia) = i then
699 # plru_acc_en <= r.hit_valid;
701 # plru_acc_en <= '0';
704 # std_ulogic_vector(to_unsigned(r.hit_way, WAY_BITS));
705 # plru_victim(i) <= plru_out;
709 def maybe_plrus(self
, m
, r
, plru_victim
):
712 with m
.If(NUM_WAYS
> 1):
713 for i
in range(NUM_LINES
):
714 plru_acc_i
= Signal(WAY_BITS
)
715 plru_acc_en
= Signal()
716 plru_out
= Signal(WAY_BITS
)
717 plru
= PLRU(WAY_BITS
)
718 comb
+= plru
.acc_i
.eq(plru_acc_i
)
719 comb
+= plru
.acc_en
.eq(plru_acc_en
)
720 comb
+= plru
.lru_o
.eq(plru_out
)
723 with m
.If(get_index(r
.hit_nia
) == i
):
724 comb
+= plru
.acc_en
.eq(r
.hit_valid
)
726 comb
+= plru
.acc_i
.eq(r
.hit_way
)
727 comb
+= plru_victim
[i
].eq(plru
.lru_o
)
729 # -- TLB hit detection and real address generation
730 # itlb_lookup : process(all)
731 # variable pte : tlb_pte_t;
732 # variable ttag : tlb_tag_t;
734 # tlb_req_index <= hash_ea(i_in.nia);
735 # pte := itlb_ptes(tlb_req_index);
736 # ttag := itlb_tags(tlb_req_index);
737 # if i_in.virt_mode = '1' then
738 # real_addr <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
739 # i_in.nia(TLB_LG_PGSZ - 1 downto 0);
740 # if ttag = i_in.nia(63 downto TLB_LG_PGSZ + TLB_BITS) then
741 # ra_valid <= itlb_valids(tlb_req_index);
745 # eaa_priv <= pte(3);
747 # real_addr <= i_in.nia(REAL_ADDR_BITS - 1 downto 0);
752 # -- no IAMR, so no KUEP support for now
753 # priv_fault <= eaa_priv and not i_in.priv_mode;
754 # access_ok <= ra_valid and not priv_fault;
756 # TLB hit detection and real address generation
757 def itlb_lookup(self
, m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
758 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
759 priv_fault
, access_ok
):
764 pte
= Signal(TLB_PTE_BITS
)
765 ttag
= Signal(TLB_EA_TAG_BITS
)
767 comb
+= tlb_req_index
.eq(hash_ea(i_in
.nia
))
768 comb
+= pte
.eq(itlb_ptes
[tlb_req_index
])
769 comb
+= ttag
.eq(itlb_tags
[tlb_req_index
])
771 with m
.If(i_in
.virt_mode
):
772 comb
+= real_addr
.eq(Cat(
773 i_in
.nia
[:TLB_LG_PGSZ
],
774 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
777 with m
.If(ttag
== i_in
.nia
[TLB_LG_PGSZ
+ TLB_BITS
:64]):
778 comb
+= ra_valid
.eq(itlb_valid_bits
[tlb_req_index
])
780 comb
+= eaa_priv
.eq(pte
[3])
783 comb
+= real_addr
.eq(i_in
.nia
[:REAL_ADDR_BITS
])
784 comb
+= ra_valid
.eq(1)
785 comb
+= eaa_priv
.eq(1)
787 # No IAMR, so no KUEP support for now
788 comb
+= priv_fault
.eq(eaa_priv
& ~i_in
.priv_mode
)
789 comb
+= access_ok
.eq(ra_valid
& ~priv_fault
)
792 # itlb_update: process(clk)
793 # variable wr_index : tlb_index_t;
795 # if rising_edge(clk) then
796 # wr_index := hash_ea(m_in.addr);
798 # (m_in.tlbie = '1' and m_in.doall = '1') then
799 # -- clear all valid bits
800 # for i in tlb_index_t loop
801 # itlb_valids(i) <= '0';
803 # elsif m_in.tlbie = '1' then
804 # -- clear entry regardless of hit or miss
805 # itlb_valids(wr_index) <= '0';
806 # elsif m_in.tlbld = '1' then
807 # itlb_tags(wr_index) <=
808 # m_in.addr(63 downto TLB_LG_PGSZ + TLB_BITS);
809 # itlb_ptes(wr_index) <= m_in.pte;
810 # itlb_valids(wr_index) <= '1';
815 def itlb_update(self
, m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
):
821 wr_index
= Signal(TLB_SIZE
)
822 sync
+= wr_index
.eq(hash_ea(m_in
.addr
))
824 with m
.If(m_in
.tlbie
& m_in
.doall
):
825 # Clear all valid bits
826 for i
in range(TLB_SIZE
):
827 sync
+= itlb_valid_bits
[i
].eq(0)
829 with m
.Elif(m_in
.tlbie
):
830 # Clear entry regardless of hit or miss
831 sync
+= itlb_valid_bits
[wr_index
].eq(0)
833 with m
.Elif(m_in
.tlbld
):
834 sync
+= itlb_tags
[wr_index
].eq(
835 m_in
.addr
[TLB_LG_PGSZ
+ TLB_BITS
:64]
837 sync
+= itlb_ptes
[wr_index
].eq(m_in
.pte
)
838 sync
+= itlb_valid_bits
[wr_index
].eq(1)
840 # -- Cache hit detection, output to fetch2 and other misc logic
841 # icache_comb : process(all)
842 # Cache hit detection, output to fetch2 and other misc logic
843 def icache_comb(self
, m
, use_previous
, r
, req_index
, req_row
,
844 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
845 cache_tags
, access_ok
, req_is_hit
,
846 req_is_miss
, replace_way
, plru_victim
, cache_out
):
847 # variable is_hit : std_ulogic;
848 # variable hit_way : way_t;
851 #comb += Display("ENTER icache_comb - use_previous:%x req_index:%x " \
852 # "req_row:%x req_tag:%x real_addr:%x req_laddr:%x " \
853 # "access_ok:%x req_is_hit:%x req_is_miss:%x " \
854 # "replace_way:%x", use_previous, req_index, req_row, \
855 # req_tag, real_addr, req_laddr, access_ok, \
856 # req_is_hit, req_is_miss, replace_way)
858 i_in
, i_out
, wb_out
= self
.i_in
, self
.i_out
, self
.wb_out
859 flush_in
, stall_out
= self
.flush_in
, self
.stall_out
862 hit_way
= Signal(NUM_WAYS
)
864 # -- i_in.sequential means that i_in.nia this cycle
865 # -- is 4 more than last cycle. If we read more
866 # -- than 32 bits at a time, had a cache hit last
867 # -- cycle, and we don't want the first 32-bit chunk
868 # -- then we can keep the data we read last cycle
869 # -- and just use that.
870 # if unsigned(i_in.nia(INSN_BITS+2-1 downto 2)) /= 0 then
871 # use_previous <= i_in.sequential and r.hit_valid;
873 # use_previous <= '0';
875 # i_in.sequential means that i_in.nia this cycle is 4 more than
876 # last cycle. If we read more than 32 bits at a time, had a
877 # cache hit last cycle, and we don't want the first 32-bit chunk
878 # then we can keep the data we read last cycle and just use that.
879 with m
.If(i_in
.nia
[2:INSN_BITS
+2] != 0):
880 comb
+= use_previous
.eq(i_in
.sequential
& r
.hit_valid
)
882 # -- Extract line, row and tag from request
883 # req_index <= get_index(i_in.nia);
884 # req_row <= get_row(i_in.nia);
885 # req_tag <= get_tag(real_addr);
886 # Extract line, row and tag from request
887 comb
+= req_index
.eq(get_index(i_in
.nia
))
888 comb
+= req_row
.eq(get_row(i_in
.nia
))
889 comb
+= req_tag
.eq(get_tag(real_addr
))
891 # -- Calculate address of beginning of cache row, will be
892 # -- used for cache miss processing if needed
894 # (63 downto REAL_ADDR_BITS => '0') &
895 # real_addr(REAL_ADDR_BITS - 1 downto ROW_OFF_BITS) &
896 # (ROW_OFF_BITS-1 downto 0 => '0');
897 # Calculate address of beginning of cache row, will be
898 # used for cache miss processing if needed
899 comb
+= req_laddr
.eq(Cat(
900 Const(0b0, ROW_OFF_BITS
),
901 real_addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
],
905 # -- Test if pending request is a hit on any way
908 # for i in way_t loop
909 # if i_in.req = '1' and
910 # (cache_valids(req_index)(i) = '1' or
911 # (r.state = WAIT_ACK and
912 # req_index = r.store_index and
913 # i = r.store_way and
914 # r.rows_valid(req_row mod ROW_PER_LINE) = '1')) then
915 # if read_tag(i, cache_tags(req_index)) = req_tag then
921 # Test if pending request is a hit on any way
922 for i
in range(NUM_WAYS
):
924 (cache_valid_bits
[req_index
][i
] |
925 ((r
.state
== State
.WAIT_ACK
)
926 & (req_index
== r
.store_index
)
928 & r
.rows_valid
[req_row
% ROW_PER_LINE
]))):
929 with m
.If(read_tag(i
, cache_tags
[req_index
]) == req_tag
):
930 comb
+= hit_way
.eq(i
)
933 # -- Generate the "hit" and "miss" signals
934 # -- for the synchronous blocks
935 # if i_in.req = '1' and access_ok = '1' and flush_in = '0'
937 # req_is_hit <= is_hit;
938 # req_is_miss <= not is_hit;
941 # req_is_miss <= '0';
943 # req_hit_way <= hit_way;
944 # Generate the "hit" and "miss" signals
945 # for the synchronous blocks
946 with m
.If(i_in
.req
& access_ok
& ~flush_in
):
947 comb
+= req_is_hit
.eq(is_hit
)
948 comb
+= req_is_miss
.eq(~is_hit
)
951 comb
+= req_is_hit
.eq(0)
952 comb
+= req_is_miss
.eq(0)
954 # -- The way to replace on a miss
955 # if r.state = CLR_TAG then
957 # to_integer(unsigned(plru_victim(r.store_index)));
959 # replace_way <= r.store_way;
961 # The way to replace on a miss
962 with m
.If(r
.state
== State
.CLR_TAG
):
963 comb
+= replace_way
.eq(plru_victim
[r
.store_index
])
966 comb
+= replace_way
.eq(r
.store_way
)
968 # -- Output instruction from current cache row
970 # -- Note: This is a mild violation of our design principle of
971 # -- having pipeline stages output from a clean latch. In this
972 # -- case we output the result of a mux. The alternative would
973 # -- be output an entire row which I prefer not to do just yet
974 # -- as it would force fetch2 to know about some of the cache
975 # -- geometry information.
976 # i_out.insn <= read_insn_word(r.hit_nia, cache_out(r.hit_way));
977 # i_out.valid <= r.hit_valid;
978 # i_out.nia <= r.hit_nia;
979 # i_out.stop_mark <= r.hit_smark;
980 # i_out.fetch_failed <= r.fetch_failed;
981 # Output instruction from current cache row
983 # Note: This is a mild violation of our design principle of
984 # having pipeline stages output from a clean latch. In this
985 # case we output the result of a mux. The alternative would
986 # be output an entire row which I prefer not to do just yet
987 # as it would force fetch2 to know about some of the cache
988 # geometry information.
989 #comb += Display("BEFORE read_insn_word - r.hit_nia:%x " \
990 # "r.hit_way:%x, cache_out[r.hit_way]:%x", r.hit_nia, \
991 # r.hit_way, cache_out[r.hit_way])
992 comb
+= i_out
.insn
.eq(read_insn_word(r
.hit_nia
, cache_out
[r
.hit_way
]))
993 comb
+= i_out
.valid
.eq(r
.hit_valid
)
994 comb
+= i_out
.nia
.eq(r
.hit_nia
)
995 comb
+= i_out
.stop_mark
.eq(r
.hit_smark
)
996 comb
+= i_out
.fetch_failed
.eq(r
.fetch_failed
)
998 # -- Stall fetch1 if we have a miss on cache or TLB
999 # -- or a protection fault
1000 # stall_out <= not (is_hit and access_ok);
1001 # Stall fetch1 if we have a miss on cache or TLB
1002 # or a protection fault
1003 comb
+= stall_out
.eq(~
(is_hit
& access_ok
))
1005 # -- Wishbone requests output (from the cache miss reload machine)
1006 # wishbone_out <= r.wb;
1007 # Wishbone requests output (from the cache miss reload machine)
1008 comb
+= wb_out
.eq(r
.wb
)
1011 # -- Cache hit synchronous machine
1012 # icache_hit : process(clk)
1013 # Cache hit synchronous machine
1014 def icache_hit(self
, m
, use_previous
, r
, req_is_hit
, req_hit_way
,
1015 req_index
, req_tag
, real_addr
):
1018 i_in
, stall_in
= self
.i_in
, self
.stall_in
1019 flush_in
= self
.flush_in
1022 # if rising_edge(clk) then
1023 # -- keep outputs to fetch2 unchanged on a stall
1024 # -- except that flush or reset sets valid to 0
1025 # -- If use_previous, keep the same data as last
1026 # -- cycle and use the second half
1027 # if stall_in = '1' or use_previous = '1' then
1028 # if rst = '1' or flush_in = '1' then
1029 # r.hit_valid <= '0';
1031 # keep outputs to fetch2 unchanged on a stall
1032 # except that flush or reset sets valid to 0
1033 # If use_previous, keep the same data as last
1034 # cycle and use the second half
1035 with m
.If(stall_in | use_previous
):
1036 with m
.If(flush_in
):
1037 sync
+= r
.hit_valid
.eq(0)
1039 # -- On a hit, latch the request for the next cycle,
1040 # -- when the BRAM data will be available on the
1041 # -- cache_out output of the corresponding way
1042 # r.hit_valid <= req_is_hit;
1043 # if req_is_hit = '1' then
1044 # r.hit_way <= req_hit_way;
1046 # On a hit, latch the request for the next cycle,
1047 # when the BRAM data will be available on the
1048 # cache_out output of the corresponding way
1049 sync
+= r
.hit_valid
.eq(req_is_hit
)
1051 with m
.If(req_is_hit
):
1052 sync
+= r
.hit_way
.eq(req_hit_way
)
1054 # report "cache hit nia:" & to_hstring(i_in.nia) &
1055 # " IR:" & std_ulogic'image(i_in.virt_mode) &
1056 # " SM:" & std_ulogic'image(i_in.stop_mark) &
1057 # " idx:" & integer'image(req_index) &
1058 # " tag:" & to_hstring(req_tag) &
1059 # " way:" & integer'image(req_hit_way) &
1060 # " RA:" & to_hstring(real_addr);
1061 sync
+= Display("cache hit nia:%x IR:%x SM:%x idx:%x " \
1062 "tag:%x way:%x RA:%x", i_in
.nia
, \
1063 i_in
.virt_mode
, i_in
.stop_mark
, req_index
, \
1064 req_tag
, req_hit_way
, real_addr
)
1070 # if stall_in = '0' then
1071 # -- Send stop marks and NIA down regardless of validity
1072 # r.hit_smark <= i_in.stop_mark;
1073 # r.hit_nia <= i_in.nia;
1075 with m
.If(~stall_in
):
1076 # Send stop marks and NIA down regardless of validity
1077 sync
+= r
.hit_smark
.eq(i_in
.stop_mark
)
1078 sync
+= r
.hit_nia
.eq(i_in
.nia
)
1082 # -- Cache miss/reload synchronous machine
1083 # icache_miss : process(clk)
1084 # Cache miss/reload synchronous machine
1085 def icache_miss(self
, m
, cache_valid_bits
, r
, req_is_miss
,
1086 req_index
, req_laddr
, req_tag
, replace_way
,
1087 cache_tags
, access_ok
, real_addr
):
1091 i_in
, wb_in
, m_in
= self
.i_in
, self
.wb_in
, self
.m_in
1092 stall_in
, flush_in
= self
.stall_in
, self
.flush_in
1093 inval_in
= self
.inval_in
1095 # variable tagset : cache_tags_set_t;
1096 # variable stbs_done : boolean;
1098 tagset
= Signal(TAG_RAM_WIDTH
)
1099 stbs_done
= Signal()
1102 # if rising_edge(clk) then
1103 # -- On reset, clear all valid bits to force misses
1105 # On reset, clear all valid bits to force misses
1106 # for i in index_t loop
1107 # cache_valids(i) <= (others => '0');
1112 # -- We only ever do reads on wishbone
1113 # r.wb.dat <= (others => '0');
1114 # r.wb.sel <= "11111111";
1117 # -- Not useful normally but helps avoiding
1118 # -- tons of sim warnings
1119 # r.wb.adr <= (others => '0');
1123 # -- Process cache invalidations
1124 # if inval_in = '1' then
1125 # for i in index_t loop
1126 # cache_valids(i) <= (others => '0');
1128 # r.store_valid <= '0';
1130 comb
+= r
.wb
.sel
.eq(-1)
1131 comb
+= r
.wb
.adr
.eq(r
.req_adr
[3:])
1133 # Process cache invalidations
1134 with m
.If(inval_in
):
1135 for i
in range(NUM_LINES
):
1136 sync
+= cache_valid_bits
[i
].eq(0)
1137 sync
+= r
.store_valid
.eq(0)
1139 # -- Main state machine
1141 # Main state machine
1142 with m
.Switch(r
.state
):
1145 with m
.Case(State
.IDLE
):
1146 # -- Reset per-row valid flags,
1147 # -- only used in WAIT_ACK
1148 # for i in 0 to ROW_PER_LINE - 1 loop
1149 # r.rows_valid(i) <= '0';
1151 # Reset per-row valid flags,
1152 # only used in WAIT_ACK
1153 for i
in range(ROW_PER_LINE
):
1154 sync
+= r
.rows_valid
[i
].eq(0)
1156 # -- We need to read a cache line
1157 # if req_is_miss = '1' then
1158 # report "cache miss nia:" & to_hstring(i_in.nia) &
1159 # " IR:" & std_ulogic'image(i_in.virt_mode) &
1160 # " SM:" & std_ulogic'image(i_in.stop_mark) &
1161 # " idx:" & integer'image(req_index) &
1162 # " way:" & integer'image(replace_way) &
1163 # " tag:" & to_hstring(req_tag) &
1164 # " RA:" & to_hstring(real_addr);
1165 # We need to read a cache line
1166 with m
.If(req_is_miss
):
1168 "cache miss nia:%x IR:%x SM:%x idx:%x " \
1169 " way:%x tag:%x RA:%x", i_in
.nia
, \
1170 i_in
.virt_mode
, i_in
.stop_mark
, req_index
, \
1171 replace_way
, req_tag
, real_addr
)
1173 # -- Keep track of our index and way for
1174 # -- subsequent stores
1175 # r.store_index <= req_index;
1176 # r.store_row <= get_row(req_laddr);
1177 # r.store_tag <= req_tag;
1178 # r.store_valid <= '1';
1180 # get_row_of_line(get_row(req_laddr)) - 1;
1181 # Keep track of our index and way
1182 # for subsequent stores
1183 sync
+= r
.store_index
.eq(req_index
)
1184 sync
+= r
.store_row
.eq(get_row(req_laddr
))
1185 sync
+= r
.store_tag
.eq(req_tag
)
1186 sync
+= r
.store_valid
.eq(1)
1187 sync
+= r
.end_row_ix
.eq(
1193 # -- Prep for first wishbone read. We calculate the
1194 # -- address of the start of the cache line and
1195 # -- start the WB cycle.
1196 # r.wb.adr <= req_laddr(r.wb.adr'left downto 0);
1199 # Prep for first wishbone read.
1201 # address of the start of the cache line and
1202 # start the WB cycle.
1203 sync
+= r
.req_adr
.eq(req_laddr
)
1204 sync
+= r
.wb
.cyc
.eq(1)
1205 sync
+= r
.wb
.stb
.eq(1)
1207 # -- Track that we had one request sent
1208 # r.state <= CLR_TAG;
1209 # Track that we had one request sent
1210 sync
+= r
.state
.eq(State
.CLR_TAG
)
1213 # when CLR_TAG | WAIT_ACK =>
1214 with m
.Case(State
.CLR_TAG
, State
.WAIT_ACK
):
1215 # if r.state = CLR_TAG then
1216 with m
.If(r
.state
== State
.CLR_TAG
):
1217 # -- Get victim way from plru
1218 # r.store_way <= replace_way;
1219 # Get victim way from plru
1220 sync
+= r
.store_way
.eq(replace_way
)
1222 # -- Force misses on that way while
1223 # -- reloading that line
1224 # cache_valids(req_index)(replace_way) <= '0';
1225 # Force misses on that way while
1226 # realoading that line
1227 cv
= Signal(INDEX_BITS
)
1228 comb
+= cv
.eq(cache_valid_bits
[req_index
])
1229 comb
+= cv
.bit_select(replace_way
, 1).eq(0)
1230 sync
+= cache_valid_bits
[req_index
].eq(cv
)
1232 # -- Store new tag in selected way
1233 # for i in 0 to NUM_WAYS-1 loop
1234 # if i = replace_way then
1235 # tagset := cache_tags(r.store_index);
1236 # write_tag(i, tagset, r.store_tag);
1237 # cache_tags(r.store_index) <= tagset;
1240 for i
in range(NUM_WAYS
):
1241 with m
.If(i
== replace_way
):
1242 comb
+= tagset
.eq(cache_tags
[r
.store_index
])
1243 comb
+= write_tag(i
, tagset
, r
.store_tag
)
1244 sync
+= cache_tags
[r
.store_index
].eq(tagset
)
1246 # r.state <= WAIT_ACK;
1247 sync
+= r
.state
.eq(State
.WAIT_ACK
)
1250 # -- Requests are all sent if stb is 0
1251 # stbs_done := r.wb.stb = '0';
1252 # Requests are all sent if stb is 0
1253 stbs_zero
= Signal()
1254 comb
+= stbs_zero
.eq(r
.wb
.stb
== 0)
1255 comb
+= stbs_done
.eq(stbs_zero
)
1257 # -- If we are still sending requests,
1258 # -- was one accepted ?
1259 # if wishbone_in.stall = '0' and not stbs_done then
1260 # If we are still sending requests,
1262 with m
.If(~wb_in
.stall
& ~stbs_zero
):
1263 # -- That was the last word ? We are done sending.
1264 # -- Clear stb and set stbs_done so we can handle
1265 # -- an eventual last ack on the same cycle.
1266 # if is_last_row_addr(r.wb.adr, r.end_row_ix) then
1268 # stbs_done := true;
1270 # That was the last word ?
1271 # We are done sending.
1272 # Clear stb and set stbs_done
1274 # an eventual last ack on
1276 with m
.If(is_last_row_addr(r
.req_adr
, r
.end_row_ix
)):
1277 sync
+= Display("IS_LAST_ROW_ADDR " \
1278 "r.wb.addr:%x r.end_row_ix:%x " \
1279 "r.wb.stb:%x stbs_zero:%x " \
1280 "stbs_done:%x", r
.wb
.adr
, \
1281 r
.end_row_ix
, r
.wb
.stb
, \
1282 stbs_zero
, stbs_done
)
1283 sync
+= r
.wb
.stb
.eq(0)
1284 comb
+= stbs_done
.eq(1)
1286 # -- Calculate the next row address
1287 # r.wb.adr <= next_row_addr(r.wb.adr);
1288 # Calculate the next row address
1289 rarange
= Signal(LINE_OFF_BITS
- ROW_OFF_BITS
)
1291 r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
] + 1
1293 sync
+= r
.req_adr
[ROW_OFF_BITS
:LINE_OFF_BITS
].eq(
1296 sync
+= Display("RARANGE r.wb.adr:%x stbs_zero:%x " \
1297 "stbs_done:%x", rarange
, stbs_zero
, \
1301 # -- Incoming acks processing
1302 # if wishbone_in.ack = '1' then
1303 # Incoming acks processing
1304 with m
.If(wb_in
.ack
):
1305 # r.rows_valid(r.store_row mod ROW_PER_LINE)
1307 sync
+= Display("WB_IN_ACK stbs_zero:%x " \
1309 stbs_zero
, stbs_done
)
1311 sync
+= r
.rows_valid
[r
.store_row
% ROW_PER_LINE
].eq(1)
1313 # -- Check for completion
1315 # is_last_row(r.store_row, r.end_row_ix) then
1316 # Check for completion
1317 with m
.If(stbs_done
&
1318 is_last_row(r
.store_row
, r
.end_row_ix
)):
1319 # -- Complete wishbone cycle
1321 # Complete wishbone cycle
1322 sync
+= r
.wb
.cyc
.eq(0)
1324 # -- Cache line is now valid
1325 # cache_valids(r.store_index)(replace_way) <=
1326 # r.store_valid and not inval_in;
1327 # Cache line is now valid
1328 cv
= Signal(INDEX_BITS
)
1329 comb
+= cv
.eq(cache_valid_bits
[r
.store_index
])
1330 comb
+= cv
.bit_select(replace_way
, 1).eq(
1331 r
.store_valid
& ~inval_in
1333 sync
+= cache_valid_bits
[r
.store_index
].eq(cv
)
1338 sync
+= r
.state
.eq(State
.IDLE
)
1341 # -- Increment store row counter
1342 # r.store_row <= next_row(r.store_row);
1343 # Increment store row counter
1344 sync
+= r
.store_row
.eq(next_row(r
.store_row
))
1349 # -- TLB miss and protection fault processing
1350 # if rst = '1' or flush_in = '1' or m_in.tlbld = '1' then
1351 # r.fetch_failed <= '0';
1352 # elsif i_in.req = '1' and access_ok = '0' and
1353 # stall_in = '0' then
1354 # r.fetch_failed <= '1';
1356 # TLB miss and protection fault processing
1357 with m
.If(flush_in | m_in
.tlbld
):
1358 sync
+= r
.fetch_failed
.eq(0)
1360 with m
.Elif(i_in
.req
& ~access_ok
& ~stall_in
):
1361 sync
+= r
.fetch_failed
.eq(1)
1365 # icache_log: if LOG_LENGTH > 0 generate
1366 def icache_log(self
, m
, req_hit_way
, ra_valid
, access_ok
,
1367 req_is_miss
, req_is_hit
, lway
, wstate
, r
):
1371 wb_in
, i_out
= self
.wb_in
, self
.i_out
1372 log_out
, stall_out
= self
.log_out
, self
.stall_out
1374 # -- Output data to logger
1375 # signal log_data : std_ulogic_vector(53 downto 0);
1377 # data_log: process(clk)
1378 # variable lway: way_t;
1379 # variable wstate: std_ulogic;
1380 # Output data to logger
1381 for i
in range(LOG_LENGTH
):
1382 # Output data to logger
1383 log_data
= Signal(54)
1384 lway
= Signal(NUM_WAYS
)
1388 # if rising_edge(clk) then
1389 # lway := req_hit_way;
1391 sync
+= lway
.eq(req_hit_way
)
1392 sync
+= wstate
.eq(0)
1394 # if r.state /= IDLE then
1397 with m
.If(r
.state
!= State
.IDLE
):
1398 sync
+= wstate
.eq(1)
1400 # log_data <= i_out.valid &
1403 # r.wb.adr(5 downto 3) &
1404 # r.wb.stb & r.wb.cyc &
1405 # wishbone_in.stall &
1408 # r.hit_nia(5 downto 2) &
1410 # std_ulogic_vector(to_unsigned(lway, 3)) &
1411 # req_is_hit & req_is_miss &
1414 sync
+= log_data
.eq(Cat(
1415 ra_valid
, access_ok
, req_is_miss
, req_is_hit
,
1416 lway
, wstate
, r
.hit_nia
[2:6],
1417 r
.fetch_failed
, stall_out
, wb_in
.stall
, r
.wb
.cyc
,
1418 r
.wb
.stb
, r
.wb
.adr
[3:6], wb_in
.ack
, i_out
.insn
,
1423 # log_out <= log_data;
1424 comb
+= log_out
.eq(log_data
)
1428 def elaborate(self
, platform
):
1433 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1434 cache_tags
= CacheTagArray()
1435 cache_valid_bits
= CacheValidBitsArray()
1437 # signal itlb_valids : tlb_valids_t;
1438 # signal itlb_tags : tlb_tags_t;
1439 # signal itlb_ptes : tlb_ptes_t;
1440 # attribute ram_style of itlb_tags : signal is "distributed";
1441 # attribute ram_style of itlb_ptes : signal is "distributed";
1442 itlb_valid_bits
= TLBValidBitsArray()
1443 itlb_tags
= TLBTagArray()
1444 itlb_ptes
= TLBPtesArray()
1445 # TODO to be passed to nmigen as ram attributes
1446 # attribute ram_style of itlb_tags : signal is "distributed";
1447 # attribute ram_style of itlb_ptes : signal is "distributed";
1449 # -- Privilege bit from PTE EAA field
1450 # signal eaa_priv : std_ulogic;
1451 # Privilege bit from PTE EAA field
1454 # signal r : reg_internal_t;
1457 # -- Async signals on incoming request
1458 # signal req_index : index_t;
1459 # signal req_row : row_t;
1460 # signal req_hit_way : way_t;
1461 # signal req_tag : cache_tag_t;
1462 # signal req_is_hit : std_ulogic;
1463 # signal req_is_miss : std_ulogic;
1464 # signal req_laddr : std_ulogic_vector(63 downto 0);
1465 # Async signal on incoming request
1466 req_index
= Signal(NUM_LINES
)
1467 req_row
= Signal(BRAM_ROWS
)
1468 req_hit_way
= Signal(NUM_WAYS
)
1469 req_tag
= Signal(TAG_BITS
)
1470 req_is_hit
= Signal()
1471 req_is_miss
= Signal()
1472 req_laddr
= Signal(64)
1474 # signal tlb_req_index : tlb_index_t;
1475 # signal real_addr : std_ulogic_vector(
1476 # REAL_ADDR_BITS - 1 downto 0
1478 # signal ra_valid : std_ulogic;
1479 # signal priv_fault : std_ulogic;
1480 # signal access_ok : std_ulogic;
1481 # signal use_previous : std_ulogic;
1482 tlb_req_index
= Signal(TLB_SIZE
)
1483 real_addr
= Signal(REAL_ADDR_BITS
)
1485 priv_fault
= Signal()
1486 access_ok
= Signal()
1487 use_previous
= Signal()
1489 # signal cache_out : cache_ram_out_t;
1490 cache_out
= CacheRamOut()
1492 # signal plru_victim : plru_out_t;
1493 # signal replace_way : way_t;
1494 plru_victim
= PLRUOut()
1495 replace_way
= Signal(NUM_WAYS
)
1497 # call sub-functions putting everything together, using shared
1498 # signals established above
1499 self
.rams(m
, r
, cache_out
, use_previous
, replace_way
, req_row
)
1500 self
.maybe_plrus(m
, r
, plru_victim
)
1501 self
.itlb_lookup(m
, tlb_req_index
, itlb_ptes
, itlb_tags
,
1502 real_addr
, itlb_valid_bits
, ra_valid
, eaa_priv
,
1503 priv_fault
, access_ok
)
1504 self
.itlb_update(m
, itlb_valid_bits
, itlb_tags
, itlb_ptes
)
1505 self
.icache_comb(m
, use_previous
, r
, req_index
, req_row
,
1506 req_tag
, real_addr
, req_laddr
, cache_valid_bits
,
1507 cache_tags
, access_ok
, req_is_hit
, req_is_miss
,
1508 replace_way
, plru_victim
, cache_out
)
1509 self
.icache_hit(m
, use_previous
, r
, req_is_hit
, req_hit_way
,
1510 req_index
, req_tag
, real_addr
)
1511 self
.icache_miss(m
, cache_valid_bits
, r
, req_is_miss
, req_index
,
1512 req_laddr
, req_tag
, replace_way
, cache_tags
,
1513 access_ok
, real_addr
)
1514 #self.icache_log(m, log_out, req_hit_way, ra_valid, access_ok,
1515 # req_is_miss, req_is_hit, lway, wstate, r)
1523 # use ieee.std_logic_1164.all;
1526 # use work.common.all;
1527 # use work.wishbone_types.all;
1529 # entity icache_tb is
1532 # architecture behave of icache_tb is
1533 # signal clk : std_ulogic;
1534 # signal rst : std_ulogic;
1536 # signal i_out : Fetch1ToIcacheType;
1537 # signal i_in : IcacheToDecode1Type;
1539 # signal m_out : MmuToIcacheType;
1541 # signal wb_bram_in : wishbone_master_out;
1542 # signal wb_bram_out : wishbone_slave_out;
1544 # constant clk_period : time := 10 ns;
1546 # icache0: entity work.icache
1560 # wishbone_out => wb_bram_in,
1561 # wishbone_in => wb_bram_out
1564 # -- BRAM Memory slave
1565 # bram0: entity work.wishbone_bram_wrapper
1567 # MEMORY_SIZE => 1024,
1568 # RAM_INIT_FILE => "icache_test.bin"
1573 # wishbone_in => wb_bram_in,
1574 # wishbone_out => wb_bram_out
1577 # clk_process: process
1580 # wait for clk_period/2;
1582 # wait for clk_period/2;
1585 # rst_process: process
1588 # wait for 2*clk_period;
1596 # i_out.nia <= (others => '0');
1597 # i_out.stop_mark <= '0';
1599 # m_out.tlbld <= '0';
1600 # m_out.tlbie <= '0';
1601 # m_out.addr <= (others => '0');
1602 # m_out.pte <= (others => '0');
1604 # wait until rising_edge(clk);
1605 # wait until rising_edge(clk);
1606 # wait until rising_edge(clk);
1607 # wait until rising_edge(clk);
1610 # i_out.nia <= x"0000000000000004";
1612 # wait for 30*clk_period;
1613 # wait until rising_edge(clk);
1615 # assert i_in.valid = '1' severity failure;
1616 # assert i_in.insn = x"00000001"
1617 # report "insn @" & to_hstring(i_out.nia) &
1618 # "=" & to_hstring(i_in.insn) &
1619 # " expected 00000001"
1624 # wait until rising_edge(clk);
1628 # i_out.nia <= x"0000000000000008";
1629 # wait until rising_edge(clk);
1630 # wait until rising_edge(clk);
1631 # assert i_in.valid = '1' severity failure;
1632 # assert i_in.insn = x"00000002"
1633 # report "insn @" & to_hstring(i_out.nia) &
1634 # "=" & to_hstring(i_in.insn) &
1635 # " expected 00000002"
1637 # wait until rising_edge(clk);
1641 # i_out.nia <= x"0000000000000040";
1643 # wait for 30*clk_period;
1644 # wait until rising_edge(clk);
1646 # assert i_in.valid = '1' severity failure;
1647 # assert i_in.insn = x"00000010"
1648 # report "insn @" & to_hstring(i_out.nia) &
1649 # "=" & to_hstring(i_in.insn) &
1650 # " expected 00000010"
1653 # -- test something that aliases
1655 # i_out.nia <= x"0000000000000100";
1656 # wait until rising_edge(clk);
1657 # wait until rising_edge(clk);
1658 # assert i_in.valid = '0' severity failure;
1659 # wait until rising_edge(clk);
1661 # wait for 30*clk_period;
1662 # wait until rising_edge(clk);
1664 # assert i_in.valid = '1' severity failure;
1665 # assert i_in.insn = x"00000040"
1666 # report "insn @" & to_hstring(i_out.nia) &
1667 # "=" & to_hstring(i_in.insn) &
1668 # " expected 00000040"
1676 def icache_sim(dut
):
1681 yield i_in
.valid
.eq(0)
1682 yield i_out
.priv_mode
.eq(1)
1683 yield i_out
.req
.eq(0)
1684 yield i_out
.nia
.eq(0)
1685 yield i_out
.stop_mark
.eq(0)
1686 yield m_out
.tlbld
.eq(0)
1687 yield m_out
.tlbie
.eq(0)
1688 yield m_out
.addr
.eq(0)
1689 yield m_out
.pte
.eq(0)
1694 yield i_out
.req
.eq(1)
1695 yield i_out
.nia
.eq(Const(0x0000000000000004, 64))
1699 valid
= yield i_in
.valid
1700 nia
= yield i_out
.nia
1701 insn
= yield i_in
.insn
1702 print(f
"valid? {valid}")
1704 assert insn
== 0x00000001, \
1705 "insn @%x=%x expected 00000001" % (nia
, insn
)
1706 yield i_out
.req
.eq(0)
1710 yield i_out
.req
.eq(1)
1711 yield i_out
.nia
.eq(Const(0x0000000000000008, 64))
1714 valid
= yield i_in
.valid
1715 nia
= yield i_in
.nia
1716 insn
= yield i_in
.insn
1718 assert insn
== 0x00000002, \
1719 "insn @%x=%x expected 00000002" % (nia
, insn
)
1723 yield i_out
.req
.eq(1)
1724 yield i_out
.nia
.eq(Const(0x0000000000000040, 64))
1728 valid
= yield i_in
.valid
1729 nia
= yield i_out
.nia
1730 insn
= yield i_in
.insn
1732 assert insn
== 0x00000010, \
1733 "insn @%x=%x expected 00000010" % (nia
, insn
)
1735 # test something that aliases
1736 yield i_out
.req
.eq(1)
1737 yield i_out
.nia
.eq(Const(0x0000000000000100, 64))
1740 valid
= yield i_in
.valid
1745 insn
= yield i_in
.insn
1746 valid
= yield i_in
.valid
1747 insn
= yield i_in
.insn
1749 assert insn
== 0x00000040, \
1750 "insn @%x=%x expected 00000040" % (nia
, insn
)
1751 yield i_out
.req
.eq(0)
1755 def test_icache(mem
):
1758 memory
= Memory(width
=64, depth
=16*64, init
=mem
)
1759 sram
= SRAM(memory
=memory
, granularity
=8)
1763 m
.submodules
.icache
= dut
1764 m
.submodules
.sram
= sram
1766 m
.d
.comb
+= sram
.bus
.cyc
.eq(dut
.wb_out
.cyc
)
1767 m
.d
.comb
+= sram
.bus
.stb
.eq(dut
.wb_out
.stb
)
1768 m
.d
.comb
+= sram
.bus
.we
.eq(dut
.wb_out
.we
)
1769 m
.d
.comb
+= sram
.bus
.sel
.eq(dut
.wb_out
.sel
)
1770 m
.d
.comb
+= sram
.bus
.adr
.eq(dut
.wb_out
.adr
)
1771 m
.d
.comb
+= sram
.bus
.dat_w
.eq(dut
.wb_out
.dat
)
1773 m
.d
.comb
+= dut
.wb_in
.ack
.eq(sram
.bus
.ack
)
1774 m
.d
.comb
+= dut
.wb_in
.dat
.eq(sram
.bus
.dat_r
)
1780 sim
.add_sync_process(wrap(icache_sim(dut
)))
1781 with sim
.write_vcd('test_icache.vcd'):
1784 if __name__
== '__main__':
1786 vl
= rtlil
.convert(dut
, ports
=[])
1787 with
open("test_icache.il", "w") as f
:
1791 for i
in range(512):
1792 mem
.append((i
*2)|
((i
*2+1)<<32))