src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34 from nmutil.util import Display
  35
  36 import unittest
  37
  38
  39 class PortInterface(RecordObject):
  40     """PortInterface
  41
  42     defines the interface - the API - that the LDSTCompUnit connects
  43     to.  note that this is NOT a "fire-and-forget" interface.  the
  44     LDSTCompUnit *must* be kept appraised that the request is in
  45     progress, and only when it has a 100% successful completion
  46     can the notification be given (busy dropped).
  47
  48     The interface FSM rules are as follows:
  49
  50     * if busy_o is asserted, a LD/ST is in progress.  further
  51       requests may not be made until busy_o is deasserted.
  52
  53     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  54       will immediately be asserted and remain asserted.
  55
  56     * addr.ok is to be asserted when the LD/ST address is known.
  57       addr.data is to be valid on the same cycle.
  58
  59       addr.ok and addr.data must REMAIN asserted until busy_o
  60       is de-asserted.  this ensures that there is no need
  61       for the L0 Cache/Buffer to have an additional address latch
  62       (because the LDSTCompUnit already has it)
  63
  64     * addr_ok_o (or exception.happened) must be waited for.  these will
  65       be asserted *only* for one cycle and one cycle only.
  66
  67     * exception.happened will be asserted if there is no chance that the
  68       memory request may be fulfilled.
  69
  70       busy_o is deasserted on the same cycle as exception.happened is asserted.
  71
  72     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  73       HUNDRED PERCENT guarantee that the memory request will be
  74       fulfilled.
  75
  76     * for a LD, ld.ok will be asserted - for only one clock cycle -
  77       at any point in the future that is acceptable to the underlying
  78       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  79
  80       busy_o is deasserted on the same cycle as ld.ok is asserted.
  81
  82     * for a ST, st.ok may be asserted only after addr_ok_o had been
  83       asserted, alongside valid st.data at the same time.  st.ok
  84       must only be asserted for one cycle.
  85
  86       the underlying Memory is REQUIRED to pick up that data and
  87       guarantee its delivery.  no back-acknowledgement is required.
  88
  89       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  90     """
  91
  92     def __init__(self, name=None, regwid=64, addrwid=48):
  93
  94         self._regwid = regwid
  95         self._addrwid = addrwid
  96
  97         RecordObject.__init__(self, name=name)
  98
  99         # distinguish op type (ld/st)
 100         self.is_ld_i    = Signal(reset_less=True)
 101         self.is_st_i    = Signal(reset_less=True)
 102
 103         # LD/ST data length (TODO: other things may be needed)
 104         self.data_len = Signal(4, reset_less=True)
 105
 106         # common signals
 107         self.busy_o = Signal(reset_less=True)     # do not use if busy
 108         self.go_die_i = Signal(reset_less=True)   # back to reset
 109         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 110         # addr is valid (TLB, L1 etc.)
 111         self.addr_ok_o = Signal(reset_less=True)
 112         self.exc_o = LDSTException("exc")
 113         self.dar_o = Signal(64, reset_less=True)
 114
 115         # LD/ST
 116         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 117         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 118
 119         # additional "modes"
 120         self.is_nc         = Signal()  # no cacheing
 121         self.msr_pr        = Signal()  # 1==virtual, 0==privileged
 122         self.is_dcbz_i     = Signal(reset_less=True)
 123
 124         # mmu
 125         self.mmu_done          = Signal() # keep for now
 126
 127         # dcache
 128         self.ldst_error        = Signal()
 129         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 130         self.cache_paradox     = Signal()
 131
 132     def connect_port(self, inport):
 133         print("connect_port", self, inport)
 134         return [self.is_ld_i.eq(inport.is_ld_i),
 135                 self.is_st_i.eq(inport.is_st_i),
 136                 self.is_nc.eq(inport.is_nc),
 137                 self.is_dcbz_i.eq(inport.is_dcbz_i),
 138                 self.data_len.eq(inport.data_len),
 139                 self.go_die_i.eq(inport.go_die_i),
 140                 self.addr.data.eq(inport.addr.data),
 141                 self.addr.ok.eq(inport.addr.ok),
 142                 self.st.eq(inport.st),
 143                 self.msr_pr.eq(inport.msr_pr),
 144                 inport.ld.eq(self.ld),
 145                 inport.busy_o.eq(self.busy_o),
 146                 inport.addr_ok_o.eq(self.addr_ok_o),
 147                 inport.exc_o.eq(self.exc_o),
 148                 inport.dar_o.eq(self.dar_o),
 149                 inport.mmu_done.eq(self.mmu_done),
 150                 inport.ldst_error.eq(self.ldst_error),
 151                 inport.cache_paradox.eq(self.cache_paradox)
 152                 ]
 153
 154
 155 class PortInterfaceBase(Elaboratable):
 156     """PortInterfaceBase
 157
 158     Base class for PortInterface-compliant Memory read/writers
 159     """
 160
 161     def __init__(self, regwid=64, addrwid=4):
 162         self.regwid = regwid
 163         self.addrwid = addrwid
 164         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 165
 166     @property
 167     def addrbits(self):
 168         return log2_int(self.regwid//8)
 169
 170     def splitaddr(self, addr):
 171         """split the address into top and bottom bits of the memory granularity
 172         """
 173         return addr[:self.addrbits], addr[self.addrbits:]
 174
 175     def connect_port(self, inport):
 176         return self.pi.connect_port(inport)
 177
 178     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass
 179     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 180     def set_wr_data(self, m, data, wen): pass
 181     def get_rd_data(self, m): pass
 182
 183     def elaborate(self, platform):
 184         m = Module()
 185         comb, sync = m.d.comb, m.d.sync
 186
 187         # state-machine latches
 188         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 189         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 190         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 191         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 192         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 193         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 194         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 195
 196         self.busy_l = busy_l
 197
 198         sync += st_done.s.eq(0)
 199         comb += st_done.r.eq(0)
 200         comb += st_active.r.eq(0)
 201         comb += ld_active.r.eq(0)
 202         comb += cyc_l.s.eq(0)
 203         comb += cyc_l.r.eq(0)
 204         comb += busy_l.s.eq(0)
 205         comb += busy_l.r.eq(0)
 206         sync += adrok_l.s.eq(0)
 207         comb += adrok_l.r.eq(0)
 208
 209         # expand ld/st binary length/addr[:3] into unary bitmap
 210         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 211
 212         lds = Signal(reset_less=True)
 213         sts = Signal(reset_less=True)
 214         pi = self.pi
 215         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 216         comb += sts.eq(pi.is_st_i)  # st-req signals
 217         pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv
 218
 219         # detect busy "edge"
 220         busy_delay = Signal()
 221         busy_edge = Signal()
 222         sync += busy_delay.eq(pi.busy_o)
 223         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 224
 225         # misalignment detection: bits at end of lenexpand are set.
 226         # when using the L0CacheBuffer "data expander" which splits requests
 227         # into *two* PortInterfaces, this acts as a "safety check".
 228         misalign = Signal()
 229         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 230
 231
 232         # activate mode: only on "edge"
 233         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 234         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 235
 236         # LD/ST requested activates "busy" (only if not already busy)
 237         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 238             comb += busy_l.s.eq(~busy_delay)
 239
 240         # if now in "LD" mode: wait for addr_ok, then send the address out
 241         # to memory, acknowledge address, and send out LD data
 242         with m.If(ld_active.q):
 243             # set up LenExpander with the LD len and lower bits of addr
 244             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 245             comb += lenexp.len_i.eq(pi.data_len)
 246             comb += lenexp.addr_i.eq(lsbaddr)
 247             with m.If(pi.addr.ok & adrok_l.qn):
 248                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 249                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 250                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 251
 252         # if now in "ST" mode: likewise do the same but with "ST"
 253         # to memory, acknowledge address, and send out LD data
 254         with m.If(st_active.q):
 255             # set up LenExpander with the ST len and lower bits of addr
 256             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 257             comb += lenexp.len_i.eq(pi.data_len)
 258             comb += lenexp.addr_i.eq(lsbaddr)
 259             with m.If(pi.addr.ok):
 260                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr,
 261                                  pi.is_dcbz_i)
 262                 with m.If(adrok_l.qn):
 263                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 264                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 265
 266         # for LD mode, when addr has been "ok'd", assume that (because this
 267         # is a "Memory" test-class) the memory read data is valid.
 268         comb += reset_l.s.eq(0)
 269         comb += reset_l.r.eq(0)
 270         lddata = Signal(self.regwid, reset_less=True)
 271         data, ldok = self.get_rd_data(m)
 272         comb += lddata.eq((data & lenexp.rexp_o) >>
 273                           (lenexp.addr_i*8))
 274         with m.If(ld_active.q & adrok_l.q):
 275             # shift data down before pushing out.  requires masking
 276             # from the *byte*-expanded version of LenExpand output
 277             comb += pi.ld.data.eq(lddata)  # put data out
 278             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 279             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 280
 281         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 282         with m.If(st_active.q & pi.st.ok):
 283             # shift data up before storing.  lenexp *bit* version of mask is
 284             # passed straight through as byte-level "write-enable" lines.
 285             stdata = Signal(self.regwid, reset_less=True)
 286             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 287             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 288             # and also handle the ready/stall/busy protocol
 289             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 290             sync += st_done.s.eq(1)     # store done trigger
 291         with m.If(st_done.q):
 292             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 293
 294         # ugly hack, due to simultaneous addr req-go acknowledge
 295         reset_delay = Signal(reset_less=True)
 296         sync += reset_delay.eq(reset_l.q)
 297         with m.If(reset_delay):
 298             comb += adrok_l.r.eq(1)     # address reset
 299
 300         # after waiting one cycle (reset_l is "sync" mode), reset the port
 301         with m.If(reset_l.q):
 302             comb += ld_active.r.eq(1)   # leave the LD active for 1 cycle
 303             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 304             comb += reset_l.r.eq(1)     # clear reset
 305             comb += adrok_l.r.eq(1)     # address reset
 306             comb += st_done.r.eq(1)     # store done reset
 307
 308         # monitor for an exception, clear busy immediately
 309         with m.If(self.pi.exc_o.happened):
 310             comb += busy_l.r.eq(1)
 311
 312         # however ST needs one cycle before busy is reset
 313         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 314         with m.If(reset_l.s):
 315             comb += cyc_l.s.eq(1)
 316
 317         with m.If(cyc_l.q):
 318             comb += cyc_l.r.eq(1)
 319             comb += busy_l.r.eq(1)
 320
 321         # busy latch outputs to interface
 322         comb += pi.busy_o.eq(busy_l.q)
 323
 324         return m
 325
 326     def ports(self):
 327         yield from self.pi.ports()
 328
 329
 330 class TestMemoryPortInterface(PortInterfaceBase):
 331     """TestMemoryPortInterface
 332
 333     This is a test class for simple verification of the LDSTCompUnit
 334     and for the simple core, to be able to run unit tests rapidly and
 335     with less other code in the way.
 336
 337     Versions of this which are *compatible* (conform with PortInterface)
 338     will include augmented-Wishbone Bus versions, including ones that
 339     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 340     possible version that complies with PortInterface".
 341     """
 342
 343     def __init__(self, regwid=64, addrwid=4):
 344         super().__init__(regwid, addrwid)
 345         # hard-code memory addressing width to 6 bits
 346         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 347
 348     def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
 349         lsbaddr, msbaddr = self.splitaddr(addr)
 350         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 351
 352     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 353         lsbaddr, msbaddr = self.splitaddr(addr)
 354         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 355
 356     def set_wr_data(self, m, data, wen):
 357         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 358         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 359         return Const(1, 1)
 360
 361     def get_rd_data(self, m):
 362         return self.mem.rdport.data, Const(1, 1)
 363
 364     def elaborate(self, platform):
 365         m = super().elaborate(platform)
 366
 367         # add TestMemory as submodule
 368         m.submodules.mem = self.mem
 369
 370         return m
 371
 372     def ports(self):
 373         yield from super().ports()
 374         # TODO: memory ports