src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from nmigen.compat.sim import run_simulation, Settle
  14 from nmigen.cli import rtlil
  15 from nmigen import Module
  16
  17 from soc.decoder.power_enums import InternalOp
  18
  19 from soc.experiment.compalu_multi import MultiCompUnit
  20 from soc.experiment.alu_hier import ALU, DummyALU
  21 from soc.fu.alu.alu_input_record import CompALUOpSubset
  22
  23
  24 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
  25     yield dut.issue_i.eq(0)
  26     yield
  27     yield dut.src_i[0].eq(a)
  28     yield dut.src_i[1].eq(b)
  29     yield dut.oper_i.insn_type.eq(op)
  30     yield dut.oper_i.invert_a.eq(inv_a)
  31     yield dut.oper_i.imm_data.imm.eq(imm)
  32     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
  33     yield dut.oper_i.zero_a.eq(zero_a)
  34     yield dut.issue_i.eq(1)
  35     yield
  36     yield dut.issue_i.eq(0)
  37     yield
  38     if not imm_ok or not zero_a:
  39         yield dut.rd.go.eq(0b11)
  40         while True:
  41             yield
  42             rd_rel_o = yield dut.rd.rel
  43             print ("rd_rel", rd_rel_o)
  44             if rd_rel_o:
  45                 break
  46         yield dut.rd.go.eq(0)
  47     if len(dut.src_i) == 3:
  48         yield dut.rd.go.eq(0b100)
  49         while True:
  50             yield
  51             rd_rel_o = yield dut.rd.rel
  52             print ("rd_rel", rd_rel_o)
  53             if rd_rel_o:
  54                 break
  55         yield dut.rd.go.eq(0)
  56
  57     req_rel_o = yield dut.wr.rel
  58     result = yield dut.data_o
  59     print ("req_rel", req_rel_o, result)
  60     while True:
  61         req_rel_o = yield dut.wr.rel
  62         result = yield dut.data_o
  63         print ("req_rel", req_rel_o, result)
  64         if req_rel_o:
  65             break
  66         yield
  67     yield dut.wr.go[0].eq(1)
  68     yield Settle()
  69     result = yield dut.data_o
  70     yield
  71     print ("result", result)
  72     yield dut.wr.go[0].eq(0)
  73     yield
  74     return result
  75
  76
  77 def scoreboard_sim_dummy(dut):
  78     result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
  79                                     imm=8, imm_ok=1)
  80     assert result == 5, result
  81
  82     result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
  83                                     imm=8, imm_ok=1)
  84     assert result == 9, result
  85
  86
  87 def scoreboard_sim(dut):
  88     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
  89                                     imm=8, imm_ok=1)
  90     assert result == 13
  91
  92     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
  93     assert result == 7
  94
  95     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
  96     assert result == 65532
  97
  98     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
  99                                     imm=8, imm_ok=1)
 100     assert result == 8
 101
 102     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
 103     assert result == 2
 104
 105
 106 def test_compunit():
 107
 108     m = Module()
 109     alu = ALU(16)
 110     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 111     m.submodules.cu = dut
 112
 113     vl = rtlil.convert(dut, ports=dut.ports())
 114     with open("test_compunit1.il", "w") as f:
 115         f.write(vl)
 116
 117     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
 118
 119
 120 class CompUnitParallelTest:
 121     def __init__(self, dut):
 122         self.dut = dut
 123
 124         # Operation cycle should not take longer than this:
 125         self.MAX_BUSY_WAIT = 50
 126
 127         # Minimum duration in which issue_i will be kept inactive,
 128         # during which busy_o must remain low.
 129         self.MIN_BUSY_LOW = 5
 130
 131         # Number of cycles to stall until the assertion of go.
 132         # One value, for each port. Can be zero, for no delay.
 133         self.RD_GO_DELAY = [0, 3]
 134
 135         # store common data for the input operation of the processes
 136         # input operation:
 137         self.op = 0
 138         self.inv_a = self.zero_a = 0
 139         self.imm = self.imm_ok = 0
 140         self.rdmaskn = (0, 0)
 141         # input data:
 142         self.a = self.b = 0
 143
 144     def driver(self):
 145         print("Begin parallel test.")
 146         yield from self.operation(5, 2, InternalOp.OP_ADD, inv_a=0,
 147                                   imm=8, imm_ok=1, rdmaskn=(1, 0))
 148
 149     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 150                   rdmaskn=(0, 0)):
 151         # store data for the operation
 152         self.a = a
 153         self.b = b
 154         self.op = op
 155         self.inv_a = inv_a
 156         self.imm = imm
 157         self.imm_ok = imm_ok
 158         self.zero_a = zero_a
 159         self.rdmaskn = rdmaskn
 160
 161         # trigger operation cycle
 162         yield from self.issue()
 163
 164     def issue(self):
 165         # issue_i starts inactive
 166         yield self.dut.issue_i.eq(0)
 167
 168         for n in range(self.MIN_BUSY_LOW):
 169             yield
 170             # busy_o must remain inactive. It cannot rise on its own.
 171             busy_o = yield self.dut.busy_o
 172             assert not busy_o
 173
 174         # activate issue_i to begin the operation cycle
 175         yield self.dut.issue_i.eq(1)
 176
 177         # at the same time, present the operation
 178         yield self.dut.oper_i.insn_type.eq(self.op)
 179         yield self.dut.oper_i.invert_a.eq(self.inv_a)
 180         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
 181         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
 182         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 183         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 184         yield self.dut.rdmaskn.eq(rdmaskn)
 185
 186         # give one cycle for the CompUnit to latch the data
 187         yield
 188
 189         # busy_o must keep being low in this cycle, because issue_i was
 190         # low on the previous cycle.
 191         # It cannot rise on its own.
 192         # Also, busy_o and issue_i must never be active at the same time, ever.
 193         busy_o = yield self.dut.busy_o
 194         assert not busy_o
 195
 196         # Lower issue_i
 197         yield self.dut.issue_i.eq(0)
 198
 199         # deactivate inputs along with issue_i, so we can be sure the data
 200         # was latched at the correct cycle
 201         # note: rdmaskn must be held, while busy_o is active
 202         # TODO: deactivate rdmaskn when the busy_o cycle ends
 203         yield self.dut.oper_i.insn_type.eq(0)
 204         yield self.dut.oper_i.invert_a.eq(0)
 205         yield self.dut.oper_i.imm_data.imm.eq(0)
 206         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
 207         yield self.dut.oper_i.zero_a.eq(0)
 208         yield
 209
 210         # wait for busy_o to lower
 211         # timeout after self.MAX_BUSY_WAIT cycles
 212         for n in range(self.MAX_BUSY_WAIT):
 213             # sample busy_o in the current cycle
 214             busy_o = yield self.dut.busy_o
 215             if not busy_o:
 216                 # operation cycle ends when busy_o becomes inactive
 217                 break
 218             yield
 219
 220         # if busy_o is still active, a timeout has occurred
 221         # TODO: Uncomment this, once the test is complete:
 222         # assert not busy_o
 223
 224         if busy_o:
 225             print("If you are reading this, "
 226                   "it's because the above test failed, as expected,\n"
 227                   "with a timeout. It must pass, once the test is complete.")
 228             return
 229
 230         print("If you are reading this, "
 231               "it's because the above test unexpectedly passed.")
 232
 233     def rd(self, rd_idx):
 234         # wait for issue_i to rise
 235         while True:
 236             issue_i = yield self.dut.issue_i
 237             if issue_i:
 238                 break
 239             # issue_i has not risen yet, so rd must keep low
 240             rel = yield self.dut.rd.rel[rd_idx]
 241             assert not rel
 242             yield
 243
 244         # we do not want rd to rise on an immediate operand
 245         # if it is immediate, exit the process
 246         # likewise, if the read mask is active
 247         # TODO: don't exit the process, monitor rd instead to ensure it
 248         #       doesn't rise on its own
 249         if self.rdmaskn[rd_idx] \
 250                 or (rd_idx == 0 and self.zero_a) \
 251                 or (rd_idx == 1 and self.imm_ok):
 252             return
 253
 254         # issue_i has risen. rel must rise on the next cycle
 255         rel = yield self.dut.rd.rel[rd_idx]
 256         assert not rel
 257
 258         # stall for additional cycles. Check that rel doesn't fall on its own
 259         for n in range(self.RD_GO_DELAY[rd_idx]):
 260             yield
 261             rel = yield self.dut.rd.rel[rd_idx]
 262             assert rel
 263
 264         # Before asserting "go", make sure "rel" has risen.
 265         # The use of Settle allows "go" to be set combinatorially,
 266         # rising on the same cycle as "rel".
 267         yield Settle()
 268         rel = yield self.dut.rd.rel[rd_idx]
 269         assert rel
 270
 271         # assert go for one cycle
 272         yield self.dut.rd.go[rd_idx].eq(1)
 273         yield
 274
 275         # rel must keep high, since go was inactive in the last cycle
 276         rel = yield self.dut.rd.rel[rd_idx]
 277         assert rel
 278
 279         # finish the go one-clock pulse
 280         yield self.dut.rd.go[rd_idx].eq(0)
 281         yield
 282
 283         # rel must have gone low in response to go being high
 284         # on the previous cycle
 285         rel = yield self.dut.rd.rel[rd_idx]
 286         assert not rel
 287
 288         # TODO: also when dut.rd.go is set, put the expected value into
 289         # the src_i.  use dut.get_in[rd_idx] to do so
 290
 291     def wr(self, wr_idx):
 292         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 293         yield
 294         # TODO: also when dut.wr.go is set, check the output against the
 295         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 296
 297     def run_simulation(self, vcd_name):
 298         run_simulation(self.dut, [self.driver(),
 299                                   self.rd(0),  # one read port (a)
 300                                   self.rd(1),  # one read port (b)
 301                                   self.wr(0),  # one write port (o)
 302                                   ],
 303                        vcd_name=vcd_name)
 304
 305
 306 def test_compunit_regspec3():
 307
 308     inspec = [('INT', 'a', '0:15'),
 309               ('INT', 'b', '0:15'),
 310               ('INT', 'c', '0:15')]
 311     outspec = [('INT', 'o', '0:15'),
 312               ]
 313
 314     regspec = (inspec, outspec)
 315
 316     m = Module()
 317     alu = DummyALU(16)
 318     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 319     m.submodules.cu = dut
 320
 321     run_simulation(m, scoreboard_sim_dummy(dut),
 322                    vcd_name='test_compunit_regspec3.vcd')
 323
 324
 325 def test_compunit_regspec1():
 326
 327     inspec = [('INT', 'a', '0:15'),
 328               ('INT', 'b', '0:15')]
 329     outspec = [('INT', 'o', '0:15'),
 330               ]
 331
 332     regspec = (inspec, outspec)
 333
 334     m = Module()
 335     alu = ALU(16)
 336     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 337     m.submodules.cu = dut
 338
 339     vl = rtlil.convert(dut, ports=dut.ports())
 340     with open("test_compunit_regspec1.il", "w") as f:
 341         f.write(vl)
 342
 343     run_simulation(m, scoreboard_sim(dut),
 344                    vcd_name='test_compunit_regspec1.vcd')
 345
 346     test = CompUnitParallelTest(dut)
 347     test.run_simulation("test_compunit_parallel.vcd")
 348
 349
 350 if __name__ == '__main__':
 351     test_compunit()
 352     test_compunit_regspec1()
 353     test_compunit_regspec3()