src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.experiment.alu_hier import ALU, DummyALU
  16 from soc.experiment.compalu_multi import MultiCompUnit
  17 from soc.decoder.power_enums import MicrOp
  18 from nmutil.gtkw import write_gtkw
  19 from nmigen import Module, Signal
  20 from nmigen.cli import rtlil
  21
  22 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  23 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  24 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  25                                         Passive)
  26
  27
  28 def wrap(process):
  29     def wrapper():
  30         yield from process
  31     return wrapper
  32
  33
  34 class OperandProducer:
  35     """
  36     Produces an operand when requested by the Computation Unit
  37     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  38
  39     Attaches itself to the `dut` operand indexed by `op_index`.
  40
  41     Has a programmable delay between the assertion of `rel_o` and the
  42     `go_i` pulse.
  43
  44     Data is presented only during the cycle in which `go_i` is active.
  45
  46     It adds itself as a passive process to the simulation (`sim` parameter).
  47     Since it is passive, it will not hang the simulation, and does not need a
  48     flag to terminate itself.
  49     """
  50     def __init__(self, sim, dut, op_index):
  51         self.count = Signal(8, name=f"src{op_index + 1}_count")
  52         """ transaction counter"""
  53         # data and handshake signals from the DUT
  54         self.port = dut.src_i[op_index]
  55         self.go_i = dut.rd.go_i[op_index]
  56         self.rel_o = dut.rd.rel_o[op_index]
  57         # transaction parameters, passed via signals
  58         self.delay = Signal(8)
  59         self.data = Signal.like(self.port)
  60         # add ourselves to the simulation process list
  61         sim.add_sync_process(self._process)
  62
  63     def _process(self):
  64         yield Passive()
  65         while True:
  66             # Settle() is needed to give a quick response to
  67             # the zero delay case
  68             yield Settle()
  69             # wait for rel_o to become active
  70             while not (yield self.rel_o):
  71                 yield
  72                 yield Settle()
  73             # read the transaction parameters
  74             delay = (yield self.delay)
  75             data = (yield self.data)
  76             # wait for `delay` cycles
  77             for _ in range(delay):
  78                 yield
  79             # activate go_i and present data, for one cycle
  80             yield self.go_i.eq(1)
  81             yield self.port.eq(data)
  82             yield self.count.eq(self.count + 1)
  83             yield
  84             yield self.go_i.eq(0)
  85             yield self.port.eq(0)
  86
  87     def send(self, data, delay):
  88         """
  89         Schedules the module to send some `data`, counting `delay` cycles after
  90         `rel_i` becomes active.
  91
  92         To be called from the main test-bench process,
  93         it returns in the same cycle.
  94
  95         Communication with the worker process is done by means of
  96         combinatorial simulation-only signals.
  97
  98         """
  99         yield self.data.eq(data)
 100         yield self.delay.eq(delay)
 101
 102
 103 class ResultConsumer:
 104     """
 105     Consumes a result when requested by the Computation Unit
 106     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 107
 108     Attaches itself to the `dut` result indexed by `op_index`.
 109
 110     Has a programmable delay between the assertion of `rel_o` and the
 111     `go_i` pulse.
 112
 113     Data is retrieved only during the cycle in which `go_i` is active.
 114
 115     It adds itself as a passive process to the simulation (`sim` parameter).
 116     Since it is passive, it will not hang the simulation, and does not need a
 117     flag to terminate itself.
 118     """
 119     def __init__(self, sim, dut, op_index):
 120         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 121         """ transaction counter"""
 122         # data and handshake signals from the DUT
 123         self.port = dut.dest[op_index]
 124         self.go_i = dut.wr.go_i[op_index]
 125         self.rel_o = dut.wr.rel_o[op_index]
 126         # transaction parameters, passed via signals
 127         self.delay = Signal(8)
 128         self.expected = Signal.like(self.port)
 129         # add ourselves to the simulation process list
 130         sim.add_sync_process(self._process)
 131
 132     def _process(self):
 133         yield Passive()
 134         while True:
 135             # Settle() is needed to give a quick response to
 136             # the zero delay case
 137             yield Settle()
 138             # wait for rel_o to become active
 139             while not (yield self.rel_o):
 140                 yield
 141                 yield Settle()
 142             # read the transaction parameters
 143             delay = (yield self.delay)
 144             expected = (yield self.expected)
 145             # wait for `delay` cycles
 146             for _ in range(delay):
 147                 yield
 148             # activate go_i for one cycle
 149             yield self.go_i.eq(1)
 150             yield self.count.eq(self.count + 1)
 151             yield
 152             # check received data against the expected value
 153             result = (yield self.port)
 154             assert result == expected,\
 155                 f"expected {expected}, received {result}"
 156             yield self.go_i.eq(0)
 157             yield self.port.eq(0)
 158
 159     def receive(self, expected, delay):
 160         """
 161         Schedules the module to receive some result,
 162         counting `delay` cycles after `rel_i` becomes active.
 163         As 'go_i' goes active, check the result with `expected`.
 164
 165         To be called from the main test-bench process,
 166         it returns in the same cycle.
 167
 168         Communication with the worker process is done by means of
 169         combinatorial simulation-only signals.
 170         """
 171         yield self.expected.eq(expected)
 172         yield self.delay.eq(delay)
 173
 174
 175 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 176     yield dut.issue_i.eq(0)
 177     yield
 178     yield dut.src_i[0].eq(a)
 179     yield dut.src_i[1].eq(b)
 180     yield dut.oper_i.insn_type.eq(op)
 181     yield dut.oper_i.invert_in.eq(inv_a)
 182     yield dut.oper_i.imm_data.data.eq(imm)
 183     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 184     yield dut.oper_i.zero_a.eq(zero_a)
 185     yield dut.issue_i.eq(1)
 186     yield
 187     yield dut.issue_i.eq(0)
 188     yield
 189     if not imm_ok or not zero_a:
 190         yield dut.rd.go_i.eq(0b11)
 191         while True:
 192             yield
 193             rd_rel_o = yield dut.rd.rel_o
 194             print("rd_rel", rd_rel_o)
 195             if rd_rel_o:
 196                 break
 197         yield dut.rd.go_i.eq(0)
 198     else:
 199         print("no go rd")
 200
 201     if len(dut.src_i) == 3:
 202         yield dut.rd.go_i.eq(0b100)
 203         while True:
 204             yield
 205             rd_rel_o = yield dut.rd.rel_o
 206             print("rd_rel", rd_rel_o)
 207             if rd_rel_o:
 208                 break
 209         yield dut.rd.go_i.eq(0)
 210     else:
 211         print("no 3rd rd")
 212
 213     req_rel_o = yield dut.wr.rel_o
 214     result = yield dut.data_o
 215     print("req_rel", req_rel_o, result)
 216     while True:
 217         req_rel_o = yield dut.wr.rel_o
 218         result = yield dut.data_o
 219         print("req_rel", req_rel_o, result)
 220         if req_rel_o:
 221             break
 222         yield
 223     yield dut.wr.go_i[0].eq(1)
 224     yield Settle()
 225     result = yield dut.data_o
 226     yield
 227     print("result", result)
 228     yield dut.wr.go_i[0].eq(0)
 229     yield
 230     return result
 231
 232
 233 def scoreboard_sim_fsm(dut, producers, consumers):
 234
 235     # stores the operation count
 236     op_count = 0
 237
 238     def op_sim_fsm(a, b, direction, expected, delays):
 239         print("op_sim_fsm", a, b, direction, expected)
 240         yield dut.issue_i.eq(0)
 241         yield
 242         # forward data and delays to the producers and consumers
 243         yield from producers[0].send(a, delays[0])
 244         yield from producers[1].send(b, delays[1])
 245         yield from consumers[0].receive(expected, delays[2])
 246         # submit operation, and assert issue_i for one cycle
 247         yield dut.oper_i.sdir.eq(direction)
 248         yield dut.issue_i.eq(1)
 249         yield
 250         yield dut.issue_i.eq(0)
 251         # wait for busy to be negated
 252         yield Settle()
 253         while (yield dut.busy_o):
 254             yield
 255             yield Settle()
 256         # update the operation count
 257         nonlocal op_count
 258         op_count = (op_count + 1) & 255
 259         # check that producers and consumers have the same count
 260         # this assures that no data was left unused or was lost
 261         assert (yield producers[0].count) == op_count
 262         assert (yield producers[1].count) == op_count
 263         assert (yield consumers[0].count) == op_count
 264
 265     # 13 >> 2 = 3
 266     # operand 1 arrives immediately
 267     # operand 2 arrives after operand 1
 268     # write data is accepted immediately
 269     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 270     # 3 << 4 = 48
 271     # operand 2 arrives immediately
 272     # operand 1 arrives after operand 2
 273     # write data is accepted after some delay
 274     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 275     # 21 << 0 = 21
 276     # operands 1 and 2 arrive at the same time
 277     # write data is accepted after some delay
 278     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 279
 280
 281 def scoreboard_sim_dummy(dut):
 282     result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
 283                                imm=8, imm_ok=1)
 284     assert result == 5, result
 285
 286     result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
 287                                imm=8, imm_ok=1)
 288     assert result == 9, result
 289
 290
 291 class OpSim:
 292     """ALU Operation issuer
 293
 294     Issues operations to the DUT"""
 295     def __init__(self, dut, producers, consumers):
 296         self.op_count = 0
 297         self.zero_a_count = 0
 298         self.imm_ok_count = 0
 299         self.dut = dut
 300         self.producers = producers
 301         self.consumers = consumers
 302
 303     def issue(self, a, b, op, expected, delays,
 304               inv_a=0, imm=0, imm_ok=0, zero_a=0):
 305         """Executes the issue operation"""
 306         dut = self.dut
 307         producers = self.producers
 308         consumers = self.consumers
 309         print("issue", a, b, op, expected)
 310         yield dut.issue_i.eq(0)
 311         yield
 312         # forward data and delays to the producers and consumers
 313         if not zero_a:
 314             yield from producers[0].send(a, delays[0])
 315         if not imm_ok:
 316             yield from producers[1].send(b, delays[1])
 317         yield from consumers[0].receive(expected, delays[2])
 318         # submit operation, and assert issue_i for one cycle
 319         yield dut.oper_i.insn_type.eq(op)
 320         yield dut.oper_i.invert_in.eq(inv_a)
 321         yield dut.oper_i.imm_data.data.eq(imm)
 322         yield dut.oper_i.imm_data.ok.eq(imm_ok)
 323         yield dut.oper_i.zero_a.eq(zero_a)
 324         yield dut.issue_i.eq(1)
 325         yield
 326         yield dut.issue_i.eq(0)
 327         # wait for busy to be negated
 328         yield Settle()
 329         while (yield dut.busy_o):
 330             yield
 331             yield Settle()
 332         # update the operation count
 333         self.op_count = (self.op_count + 1) & 255
 334         # On zero_a and imm_ok executions, the producer counters will fall
 335         # behind. But, by summing the following counts, the invariant is
 336         # preserved.
 337         if zero_a:
 338             self.zero_a_count = self.zero_a_count + 1
 339         if imm_ok:
 340             self.imm_ok_count = self.imm_ok_count + 1
 341         # check that producers and consumers have the same count
 342         # this assures that no data was left unused or was lost
 343         assert (yield producers[0].count) + self.zero_a_count == self.op_count
 344         assert (yield producers[1].count) + self.imm_ok_count == self.op_count
 345         assert (yield consumers[0].count) == self.op_count
 346
 347
 348 def scoreboard_sim(op):
 349     # zero (no) input operands test
 350     # 0 + 8 = 8
 351     yield from op.issue(5, 2, MicrOp.OP_ADD,
 352                         zero_a=1, imm=8, imm_ok=1,
 353                         expected=8, delays=[0, 2, 0])
 354     # 5 + 8 = 13
 355     yield from op.issue(5, 2, MicrOp.OP_ADD,
 356                         inv_a=0, imm=8, imm_ok=1,
 357                         expected=13, delays=[2, 0, 2])
 358     # 5 + 2 = 7
 359     yield from op.issue(5, 2, MicrOp.OP_ADD,
 360                         expected=7, delays=[1, 1, 1])
 361     # (-6) + 2 = (-4)
 362     yield from op.issue(5, 2, MicrOp.OP_ADD, inv_a=1,
 363                         expected=65532, delays=[1, 2, 0])
 364     # 0 + 2 = 2
 365     yield from op.issue(5, 2, MicrOp.OP_ADD, zero_a=1,
 366                         expected=2, delays=[2, 0, 1])
 367
 368     # test combinatorial zero-delay operation
 369     # In the test ALU, any operation other than ADD, MUL or SHR
 370     # is zero-delay, and do a subtraction.
 371     yield from op.issue(5, 2, MicrOp.OP_NOP,
 372                         expected=3, delays=[0, 1, 2])
 373
 374
 375 def test_compunit_fsm():
 376     top = "top.cu" if is_engine_pysim() else "cu"
 377     style = {
 378         'in': {'color': 'orange'},
 379         'out': {'color': 'yellow'},
 380     }
 381     traces = [
 382         'clk',
 383         ('operation port', {'color': 'red'}, [
 384             'cu_issue_i', 'cu_busy_o',
 385             {'comment': 'operation'},
 386             'oper_i_None__sdir']),
 387         ('operand 1 port', 'in', [
 388             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 389             ('cu_rd__go_i[1:0]', {'bit': 1}),
 390             'src1_i[7:0]']),
 391         ('operand 2 port', 'in', [
 392             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 393             ('cu_rd__go_i[1:0]', {'bit': 0}),
 394             'src2_i[7:0]']),
 395         ('result port', 'out', [
 396             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 397         ('alu', {'module': top+'.alu'}, [
 398             ('prev port', 'in', [
 399                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 400                 'p_valid_i', 'p_ready_o']),
 401             ('next port', 'out', [
 402                 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
 403         ]),
 404         ('debug', {'module': 'top'},
 405          ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
 406
 407     ]
 408     write_gtkw(
 409         "test_compunit_fsm1.gtkw",
 410         "test_compunit_fsm1.vcd",
 411         traces, style,
 412         module=top
 413     )
 414     m = Module()
 415     alu = Shifter(8)
 416     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 417     m.submodules.cu = dut
 418
 419     vl = rtlil.convert(dut, ports=dut.ports())
 420     with open("test_compunit_fsm1.il", "w") as f:
 421         f.write(vl)
 422
 423     sim = Simulator(m)
 424     sim.add_clock(1e-6)
 425
 426     # create one operand producer for each input port
 427     prod_a = OperandProducer(sim, dut, 0)
 428     prod_b = OperandProducer(sim, dut, 1)
 429     # create an result consumer for the output port
 430     cons = ResultConsumer(sim, dut, 0)
 431     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 432                                                  [prod_a, prod_b],
 433                                                  [cons])))
 434     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 435                                traces=[prod_a.count,
 436                                        prod_b.count,
 437                                        cons.count])
 438     with sim_writer:
 439         sim.run()
 440
 441
 442 def test_compunit():
 443
 444     m = Module()
 445     alu = ALU(16)
 446     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 447     m.submodules.cu = dut
 448
 449     vl = rtlil.convert(dut, ports=dut.ports())
 450     with open("test_compunit1.il", "w") as f:
 451         f.write(vl)
 452
 453     sim = Simulator(m)
 454     sim.add_clock(1e-6)
 455
 456     # create one operand producer for each input port
 457     prod_a = OperandProducer(sim, dut, 0)
 458     prod_b = OperandProducer(sim, dut, 1)
 459     # create an result consumer for the output port
 460     cons = ResultConsumer(sim, dut, 0)
 461     # create an operation issuer
 462     op = OpSim(dut, [prod_a, prod_b], [cons])
 463     sim.add_sync_process(wrap(scoreboard_sim(op)))
 464     sim_writer = sim.write_vcd('test_compunit1.vcd')
 465     with sim_writer:
 466         sim.run()
 467
 468
 469 class CompUnitParallelTest:
 470     def __init__(self, dut):
 471         self.dut = dut
 472
 473         # Operation cycle should not take longer than this:
 474         self.MAX_BUSY_WAIT = 50
 475
 476         # Minimum duration in which issue_i will be kept inactive,
 477         # during which busy_o must remain low.
 478         self.MIN_BUSY_LOW = 5
 479
 480         # Number of cycles to stall until the assertion of go.
 481         # One value, for each port. Can be zero, for no delay.
 482         self.RD_GO_DELAY = [0, 3]
 483
 484         # store common data for the input operation of the processes
 485         # input operation:
 486         self.op = 0
 487         self.inv_a = self.zero_a = 0
 488         self.imm = self.imm_ok = 0
 489         self.imm_control = (0, 0)
 490         self.rdmaskn = (0, 0)
 491         # input data:
 492         self.operands = (0, 0)
 493
 494         # Indicates completion of the sub-processes
 495         self.rd_complete = [False, False]
 496
 497     def driver(self):
 498         print("Begin parallel test.")
 499         yield from self.operation(5, 2, MicrOp.OP_ADD)
 500
 501     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 502                   rdmaskn=(0, 0)):
 503         # store data for the operation
 504         self.operands = (a, b)
 505         self.op = op
 506         self.inv_a = inv_a
 507         self.imm = imm
 508         self.imm_ok = imm_ok
 509         self.zero_a = zero_a
 510         self.imm_control = (zero_a, imm_ok)
 511         self.rdmaskn = rdmaskn
 512
 513         # Initialize completion flags
 514         self.rd_complete = [False, False]
 515
 516         # trigger operation cycle
 517         yield from self.issue()
 518
 519         # check that the sub-processes completed, before the busy_o cycle ended
 520         for completion in self.rd_complete:
 521             assert completion
 522
 523     def issue(self):
 524         # issue_i starts inactive
 525         yield self.dut.issue_i.eq(0)
 526
 527         for n in range(self.MIN_BUSY_LOW):
 528             yield
 529             # busy_o must remain inactive. It cannot rise on its own.
 530             busy_o = yield self.dut.busy_o
 531             assert not busy_o
 532
 533         # activate issue_i to begin the operation cycle
 534         yield self.dut.issue_i.eq(1)
 535
 536         # at the same time, present the operation
 537         yield self.dut.oper_i.insn_type.eq(self.op)
 538         yield self.dut.oper_i.invert_in.eq(self.inv_a)
 539         yield self.dut.oper_i.imm_data.data.eq(self.imm)
 540         yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
 541         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 542         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 543         yield self.dut.rdmaskn.eq(rdmaskn)
 544
 545         # give one cycle for the CompUnit to latch the data
 546         yield
 547
 548         # busy_o must keep being low in this cycle, because issue_i was
 549         # low on the previous cycle.
 550         # It cannot rise on its own.
 551         # Also, busy_o and issue_i must never be active at the same time, ever.
 552         busy_o = yield self.dut.busy_o
 553         assert not busy_o
 554
 555         # Lower issue_i
 556         yield self.dut.issue_i.eq(0)
 557
 558         # deactivate inputs along with issue_i, so we can be sure the data
 559         # was latched at the correct cycle
 560         # note: rdmaskn must be held, while busy_o is active
 561         # TODO: deactivate rdmaskn when the busy_o cycle ends
 562         yield self.dut.oper_i.insn_type.eq(0)
 563         yield self.dut.oper_i.invert_in.eq(0)
 564         yield self.dut.oper_i.imm_data.data.eq(0)
 565         yield self.dut.oper_i.imm_data.ok.eq(0)
 566         yield self.dut.oper_i.zero_a.eq(0)
 567         yield
 568
 569         # wait for busy_o to lower
 570         # timeout after self.MAX_BUSY_WAIT cycles
 571         for n in range(self.MAX_BUSY_WAIT):
 572             # sample busy_o in the current cycle
 573             busy_o = yield self.dut.busy_o
 574             if not busy_o:
 575                 # operation cycle ends when busy_o becomes inactive
 576                 break
 577             yield
 578
 579         # if busy_o is still active, a timeout has occurred
 580         # TODO: Uncomment this, once the test is complete:
 581         # assert not busy_o
 582
 583         if busy_o:
 584             print("If you are reading this, "
 585                   "it's because the above test failed, as expected,\n"
 586                   "with a timeout. It must pass, once the test is complete.")
 587             return
 588
 589         print("If you are reading this, "
 590               "it's because the above test unexpectedly passed.")
 591
 592     def rd(self, rd_idx):
 593         # wait for issue_i to rise
 594         while True:
 595             issue_i = yield self.dut.issue_i
 596             if issue_i:
 597                 break
 598             # issue_i has not risen yet, so rd must keep low
 599             rel = yield self.dut.rd.rel_o[rd_idx]
 600             assert not rel
 601             yield
 602
 603         # we do not want rd to rise on an immediate operand
 604         # if it is immediate, exit the process
 605         # likewise, if the read mask is active
 606         # TODO: don't exit the process, monitor rd instead to ensure it
 607         #       doesn't rise on its own
 608         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 609             self.rd_complete[rd_idx] = True
 610             return
 611
 612         # issue_i has risen. rel must rise on the next cycle
 613         rel = yield self.dut.rd.rel_o[rd_idx]
 614         assert not rel
 615
 616         # stall for additional cycles. Check that rel doesn't fall on its own
 617         for n in range(self.RD_GO_DELAY[rd_idx]):
 618             yield
 619             rel = yield self.dut.rd.rel_o[rd_idx]
 620             assert rel
 621
 622         # Before asserting "go", make sure "rel" has risen.
 623         # The use of Settle allows "go" to be set combinatorially,
 624         # rising on the same cycle as "rel".
 625         yield Settle()
 626         rel = yield self.dut.rd.rel_o[rd_idx]
 627         assert rel
 628
 629         # assert go for one cycle, passing along the operand value
 630         yield self.dut.rd.go_i[rd_idx].eq(1)
 631         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 632         # check that the operand was sent to the alu
 633         # TODO: Properly check the alu protocol
 634         yield Settle()
 635         alu_input = yield self.dut.get_in(rd_idx)
 636         assert alu_input == self.operands[rd_idx]
 637         yield
 638
 639         # rel must keep high, since go was inactive in the last cycle
 640         rel = yield self.dut.rd.rel_o[rd_idx]
 641         assert rel
 642
 643         # finish the go one-clock pulse
 644         yield self.dut.rd.go_i[rd_idx].eq(0)
 645         yield self.dut.src_i[rd_idx].eq(0)
 646         yield
 647
 648         # rel must have gone low in response to go being high
 649         # on the previous cycle
 650         rel = yield self.dut.rd.rel_o[rd_idx]
 651         assert not rel
 652
 653         self.rd_complete[rd_idx] = True
 654
 655         # TODO: check that rel doesn't rise again until the end of the
 656         #       busy_o cycle
 657
 658     def wr(self, wr_idx):
 659         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 660         yield
 661         # TODO: also when dut.wr.go is set, check the output against the
 662         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 663
 664     def run_simulation(self, vcd_name):
 665         m = Module()
 666         m.submodules.cu = self.dut
 667         sim = Simulator(m)
 668         sim.add_clock(1e-6)
 669
 670         sim.add_sync_process(wrap(self.driver()))
 671         sim.add_sync_process(wrap(self.rd(0)))
 672         sim.add_sync_process(wrap(self.rd(1)))
 673         sim.add_sync_process(wrap(self.wr(0)))
 674         sim_writer = sim.write_vcd(vcd_name)
 675         with sim_writer:
 676             sim.run()
 677
 678
 679 def test_compunit_regspec2_fsm():
 680
 681     inspec = [('INT', 'data', '0:15'),
 682               ('INT', 'shift', '0:15'),
 683               ]
 684     outspec = [('INT', 'data', '0:15'),
 685                ]
 686
 687     regspec = (inspec, outspec)
 688
 689     m = Module()
 690     alu = Shifter(8)
 691     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 692     m.submodules.cu = dut
 693
 694     sim = Simulator(m)
 695     sim.add_clock(1e-6)
 696
 697     # create one operand producer for each input port
 698     prod_a = OperandProducer(sim, dut, 0)
 699     prod_b = OperandProducer(sim, dut, 1)
 700     # create an result consumer for the output port
 701     cons = ResultConsumer(sim, dut, 0)
 702     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 703                                                  [prod_a, prod_b],
 704                                                  [cons])))
 705     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 706                                traces=[prod_a.count,
 707                                        prod_b.count,
 708                                        cons.count])
 709     with sim_writer:
 710         sim.run()
 711
 712
 713 def test_compunit_regspec3():
 714
 715     inspec = [('INT', 'a', '0:15'),
 716               ('INT', 'b', '0:15'),
 717               ('INT', 'c', '0:15')]
 718     outspec = [('INT', 'o', '0:15'),
 719                ]
 720
 721     regspec = (inspec, outspec)
 722
 723     m = Module()
 724     alu = DummyALU(16)
 725     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 726     m.submodules.cu = dut
 727
 728     sim = Simulator(m)
 729     sim.add_clock(1e-6)
 730
 731     sim.add_sync_process(wrap(scoreboard_sim_dummy(dut)))
 732     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 733     with sim_writer:
 734         sim.run()
 735
 736
 737 def test_compunit_regspec1():
 738
 739     style = {
 740         'in': {'color': 'orange'},
 741         'out': {'color': 'yellow'},
 742     }
 743     traces = [
 744         'clk',
 745         ('operation port', {'color': 'red'}, [
 746             'cu_issue_i', 'cu_busy_o',
 747             {'comment': 'operation'},
 748             ('oper_i_None__insn_type', {'display': 'insn_type'}),
 749             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 750             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 751             ('oper_i_None__imm_data__imm_ok', {'display': 'imm_ok'}),
 752             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 753         ('operand 1 port', 'in', [
 754             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 755             ('cu_rd__go_i[1:0]', {'bit': 1}),
 756             'src1_i[15:0]']),
 757         ('operand 2 port', 'in', [
 758             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 759             ('cu_rd__go_i[1:0]', {'bit': 0}),
 760             'src2_i[15:0]']),
 761         ('result port', 'out', [
 762             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 763         ('alu', {'module': 'top.cu.alu'}, [
 764             ('prev port', 'in', [
 765                 'op__insn_type', 'op__invert_i', 'a[15:0]', 'b[15:0]',
 766                 'valid_i', 'ready_o']),
 767             ('next port', 'out', [
 768                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
 769         ('debug', {'module': 'top'},
 770             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 771
 772     write_gtkw("test_compunit_regspec1.gtkw",
 773                "test_compunit_regspec1.vcd",
 774                traces, style,
 775                clk_period=1e-6,
 776                module='top.cu')
 777
 778     inspec = [('INT', 'a', '0:15'),
 779               ('INT', 'b', '0:15')]
 780     outspec = [('INT', 'o', '0:15'),
 781                ]
 782
 783     regspec = (inspec, outspec)
 784
 785     m = Module()
 786     alu = ALU(16)
 787     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 788     m.submodules.cu = dut
 789
 790     vl = rtlil.convert(dut, ports=dut.ports())
 791     with open("test_compunit_regspec1.il", "w") as f:
 792         f.write(vl)
 793
 794     sim = Simulator(m)
 795     sim.add_clock(1e-6)
 796
 797     # create one operand producer for each input port
 798     prod_a = OperandProducer(sim, dut, 0)
 799     prod_b = OperandProducer(sim, dut, 1)
 800     # create an result consumer for the output port
 801     cons = ResultConsumer(sim, dut, 0)
 802     # create an operation issuer
 803     op = OpSim(dut, [prod_a, prod_b], [cons])
 804     sim.add_sync_process(wrap(scoreboard_sim(op)))
 805     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 806                                traces=[prod_a.count,
 807                                        prod_b.count,
 808                                        cons.count])
 809     with sim_writer:
 810         sim.run()
 811
 812     test = CompUnitParallelTest(dut)
 813     test.run_simulation("test_compunit_parallel.vcd")
 814
 815
 816 if __name__ == '__main__':
 817     test_compunit()
 818     test_compunit_fsm()
 819     test_compunit_regspec1()
 820     test_compunit_regspec2_fsm()
 821     test_compunit_regspec3()