src/soc/experiment/test/test_compldst_multi.py

   1 """Self-contained unit test for the Load/Store CompUnit
   2 """
   3
   4 import unittest
   5 from nmigen import Module
   6 from nmigen.sim import Simulator
   7 from nmutil.gtkw import write_gtkw
   8
   9 from openpower.consts import MSR
  10 from openpower.decoder.power_enums import MicrOp, LDSTMode
  11
  12 from soc.experiment.compldst_multi import LDSTCompUnit
  13 from soc.experiment.pimem import PortInterface
  14 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  15
  16
  17 class OpSim:
  18     def __init__(self, dut):
  19         self.dut = dut
  20
  21     def issue(self, op, zero_a=False, imm=None, update=False,
  22               byterev=True, signext=False,
  23               data_len=2, msr_pr=0):
  24         dut = self.dut
  25         yield dut.oper_i.insn_type.eq(op)
  26         yield dut.oper_i.data_len.eq(data_len)
  27         yield dut.oper_i.zero_a.eq(zero_a)
  28         yield dut.oper_i.byte_reverse.eq(byterev)
  29         yield dut.oper_i.sign_extend.eq(signext)
  30         if imm is not None:
  31             yield dut.oper_i.imm_data.data.eq(imm)
  32             yield dut.oper_i.imm_data.ok.eq(1)
  33         if update:
  34             yield dut.oper_i.ldst_mode.eq(LDSTMode.update)
  35         yield dut.oper_i.msr[MSR.PR].eq(msr_pr)
  36         yield dut.issue_i.eq(1)
  37         yield
  38         yield dut.issue_i.eq(0)
  39         # deactivate decoder inputs along with issue_i, so we can be sure they
  40         # were latched at the correct cycle
  41         yield dut.oper_i.insn_type.eq(0)
  42         yield dut.oper_i.data_len.eq(0)
  43         yield dut.oper_i.zero_a.eq(0)
  44         yield dut.oper_i.byte_reverse.eq(0)
  45         yield dut.oper_i.sign_extend.eq(0)
  46         yield dut.oper_i.imm_data.data.eq(0)
  47         yield dut.oper_i.imm_data.ok.eq(0)
  48         yield dut.oper_i.ldst_mode.eq(LDSTMode.NONE)
  49         yield dut.oper_i.msr[MSR.PR].eq(0)
  50
  51
  52 class TestLDSTCompUnit(unittest.TestCase):
  53
  54     def test_ldst_compunit(self):
  55         m = Module()
  56         pi = PortInterface(name="pi")
  57         regspec = LDSTPipeSpec.regspec
  58         dut = LDSTCompUnit(pi, regspec, name="ldst")
  59         m.submodules.dut = dut
  60         sim = Simulator(m)
  61         sim.add_clock(1e-6)
  62         op = OpSim(dut)
  63         self.write_gtkw()
  64
  65         def process():
  66             yield from op.issue(MicrOp.OP_STORE)
  67
  68         sim.add_sync_process(process)
  69         sim_writer = sim.write_vcd("test_ldst_compunit.vcd")
  70         with sim_writer:
  71             sim.run()
  72
  73     @classmethod
  74     def write_gtkw(cls):
  75         traces = [
  76             'clk',
  77             ('operation', [
  78                 ('oper_i_ldst__insn_type', {'display': 'insn_type'}),
  79                 ('oper_i_ldst__ldst_mode', {'display': 'ldst_mode'}),
  80                 ('oper_i_ldst__zero_a', {'display': 'zero_a'}),
  81                 ('oper_i_ldst__imm_data__ok', {'display': 'imm_data_ok'}),
  82                 ('oper_i_ldst__imm_data__data[63:0]',
  83                  {'display': 'imm_data_data', 'base': 'dec'})
  84             ]),
  85             ('cu_issue_i', {'display': 'issue_i'}),
  86             ('cu_busy_o', {'display': 'busy_o'})
  87         ]
  88         write_gtkw("test_ldst_compunit.gtkw",
  89                    "test_ldst_compunit.vcd",
  90                    traces, module="top.dut")
  91
  92
  93 if __name__ == '__main__':
  94     unittest.main()