bf91cd1a0e4f6a53fcacf35f6368a49ad1141f33
1 """Self-contained unit test for the Load/Store CompUnit
5 from nmigen
import Module
6 from nmigen
.sim
import Simulator
7 from nmutil
.gtkw
import write_gtkw
9 from openpower
.consts
import MSR
10 from openpower
.decoder
.power_enums
import MicrOp
, LDSTMode
12 from soc
.experiment
.compldst_multi
import LDSTCompUnit
13 from soc
.experiment
.pimem
import PortInterface
14 from soc
.experiment
.test
.test_compalu_multi
import OperandProducer
15 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
19 def __init__(self
, dut
, sim
):
21 # create one operand producer for each input port
22 self
.producers
= list()
23 for i
in range(len(dut
.src_i
)):
24 self
.producers
.append(OperandProducer(sim
, dut
, i
))
26 def issue(self
, op
, ra
=None, rb
=None, rc
=None,
27 zero_a
=False, imm
=None, update
=False,
28 byterev
=True, signext
=False,
31 assert zero_a
== (ra
is None), \
32 "ra and zero_a are mutually exclusive"
33 assert (rb
is None) != (imm
is None), \
34 "rb and imm are mutually exclusive"
35 if op
== MicrOp
.OP_STORE
:
36 assert rc
, "need source operand for store"
39 producers
= self
.producers
41 yield from producers
[0].send(ra
, delays
['ra'])
43 yield from producers
[1].send(rb
, delays
['rb'])
45 yield from producers
[2].send(rc
, delays
['rc'])
46 yield dut
.oper_i
.insn_type
.eq(op
)
47 yield dut
.oper_i
.data_len
.eq(data_len
)
48 yield dut
.oper_i
.zero_a
.eq(zero_a
)
49 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
50 yield dut
.oper_i
.sign_extend
.eq(signext
)
52 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
53 yield dut
.oper_i
.imm_data
.ok
.eq(1)
55 yield dut
.oper_i
.ldst_mode
.eq(LDSTMode
.update
)
56 yield dut
.oper_i
.msr
[MSR
.PR
].eq(msr_pr
)
57 yield dut
.issue_i
.eq(1)
59 yield dut
.issue_i
.eq(0)
60 # deactivate decoder inputs along with issue_i, so we can be sure they
61 # were latched at the correct cycle
62 yield dut
.oper_i
.insn_type
.eq(0)
63 yield dut
.oper_i
.data_len
.eq(0)
64 yield dut
.oper_i
.zero_a
.eq(0)
65 yield dut
.oper_i
.byte_reverse
.eq(0)
66 yield dut
.oper_i
.sign_extend
.eq(0)
67 yield dut
.oper_i
.imm_data
.data
.eq(0)
68 yield dut
.oper_i
.imm_data
.ok
.eq(0)
69 yield dut
.oper_i
.ldst_mode
.eq(LDSTMode
.NONE
)
70 yield dut
.oper_i
.msr
[MSR
.PR
].eq(0)
71 while not (yield pi
.addr
.ok
):
75 class TestLDSTCompUnit(unittest
.TestCase
):
77 def test_ldst_compunit(self
):
79 pi
= PortInterface(name
="pi")
80 regspec
= LDSTPipeSpec
.regspec
81 dut
= LDSTCompUnit(pi
, regspec
, name
="ldst")
82 m
.submodules
.dut
= dut
89 yield from op
.issue(MicrOp
.OP_STORE
, ra
=1, rb
=2, rc
=3,
90 delays
={'ra': 1, 'rb': 2, 'rc': 5})
92 sim
.add_sync_process(process
)
93 sim_writer
= sim
.write_vcd("test_ldst_compunit.vcd")
102 ('oper_i_ldst__insn_type', {'display': 'insn_type'}),
103 ('oper_i_ldst__ldst_mode', {'display': 'ldst_mode'}),
104 ('oper_i_ldst__zero_a', {'display': 'zero_a'}),
105 ('oper_i_ldst__imm_data__ok', {'display': 'imm_data_ok'}),
106 ('oper_i_ldst__imm_data__data[63:0]',
107 {'display': 'imm_data_data', 'base': 'dec'})
109 ('cu_issue_i', {'display': 'issue_i'}),
110 ('cu_busy_o', {'display': 'busy_o'})
112 write_gtkw("test_ldst_compunit.gtkw",
113 "test_ldst_compunit.vcd",
114 traces
, module
="top.dut")
117 if __name__
== '__main__':