1 # test case for LOAD / STORE Computation Unit using MMU
3 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
, Tick
4 from nmigen
.cli
import verilog
, rtlil
5 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
6 from nmigen
.hdl
.rec
import Record
, Layout
8 from nmutil
.latch
import SRLatch
, latchregister
9 from nmutil
.byterev
import byte_reverse
10 from nmutil
.extend
import exts
11 from nmutil
.util
import wrap
12 from soc
.fu
.regspec
import RegSpecAPI
14 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
15 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
16 from openpower
.decoder
.power_decoder2
import Data
17 from openpower
.consts
import MSR
19 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
20 from soc
.experiment
.l0_cache
import PortInterface
21 from soc
.experiment
.pimem
import LDSTException
22 from soc
.experiment
.compldst_multi
import LDSTCompUnit
, load
, store
23 from soc
.config
.test
.test_loadstore
import TestMemPspec
25 from soc
.experiment
.mmu
import MMU
26 from nmutil
.util
import Display
28 from soc
.config
.loadstore
import ConfigMemoryPortInterface
29 from soc
.experiment
.test
import pagetables
30 from soc
.experiment
.test
.test_wishbone
import wb_get
32 ########################################
34 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
36 yield dut
.mmu
.rin
.prtbl
.eq(0x1000000) # set process table
38 data
= 0xFF #just a single byte for this test
39 #data = 0xf553b658ba7e1f51
41 yield from store(dut
, addr
, 0, data
, 0)
43 ld_data
, data_ok
, addr
= yield from load(dut
, addr
, 0, 0)
45 print(data
,data_ok
,addr
)
48 dut
.stop
= True # stop simulation
50 ########################################
53 class TestLDSTCompUnitMMU(LDSTCompUnit
):
55 def __init__(self
, rwid
, pspec
):
56 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
57 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
59 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
61 def elaborate(self
, platform
):
62 m
= LDSTCompUnit
.elaborate(self
, platform
)
63 m
.submodules
.l0
= self
.l0
64 # link addr-go direct to rel
65 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
69 def test_scoreboard_mmu():
72 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
73 imem_ifacetype
='bare_wb',
79 dut
= TestLDSTCompUnitMMU(16,pspec
)
80 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
81 with
open("test_ldst_comp_mmu1.il", "w") as f
:
84 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
86 ########################################
87 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit
):
89 def __init__(self
, pspec
):
90 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
91 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
92 regspec
= LDSTPipeSpec
.regspec
94 # use a LoadStore1 here
96 cmpi
= ConfigMemoryPortInterface(pspec
)
102 LDSTCompUnit
.__init
__(self
, ldst
.pi
, regspec
, 4)
104 def elaborate(self
, platform
):
105 m
= LDSTCompUnit
.elaborate(self
, platform
)
106 m
.submodules
.l0
= self
.l0
107 m
.submodules
.mmu
= self
.mmu
108 # link addr-go direct to rel
109 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
111 # link mmu and dcache together
112 dcache
= self
.l0
.dcache
114 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
115 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
122 def test_scoreboard_regspec_mmu():
127 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
128 imem_ifacetype
='bare_wb',
134 dut
= TestLDSTCompUnitRegSpecMMU(pspec
)
136 m
.submodules
.dut
= dut
141 dut
.mem
= pagetables
.test1
144 sim
.add_sync_process(wrap(ldst_sim(dut
)))
145 sim
.add_sync_process(wrap(wb_get(dut
)))
146 with sim
.write_vcd('test_scoreboard_regspec_mmu'):
150 if __name__
== '__main__':
151 test_scoreboard_regspec_mmu()
152 #only one test for now -- test_scoreboard_mmu()