src/soc/experiment/test/test_compldst_multi_mmu_fsm.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from nmutil.util import wrap
  12 from soc.fu.regspec import RegSpecAPI
  13
  14 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  15 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  16 from openpower.decoder.power_decoder2 import Data
  17 from openpower.consts import MSR
  18
  19 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  20 from soc.experiment.l0_cache import PortInterface
  21 from soc.experiment.pimem import LDSTException
  22 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  23 from soc.config.test.test_loadstore import TestMemPspec
  24
  25 from soc.experiment.mmu import MMU
  26 from nmutil.util import Display
  27
  28 from soc.config.loadstore import ConfigMemoryPortInterface
  29 from soc.experiment.test import pagetables
  30 from soc.experiment.test.test_wishbone import wb_get
  31
  32 #new unit added to this test case
  33 from soc.fu.mmu.pipe_data import MMUPipeSpec
  34 from soc.fu.mmu.fsm import FSMMMUStage
  35
  36 #for sending instructions to the FSM
  37 from openpower.consts import MSR
  38 from openpower.decoder.power_fields import DecodeFields
  39 from openpower.decoder.power_fieldsn import SignalBitRange
  40 from openpower.decoder.power_decoder2 import decode_spr_num
  41 from openpower.decoder.power_enums import MicrOp
  42
  43 def ldst_sim(dut):
  44     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  45     addr = 0x100e0
  46     data = 0xFF #just a single byte for this test
  47     #data = 0xf553b658ba7e1f51
  48
  49     yield from store(dut, addr, 0, data, 0)
  50     yield
  51     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  52     print(data,data_ok,ld_addr)
  53     assert(ld_data==data)
  54     yield
  55
  56     ##### not yet complete
  57     yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
  58     yield
  59     yield
  60     yield
  61     yield
  62
  63     """
  64     -- not testing dzbz here --
  65     data = 0
  66
  67     print("doing dcbz/store with data 0 .....")
  68     yield from store_debug(dut, addr, 0, data, 0, dcbz=True) #hangs
  69
  70     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  71     print(data,data_ok,ld_addr)
  72     print("ld_data is")
  73     print(ld_data)
  74     assert(ld_data==data)
  75     print("dzbz test passed")
  76     """
  77
  78     dut.stop = True # stop simulation
  79
  80 ########################################
  81
  82
  83 class TestLDSTCompUnitMMUFSM(LDSTCompUnit):
  84
  85     def __init__(self, rwid, pspec):
  86         from soc.experiment.l0_cache import TstL0CacheBuffer
  87         self.l0 = l0 = TstL0CacheBuffer(pspec)
  88         pi = l0.l0.dports[0]
  89         LDSTCompUnit.__init__(self, pi, rwid, 4)
  90
  91     def elaborate(self, platform):
  92         m = LDSTCompUnit.elaborate(self, platform)
  93         m.submodules.l0 = self.l0
  94         # link addr-go direct to rel
  95         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  96         return m
  97
  98
  99 def test_scoreboard_mmu():
 100
 101     units = {}
 102     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 103                          imem_ifacetype='bare_wb',
 104                          addr_wid=48,
 105                          mask_wid=8,
 106                          reg_wid=64,
 107                          units=units)
 108
 109     dut = TestLDSTCompUnit(16,pspec)
 110     vl = rtlil.convertMMUFSM(dut, ports=dut.ports())
 111     with open("test_ldst_comp_mmu1.il", "w") as f:
 112         f.write(vl)
 113
 114     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 115
 116 ########################################
 117 class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
 118
 119     def __init__(self, pspec):
 120         from soc.experiment.l0_cache import TstL0CacheBuffer
 121         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 122         regspec = LDSTPipeSpec.regspec
 123
 124         # use a LoadStore1 here
 125
 126         cmpi = ConfigMemoryPortInterface(pspec)
 127         self.cmpi = cmpi
 128         ldst = cmpi.pi
 129         self.l0 = ldst
 130
 131         self.mmu = MMU()
 132
 133         pipe_spec = MMUPipeSpec(id_wid=2)
 134         self.fsm = FSMMMUStage(pipe_spec)
 135
 136         self.fsm.set_ldst_interface(ldst)
 137
 138         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
 139
 140     def elaborate(self, platform):
 141         m = LDSTCompUnit.elaborate(self, platform)
 142         m.submodules.l0 = self.l0
 143         m.submodules.mmu = self.mmu
 144         m.submodules.fsm = self.fsm
 145         # link addr-go direct to rel
 146         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 147
 148         # link mmu and dcache together
 149         dcache = self.l0.dcache
 150         mmu = self.mmu
 151         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 152         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 153
 154         return m
 155
 156 def test_scoreboard_regspec_mmufsm():
 157
 158     m = Module()
 159
 160     units = {}
 161     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 162                          imem_ifacetype='bare_wb',
 163                          addr_wid=48,
 164                          mask_wid=8,
 165                          reg_wid=64,
 166                          units=units)
 167
 168     dut = TestLDSTCompUnitRegSpecMMUFSM(pspec)
 169
 170     m.submodules.dut = dut
 171
 172     sim = Simulator(m)
 173     sim.add_clock(1e-6)
 174
 175     dut.mem = pagetables.test1
 176     dut.stop = False
 177
 178     sim.add_sync_process(wrap(ldst_sim(dut))) # rename ?
 179     sim.add_sync_process(wrap(wb_get(dut)))
 180     with sim.write_vcd('test_scoreboard_regspec_mmufsm.vcd'):
 181         sim.run()
 182
 183
 184 if __name__ == '__main__':
 185     test_scoreboard_regspec_mmufsm()
 186     #only one test for now -- test_scoreboard_mmu()