1 """DCache PortInterface Test
2 starting as a copy to test_ldst_pi.py
5 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
6 from nmigen
.cli
import main
7 from nmigen
.cli
import rtlil
8 from nmutil
.mask
import Mask
, masked
9 from nmutil
.util
import Display
10 from random
import randint
, seed
11 from nmigen
.sim
import Simulator
, Delay
, Settle
12 from nmutil
.util
import wrap
14 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
15 from soc
.config
.test
.test_loadstore
import TestMemPspec
16 from soc
.config
.loadstore
import ConfigMemoryPortInterface
18 from soc
.fu
.ldst
.loadstore
import LoadStore1
19 from soc
.experiment
.mmu
import MMU
20 from soc
.experiment
.test
import pagetables
22 from nmigen
.compat
.sim
import run_simulation
23 from openpower
.test
.wb_get
import wb_get
24 from openpower
.test
import wb_get
as wbget
25 from openpower
.decoder
.power_enums
import MSRSpec
34 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
37 #disable_cache=True, # hmmm...
43 cmpi
= ConfigMemoryPortInterface(pspec
)
44 m
.submodules
.ldst
= ldst
= cmpi
.pi
45 m
.submodules
.mmu
= mmu
= MMU()
48 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
49 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
51 # link mmu and dcache together
52 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
53 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
55 # link ldst and MMU together
56 comb
+= l_in
.eq(ldst
.m_out
)
57 comb
+= ldst
.m_in
.eq(l_out
)
61 ### test case for dcbz
63 def _test_dcbz_addr_100e0(dut
, mem
):
64 mmu
= dut
.submodules
.mmu
65 pi
= dut
.submodules
.ldst
.pi
68 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
72 data
= 0xf553b658ba7e1f51
74 msr
= MSRSpec(pr
=1, dr
=0, sf
=1) # 64 bit by default
76 yield from pi_st(pi
, addr
, data
, 8, msr
)
79 ld_data
, _
, _
= yield from pi_ld(pi
, addr
, 8, msr
)
80 assert ld_data
== 0xf553b658ba7e1f51
81 ld_data
, _
, _
= yield from pi_ld(pi
, addr
, 8, msr
)
82 assert ld_data
== 0xf553b658ba7e1f51
84 print("do_dcbz ===============")
85 yield from pi_st(pi
, addr
, data
, 8, msr
, is_dcbz
=1)
86 print("done_dcbz ===============")
89 ld_data
, _
, _
= yield from pi_ld(pi
, addr
, 8, msr
)
90 print("ld_data after dcbz")
97 def test_dcbz_addr_100e0():
101 mem
= pagetables
.test1
107 sim
.add_sync_process(wrap(_test_dcbz_addr_100e0(m
, mem
)))
108 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus(), mem
)))
109 with sim
.write_vcd('test_dcbz_addr_zero.vcd'):
112 if __name__
== '__main__':
113 test_dcbz_addr_100e0()