src/soc/experiment/test/test_ldst_pi_misalign.py

   1 """MMU PortInterface Test
   2
   3 quite basic, goes directly to the MMU to assert signals (does not
   4 yet use PortInterface)
   5 """
   6
   7 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   8 from nmigen.cli import main
   9 from nmigen.cli import rtlil
  10 from nmutil.mask import Mask, masked
  11 from nmutil.util import Display
  12
  13 if True:
  14     from nmigen.back.pysim import Simulator, Delay, Settle
  15 else:
  16     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  17 from nmutil.util import wrap
  18
  19 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.config.loadstore import ConfigMemoryPortInterface
  22
  23 from soc.fu.ldst.loadstore import LoadStore1
  24 from soc.experiment.mmu import MMU
  25
  26 from nmigen.compat.sim import run_simulation
  27 from openpower.test.wb_get import wb_get
  28 from openpower.test import wb_get as wbget
  29
  30 msr_default = MSRSpec(pr=1, dr=0, sf=1) # 64 bit by default
  31
  32
  33 wbget.stop = False
  34
  35 def b(x): # byte-reverse function
  36     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  37                           byteorder='big', signed=False)
  38
  39
  40 def setup_mmu():
  41
  42     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  43                          imem_ifacetype='',
  44                          addr_wid=48,
  45                          #disable_cache=True, # hmmm...
  46                          mask_wid=8,
  47                          reg_wid=64)
  48
  49     m = Module()
  50     comb = m.d.comb
  51     cmpi = ConfigMemoryPortInterface(pspec)
  52     m.submodules.ldst = ldst = cmpi.pi
  53     m.submodules.mmu = mmu = MMU()
  54     dcache = ldst.dcache
  55
  56     l_in, l_out = mmu.l_in, mmu.l_out
  57     d_in, d_out = dcache.d_in, dcache.d_out
  58
  59     # link mmu and dcache together
  60     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  61     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
  62
  63     # link ldst and MMU together
  64     comb += l_in.eq(ldst.m_out)
  65     comb += ldst.m_in.eq(l_out)
  66
  67     return m, cmpi
  68
  69
  70
  71 def ldst_sim_misalign(dut):
  72     mmu = dut.submodules.mmu
  73     wbget.stop = False
  74
  75     yield mmu.rin.prtbl.eq(0x1000000) # set process table
  76     yield
  77
  78     # load 8 bytes at aligned address
  79     align_addr = 0x1000
  80     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  81                                           align_addr, 8, msr=msr_default)
  82     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  83     assert data == 0xdeadbeef01234567
  84
  85     # load 4 bytes at aligned address
  86     align_addr = 0x1004
  87     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  88                                           align_addr, 4, msr=msr_default)
  89     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  90     assert data == 0xdeadbeef
  91
  92     # load 8 bytes at *mis*-aligned address
  93     misalign_addr = 0x1004
  94     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  95                                           misalign_addr, 8, msr=msr_default)
  96     print ("ldst_sim_misalign", data, exctype, exc)
  97     yield
  98     dar = yield dut.submodules.ldst.dar
  99     print ("DAR", hex(dar))
 100     assert dar == misalign_addr
 101     # check exception bits
 102     assert exc.happened
 103     assert exc.alignment
 104     assert not exc.segment_fault
 105     assert not exc.instr_fault
 106     assert not exc.invalid
 107     assert not exc.perm_error
 108     assert not exc.rc_error
 109     assert not exc.badtree
 110
 111     wbget.stop = True
 112
 113
 114 def test_misalign_mmu():
 115
 116     m, cmpi = setup_mmu()
 117
 118     # virtual "memory" to use for this test
 119
 120     mem = {0x10000:    # PARTITION_TABLE_2
 121                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
 122            b(0x800000000100000b),
 123
 124            0x30000:     # RADIX_ROOT_PTE
 125                         # V = 1 L = 0 NLB = 0x400 NLS = 9
 126            b(0x8000000000040009),
 127
 128            0x40000:     # RADIX_SECOND_LEVEL
 129                         #          V = 1 L = 1 SW = 0 RPN = 0
 130                            # R = 1 C = 1 ATT = 0 EAA 0x7
 131            b(0xc000000000000183),
 132
 133           0x1000000:   # PROCESS_TABLE_3
 134                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
 135            b(0x40000000000300ad),
 136
 137          # data to return
 138           0x1000: 0xdeadbeef01234567,
 139           0x1008: 0xfeedf00ff001a5a5
 140           }
 141
 142
 143     # nmigen Simulation
 144     sim = Simulator(m)
 145     sim.add_clock(1e-6)
 146
 147     sim.add_sync_process(wrap(ldst_sim_misalign(m)))
 148     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 149     with sim.write_vcd('test_ldst_pi_misalign.vcd'):
 150         sim.run()
 151
 152
 153 if __name__ == '__main__':
 154     test_misalign_mmu()