src/soc/experiment/test/test_loadstore1.py

   1 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   2 from nmigen.cli import main
   3 from nmigen.cli import rtlil
   4 from nmutil.mask import Mask, masked
   5 from nmutil.util import Display
   6 from random import randint, seed
   7 from nmigen.sim import Simulator, Delay, Settle
   8 from nmutil.util import wrap
   9
  10 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, wait_busy
  11 #from soc.config.test.test_pi2ls import pi_st_debug
  12 from soc.config.test.test_loadstore import TestMemPspec
  13 from soc.config.loadstore import ConfigMemoryPortInterface
  14
  15 from soc.fu.ldst.loadstore import LoadStore1
  16 from soc.experiment.mmu import MMU
  17 from soc.experiment.test import pagetables
  18
  19 from nmigen.compat.sim import run_simulation
  20 from random import random
  21
  22 stop = False
  23
  24 def wb_get(wb, mem):
  25     """simulator process for getting memory load requests
  26     """
  27
  28     global stop
  29     assert(stop==False)
  30
  31     while not stop:
  32         while True: # wait for dc_valid
  33             if stop:
  34                 return
  35             cyc = yield (wb.cyc)
  36             stb = yield (wb.stb)
  37             if cyc and stb:
  38                 break
  39             yield
  40         addr = (yield wb.adr) << 3
  41         if addr not in mem:
  42             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  43
  44         # read or write?
  45         we = (yield wb.we)
  46         if we:
  47             store = (yield wb.dat_w)
  48             sel = (yield wb.sel)
  49             data = mem.get(addr, 0)
  50             # note we assume 8-bit sel, here
  51             res = 0
  52             for i in range(8):
  53                 mask = 0xff << (i*8)
  54                 if sel & (1<<i):
  55                     res |= store & mask
  56                 else:
  57                     res |= data & mask
  58             mem[addr] = res
  59             print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
  60         else:
  61             data = mem.get(addr, 0)
  62             yield wb.dat_r.eq(data)
  63             print ("    DCACHE get %x data %x" % (addr, data))
  64
  65         yield wb.ack.eq(1)
  66         yield
  67         yield wb.ack.eq(0)
  68         yield
  69
  70 def setup_mmu():
  71
  72     global stop
  73     stop = False
  74
  75     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  76                          imem_ifacetype='',
  77                          addr_wid=48,
  78                          #disable_cache=True, # hmmm...
  79                          mask_wid=8,
  80                          reg_wid=64)
  81
  82     m = Module()
  83     comb = m.d.comb
  84     cmpi = ConfigMemoryPortInterface(pspec)
  85     m.submodules.ldst = ldst = cmpi.pi
  86     m.submodules.mmu = mmu = MMU()
  87     dcache = ldst.dcache
  88
  89     l_in, l_out = mmu.l_in, mmu.l_out
  90     d_in, d_out = dcache.d_in, dcache.d_out
  91     wb_out, wb_in = dcache.wb_out, dcache.wb_in
  92
  93     # link mmu and dcache together
  94     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  95     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
  96
  97     # link ldst and MMU together
  98     comb += l_in.eq(ldst.m_out)
  99     comb += ldst.m_in.eq(l_out)
 100
 101     return m, cmpi
 102
 103 test_exceptions = False
 104 test_dcbz = False
 105 test_random = True
 106
 107 def _test_loadstore1_invalid(dut, mem):
 108     mmu = dut.submodules.mmu
 109     pi = dut.submodules.ldst.pi
 110     global stop
 111     stop = False
 112
 113     print("=== test invalid ===")
 114
 115     addr = 0
 116     ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 117     print("ld_data",ld_data,exc)
 118     assert(exc=="slow")
 119     invalid = yield pi.exc_o.invalid
 120     assert(invalid==1)
 121
 122     print("=== test invalid done ===")
 123
 124     stop = True
 125
 126
 127 def _test_loadstore1(dut, mem):
 128     mmu = dut.submodules.mmu
 129     pi = dut.submodules.ldst.pi
 130     global stop
 131     stop = False
 132
 133     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 134     yield
 135
 136     addr = 0x100e0
 137     data = 0xf553b658ba7e1f51
 138
 139     if test_dcbz:
 140         yield from pi_st(pi, addr, data, 8, msr_pr=1)
 141         yield
 142
 143         ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 144         assert ld_data == 0xf553b658ba7e1f51
 145         assert exc is None
 146         ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 147         assert ld_data == 0xf553b658ba7e1f51
 148         assert exc is None
 149
 150         print("do_dcbz ===============")
 151         yield from pi_st(pi, addr, data, 8, msr_pr=1, is_dcbz=1)
 152         print("done_dcbz ===============")
 153         yield
 154
 155         ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 156         print("ld_data after dcbz")
 157         print(ld_data)
 158         assert ld_data == 0
 159         assert exc is None
 160
 161     if test_exceptions:
 162         print("=== alignment error (ld) ===")
 163         addr = 0xFF100e0FF
 164         ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 165         alignment = yield pi.exc_o.alignment
 166         happened = yield pi.exc_o.happened
 167         dar = yield pi.dar_o
 168         assert(happened==1)
 169         assert(alignment==1)
 170         assert(dar==addr)
 171         assert(exc=="fast")
 172         yield from wait_busy(pi, debug="pi_ld_E_alignment_error")
 173         # wait is only needed in case of in exception here
 174         print("=== alignment error test passed (ld) ===")
 175
 176         print("=== alignment error (st) ===")
 177         addr = 0xFF100e0FF
 178         exc = yield from pi_st(pi, addr,0, 8, msr_pr=1)
 179         alignment = yield pi.exc_o.alignment
 180         happened = yield pi.exc_o.happened
 181         dar = yield pi.dar_o
 182         assert(happened==1)
 183         assert(alignment==1)
 184         assert(dar==addr)
 185         assert(exc=="fast")
 186         yield from wait_busy(pi, debug="pi_st_E_alignment_error")
 187         # wait is only needed in case of in exception here
 188         print("=== alignment error test passed (st) ===")
 189         yield # IMPORTANT: wait one clock cycle after failed st
 190
 191         print("=== no error ===")
 192         addr = 0x100e0
 193         ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 194         print("ld_data",ld_data,exc)
 195         print("=== no error done ===")
 196
 197     if test_random:
 198         addrs = [0x456920,0xa7a180,0x299420,0x1d9d60] # known to cause an error
 199         count = 0
 200
 201         for addr in addrs:
 202             print("== RANDOM addr ==",hex(addr))
 203             ld_data, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
 204             print("ld_data[RANDOM]",ld_data,exc,addr)
 205             #if exc=="wait_ldok_infinite_loop": # break cond for debugging
 206             #    print("wait_ldok_infinite_loop:break",count)
 207             #    break
 208             assert(exc==None)
 209             count = count + 1
 210
 211         print("== RANDOM addr done ==")
 212
 213     stop = True
 214
 215 def test_loadstore1():
 216
 217     m, cmpi = setup_mmu()
 218
 219     mem = pagetables.test1
 220
 221     # nmigen Simulation
 222     sim = Simulator(m)
 223     sim.add_clock(1e-6)
 224
 225     sim.add_sync_process(wrap(_test_loadstore1(m, mem)))
 226     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 227     with sim.write_vcd('test_loadstore1.vcd'):
 228         sim.run()
 229
 230 def test_loadstore1_invalid():
 231
 232     m, cmpi = setup_mmu()
 233
 234     mem = {}
 235
 236     # nmigen Simulation
 237     sim = Simulator(m)
 238     sim.add_clock(1e-6)
 239
 240     sim.add_sync_process(wrap(_test_loadstore1_invalid(m, mem)))
 241     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 242     with sim.write_vcd('test_loadstore1_invalid.vcd'):
 243         sim.run()
 244
 245 if __name__ == '__main__':
 246     test_loadstore1()
 247     test_loadstore1_invalid()