src/soc/fu/div/test/helper.py

   1 import random
   2 import unittest
   3 import power_instruction_analyzer as pia
   4 from nmigen import Module, Signal
   5
   6 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   7 # Also, check out the cxxsim nmigen branch, and latest yosys from git
   8 from nmutil.sim_tmp_alternative import Simulator, Delay
   9
  10 from soc.decoder.power_decoder import (create_pdecode)
  11 from soc.decoder.power_decoder2 import (PowerDecode2)
  12 from soc.decoder.power_enums import XER_bits, Function
  13 from soc.decoder.isa.all import ISA
  14 from soc.config.endian import bigendian
  15
  16 from soc.fu.test.common import ALUHelpers
  17 from soc.fu.div.pipeline import DivBasePipe
  18 from soc.fu.div.pipe_data import DivPipeSpec
  19
  20
  21 def log_rand(n, min_val=1):
  22     logrange = random.randint(1, n)
  23     return random.randint(min_val, (1 << logrange)-1)
  24
  25
  26 def get_cu_inputs(dec2, sim):
  27     """naming (res) must conform to DivFunctionUnit input regspec
  28     """
  29     res = {}
  30
  31     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  32     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  33     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  34
  35     print("alu get_cu_inputs", res)
  36
  37     return res
  38
  39
  40 def pia_res_to_output(pia_res):
  41     retval = {}
  42     if pia_res.rt is not None:
  43         retval["o"] = pia_res.rt
  44     if pia_res.cr0 is not None:
  45         cr0 = pia_res.cr0
  46         v = 0
  47         if cr0.lt:
  48             v |= 8
  49         if cr0.gt:
  50             v |= 4
  51         if cr0.eq:
  52             v |= 2
  53         if cr0.so:
  54             v |= 1
  55         retval["cr_a"] = v
  56     if pia_res.overflow is not None:
  57         overflow = pia_res.overflow
  58         v = 0
  59         if overflow.ov:
  60             v |= 1
  61         if overflow.ov32:
  62             v |= 2
  63         retval["xer_ov"] = v
  64         retval["xer_so"] = overflow.so
  65     else:
  66         retval["xer_ov"] = 0
  67         retval["xer_so"] = 0
  68     return retval
  69
  70
  71 def set_alu_inputs(alu, dec2, sim):
  72     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  73     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  74     # and place it into data_i.b
  75
  76     inp = yield from get_cu_inputs(dec2, sim)
  77     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  78     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  79
  80     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  81
  82     overflow = None
  83     if 'xer_so' in inp:
  84         so = inp['xer_so']
  85         overflow = pia.OverflowFlags(so=bool(so),
  86                                      ov=False,
  87                                      ov32=False)
  88     return pia.InstructionInput(ra=inp["ra"], rb=inp["rb"], overflow=overflow)
  89
  90
  91 class DivTestHelper(unittest.TestCase):
  92     def execute(self, alu, instruction, pdecode2, test, div_pipe_kind, sim):
  93         prog = test.program
  94         isa_sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
  95                       test.mem, test.msr,
  96                       bigendian=bigendian)
  97         gen = prog.generate_instructions()
  98         instructions = list(zip(gen, prog.assembly.splitlines()))
  99         yield Delay(0.1e-6)
 100
 101         index = isa_sim.pc.CIA.value//4
 102         while index < len(instructions):
 103             ins, code = instructions[index]
 104
 105             print("instruction: 0x{:X}".format(ins & 0xffffffff))
 106             print(code)
 107             spr = isa_sim.spr
 108             if 'XER' in spr:
 109                 so = 1 if spr['XER'][XER_bits['SO']] else 0
 110                 ov = 1 if spr['XER'][XER_bits['OV']] else 0
 111                 ov32 = 1 if spr['XER'][XER_bits['OV32']] else 0
 112                 print("before: so/ov/32", so, ov, ov32)
 113
 114             # ask the decoder to decode this binary data (endian'd)
 115             # little / big?
 116             yield pdecode2.dec.bigendian.eq(bigendian)
 117             yield instruction.eq(ins)          # raw binary instr.
 118             yield Delay(0.1e-6)
 119             fn_unit = yield pdecode2.e.do.fn_unit
 120             self.assertEqual(fn_unit, Function.DIV.value)
 121             pia_inputs = yield from set_alu_inputs(alu, pdecode2,
 122                                                    isa_sim)
 123
 124             # set valid for one cycle, propagate through pipeline..
 125             # note that it is critically important to do this
 126             # for DIV otherwise it starts trying to produce
 127             # multiple results.
 128             yield alu.p.valid_i.eq(1)
 129             yield
 130             yield alu.p.valid_i.eq(0)
 131
 132             opname = code.split(' ')[0]
 133             fnname = opname.replace(".", "_")
 134             print(f"{fnname}({pia_inputs})")
 135             pia_res = getattr(
 136                 pia, opname.replace(".", "_"))(pia_inputs)
 137             print(f"-> {pia_res}")
 138
 139             yield from isa_sim.call(opname)
 140             index = isa_sim.pc.CIA.value//4
 141
 142             vld = yield alu.n.valid_o
 143             while not vld:
 144                 yield
 145                 yield Delay(0.1e-6)
 146                 # XXX sim._engine is an internal variable
 147                 # Waiting on https://github.com/nmigen/nmigen/issues/443
 148                 try:
 149                     print(f"time: {sim._engine.now * 1e6}us")
 150                 except AttributeError:
 151                     pass
 152                 vld = yield alu.n.valid_o
 153                 # bug #425 investigation
 154                 do = alu.pipe_end.div_out
 155                 ctx_op = do.i.ctx.op
 156                 is_32bit = yield ctx_op.is_32bit
 157                 is_signed = yield ctx_op.is_signed
 158                 quotient_root = yield do.i.core.quotient_root
 159                 quotient_65 = yield do.quotient_65
 160                 dive_abs_ov32 = yield do.i.dive_abs_ov32
 161                 div_by_zero = yield do.i.div_by_zero
 162                 quotient_neg = yield do.quotient_neg
 163                 print("32bit", hex(is_32bit))
 164                 print("signed", hex(is_signed))
 165                 print("quotient_root", hex(quotient_root))
 166                 print("quotient_65", hex(quotient_65))
 167                 print("div_by_zero", hex(div_by_zero))
 168                 print("dive_abs_ov32", hex(dive_abs_ov32))
 169                 print("quotient_neg", hex(quotient_neg))
 170                 print("vld", vld)
 171                 print("")
 172
 173             yield Delay(0.1e-6)
 174             # XXX sim._engine is an internal variable
 175             # Waiting on https://github.com/nmigen/nmigen/issues/443
 176             try:
 177                 print(f"check time: {sim._engine.now * 1e6}us")
 178             except AttributeError:
 179                 pass
 180             msg = "%s: %s" % (div_pipe_kind.name, code)
 181             msg += " %s" % (repr(prog.assembly))
 182             msg += " %s" % (repr(test.regs))
 183             yield from self.check_alu_outputs(alu, pdecode2,
 184                                               isa_sim, msg,
 185                                               pia_res)
 186             yield
 187
 188     def run_all(self, test_data, div_pipe_kind, file_name_prefix):
 189         m = Module()
 190         comb = m.d.comb
 191         instruction = Signal(32)
 192
 193         pdecode = create_pdecode()
 194
 195         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 196
 197         pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
 198         m.submodules.alu = alu = DivBasePipe(pspec)
 199
 200         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 201         comb += alu.n.ready_i.eq(1)
 202         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 203         sim = Simulator(m)
 204
 205         sim.add_clock(1e-6)
 206
 207         def process():
 208             for test in test_data:
 209                 print(test.name)
 210                 with self.subTest(test.name):
 211                     yield from self.execute(alu, instruction, pdecode2,
 212                                             test, div_pipe_kind, sim)
 213
 214         sim.add_sync_process(process)
 215         with sim.write_vcd(f"{file_name_prefix}_{div_pipe_kind.name}.vcd"):
 216             sim.run()
 217
 218     def check_alu_outputs(self, alu, dec2, sim, code, pia_res):
 219
 220         rc = yield dec2.e.do.rc.data
 221         cridx_ok = yield dec2.e.write_cr.ok
 222         cridx = yield dec2.e.write_cr.data
 223
 224         print("check extra output", repr(code), cridx_ok, cridx)
 225         if rc:
 226             self.assertEqual(cridx, 0, code)
 227
 228         sim_o = {}
 229         res = {}
 230
 231         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 232         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 233         yield from ALUHelpers.get_int_o(res, alu, dec2)
 234         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 235
 236         print("res output", res)
 237
 238         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 239         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 240         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 241         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 242
 243         print("sim output", sim_o)
 244
 245         print("power-instruction-analyzer result:")
 246         print(pia_res)
 247         if pia_res is not None:
 248             with self.subTest(check="pia", sim_o=sim_o, pia_res=str(pia_res)):
 249                 pia_o = pia_res_to_output(pia_res)
 250                 ALUHelpers.check_int_o(self, res, pia_o, code)
 251                 ALUHelpers.check_cr_a(self, res, pia_o, code)
 252                 ALUHelpers.check_xer_ov(self, res, pia_o, code)
 253                 ALUHelpers.check_xer_so(self, res, pia_o, code)
 254
 255         with self.subTest(check="sim", sim_o=sim_o, pia_res=str(pia_res)):
 256             ALUHelpers.check_int_o(self, res, sim_o, code)
 257             ALUHelpers.check_cr_a(self, res, sim_o, code)
 258             ALUHelpers.check_xer_ov(self, res, sim_o, code)
 259             ALUHelpers.check_xer_so(self, res, sim_o, code)
 260
 261         oe = yield dec2.e.do.oe.oe
 262         oe_ok = yield dec2.e.do.oe.ok
 263         print("oe, oe_ok", oe, oe_ok)
 264         if not oe or not oe_ok:
 265             # if OE not enabled, XER SO and OV must not be activated
 266             so_ok = yield alu.n.data_o.xer_so.ok
 267             ov_ok = yield alu.n.data_o.xer_ov.ok
 268             print("so, ov", so_ok, ov_ok)
 269             self.assertEqual(ov_ok, False, code)
 270             self.assertEqual(so_ok, False, code)