src/soc/fu/div/test/test_pipe_caller.py

   1 import random
   2 import unittest
   3 from soc.simulator.program import Program
   4 from soc.config.endian import bigendian
   5
   6 from soc.fu.test.common import (TestCase, TestAccumulatorBase, skip_case)
   7 from soc.fu.div.pipe_data import DivPipeKind
   8
   9 from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
  10                                     set_alu_inputs, DivTestHelper)
  11
  12
  13 class DivTestCases(TestAccumulatorBase):
  14     def case_divwe_regression(self):
  15         # div FU and power-instruction-analyzer both correctly return 0
  16         # hitting behavior undefined by Power v3.1 spec, need to adjust
  17         # simulator API to tell tests that the simulator's output doesn't
  18         # need to completely match
  19         lst = [f"divwe 3, 1, 2"]
  20         initial_regs = [0] * 32
  21         initial_regs[1] = 1
  22         initial_regs[2] = 1
  23         with Program(lst, bigendian) as prog:
  24             self.add_case(prog, initial_regs)
  25
  26     def case_divwe__regression(self):
  27         lst = ["divwe. 3, 1, 2"]
  28         initial_regs = [0] * 32
  29         with Program(lst, bigendian) as prog:
  30             self.add_case(prog, initial_regs)
  31
  32     def case_divw_regression(self):
  33         # simulator is wrong, FSM and power-instruction-analyzer both correct
  34         lst = [f"divw 0, 1, 2"]
  35         initial_regs = [0] * 32
  36         initial_regs[2] = 0x2
  37         initial_regs[1] = 0x80000000
  38         with Program(lst, bigendian) as prog:
  39             self.add_case(prog, initial_regs)
  40
  41     # modulo
  42     def case_modsd_regression2(self):
  43         lst = [f"modsd 0, 1, 2"]
  44         initial_regs = [0] * 32
  45         initial_regs[2] = 0xff
  46         initial_regs[1] = 0x7fffffffffffffff
  47         with Program(lst, bigendian) as prog:
  48             self.add_case(prog, initial_regs)
  49
  50     # modulo
  51     def case_modsd_regression(self):
  52         lst = [f"modsd 17, 27, 0"]
  53         initial_regs = [0] * 32
  54         initial_regs[0] = 0xff
  55         initial_regs[27] = 0x7fffffffffffffff
  56         with Program(lst, bigendian) as prog:
  57             self.add_case(prog, initial_regs)
  58
  59     def case_divduo_regression(self):
  60         lst = [f"divduo. 11, 20, 6"]
  61         initial_regs = [0] * 32
  62         # gpr: 00ff00ff00ff0080 <- r6
  63         # gpr: 000000000000007f <- r11
  64         # gpr: 7f6e5d4c3b2a1908 <- r20
  65         initial_regs[6] = 0x00ff00ff00ff0080
  66         initial_regs[20] = 0x7f6e5d4c3b2a1908
  67         with Program(lst, bigendian) as prog:
  68             self.add_case(prog, initial_regs)
  69
  70     def case_0_regression(self):
  71         for i in range(40):
  72             lst = ["divwo 3, 1, 2"]
  73             initial_regs = [0] * 32
  74             initial_regs[1] = 0xbc716835f32ac00c
  75             initial_regs[2] = 0xcdf69a7f7042db66
  76             with Program(lst, bigendian) as prog:
  77                 self.add_case(prog, initial_regs)
  78
  79     def case_1_regression(self):
  80         lst = ["divwo 3, 1, 2"]
  81         initial_regs = [0] * 32
  82         initial_regs[1] = 0x10000000000000000-4
  83         initial_regs[2] = 0x10000000000000000-2
  84         with Program(lst, bigendian) as prog:
  85             self.add_case(prog, initial_regs)
  86
  87     def case_2_regression(self):
  88         lst = ["divwo 3, 1, 2"]
  89         initial_regs = [0] * 32
  90         initial_regs[1] = 0xffffffffffff9321
  91         initial_regs[2] = 0xffffffffffff7012
  92         with Program(lst, bigendian) as prog:
  93             self.add_case(prog, initial_regs)
  94
  95     def case_3_regression(self):
  96         lst = ["divwo. 3, 1, 2"]
  97         initial_regs = [0] * 32
  98         initial_regs[1] = 0x1b8e32f2458746af
  99         initial_regs[2] = 0x6b8aee2ccf7d62e9
 100         with Program(lst, bigendian) as prog:
 101             self.add_case(prog, initial_regs)
 102
 103     def case_4_regression(self):
 104         lst = ["divw 3, 1, 2"]
 105         initial_regs = [0] * 32
 106         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 107         initial_regs[2] = 0xe730c2eed6cc8dd7
 108         with Program(lst, bigendian) as prog:
 109             self.add_case(prog, initial_regs)
 110
 111     def case_5_regression(self):
 112         lst = ["divw 3, 1, 2",
 113                "divwo. 6, 4, 5"]
 114         initial_regs = [0] * 32
 115         initial_regs[1] = 0x1c4e6c2f3aa4a05c
 116         initial_regs[2] = 0xe730c2eed6cc8dd7
 117         initial_regs[4] = 0x1b8e32f2458746af
 118         initial_regs[5] = 0x6b8aee2ccf7d62e9
 119         with Program(lst, bigendian) as prog:
 120             self.add_case(prog, initial_regs)
 121
 122     def case_6_regression(self):
 123         # CR0 not getting set properly for this one
 124         # turns out that overflow is not set correctly in
 125         # fu/div/output_stage.py calc_overflow
 126         # https://bugs.libre-soc.org/show_bug.cgi?id=425
 127         lst = ["divw. 3, 1, 2"]
 128         initial_regs = [0] * 32
 129         initial_regs[1] = 0x61c1cc3b80f2a6af
 130         initial_regs[2] = 0x9dc66a7622c32bc0
 131         with Program(lst, bigendian) as prog:
 132             self.add_case(prog, initial_regs)
 133
 134     def case_7_regression(self):
 135         # https://bugs.libre-soc.org/show_bug.cgi?id=425
 136         lst = ["divw. 3, 1, 2"]
 137         initial_regs = [0] * 32
 138         initial_regs[1] = 0xf1791627e05e8096
 139         initial_regs[2] = 0xffc868bf4573da0b
 140         with Program(lst, bigendian) as prog:
 141             self.add_case(prog, initial_regs)
 142
 143     def case_8_fsm_regression(self):  # FSM result is "36" not 6
 144         lst = ["divwu. 3, 1, 2"]
 145         initial_regs = [0] * 32
 146         initial_regs[1] = 18
 147         initial_regs[2] = 3
 148         with Program(lst, bigendian) as prog:
 149             self.add_case(prog, initial_regs)
 150
 151     def case_9_regression(self):  # CR0 fails: expected 0b10, actual 0b11
 152         lst = ["divw. 3, 1, 2"]
 153         initial_regs = [0] * 32
 154         initial_regs[1] = 1
 155         initial_regs[2] = 0
 156         with Program(lst, bigendian) as prog:
 157             self.add_case(prog, initial_regs)
 158
 159     def case_10_regression(self):  # overflow fails
 160         lst = ["divwo 3, 1, 2"]
 161         initial_regs = [0] * 32
 162         initial_regs[1] = 0xbc716835f32ac00c
 163         initial_regs[2] = 0xcdf69a7f7042db66
 164         with Program(lst, bigendian) as prog:
 165             self.add_case(prog, initial_regs)
 166
 167     def case_11_regression(self):
 168         lst = ["divwo. 3, 1, 2"]
 169         initial_regs = [0] * 32
 170         initial_regs[1] = 0xffffffffffffffff
 171         initial_regs[2] = 0xffffffffffffffff
 172         with Program(lst, bigendian) as prog:
 173             self.add_case(prog, initial_regs)
 174
 175     def case_divw_by_zero_1(self):
 176         lst = ["divw. 3, 1, 2"]
 177         initial_regs = [0] * 32
 178         initial_regs[1] = 0x1
 179         initial_regs[2] = 0x0
 180         with Program(lst, bigendian) as prog:
 181             self.add_case(prog, initial_regs)
 182
 183     def case_divw_overflow2(self):
 184         lst = ["divw. 3, 1, 2"]
 185         initial_regs = [0] * 32
 186         initial_regs[1] = 0x80000000
 187         initial_regs[2] = 0xffffffffffffffff  # top bits don't seem to matter
 188         with Program(lst, bigendian) as prog:
 189             self.add_case(prog, initial_regs)
 190
 191     def case_divw_overflow3(self):
 192         lst = ["divw. 3, 1, 2"]
 193         initial_regs = [0] * 32
 194         initial_regs[1] = 0x80000000
 195         initial_regs[2] = 0xffffffff
 196         with Program(lst, bigendian) as prog:
 197             self.add_case(prog, initial_regs)
 198
 199     def case_divwuo_regression_1(self):
 200         lst = ["divwuo. 3, 1, 2"]
 201         initial_regs = [0] * 32
 202         initial_regs[1] = 0x7591a398c4e32b68
 203         initial_regs[2] = 0x48674ab432867d69
 204         with Program(lst, bigendian) as prog:
 205             self.add_case(prog, initial_regs)
 206
 207     def case_divwuo_1(self):
 208         lst = ["divwuo. 3, 1, 2"]
 209         initial_regs = [0] * 32
 210         initial_regs[1] = 0x50
 211         initial_regs[2] = 0x2
 212         with Program(lst, bigendian) as prog:
 213             self.add_case(prog, initial_regs)
 214
 215     def case_rand_divwu(self):
 216         insns = ["divwu", "divwu.", "divwuo", "divwuo."]
 217         for i in range(40):
 218             choice = random.choice(insns)
 219             lst = [f"{choice} 3, 1, 2"]
 220             initial_regs = [0] * 32
 221             initial_regs[1] = log_rand(32)
 222             initial_regs[2] = log_rand(32)
 223             with Program(lst, bigendian) as prog:
 224                 self.add_case(prog, initial_regs)
 225
 226     def case_rand_divw(self):
 227         insns = ["divw", "divw.", "divwo", "divwo."]
 228         for i in range(40):
 229             choice = random.choice(insns)
 230             lst = [f"{choice} 3, 1, 2"]
 231             initial_regs = [0] * 32
 232             initial_regs[1] = log_rand(32)
 233             initial_regs[2] = log_rand(32)
 234             with Program(lst, bigendian) as prog:
 235                 self.add_case(prog, initial_regs)
 236
 237
 238 class TestPipe(DivTestHelper):
 239     def test_div_pipe_core(self):
 240         self.run_all(DivTestCases().test_data,
 241                      DivPipeKind.DivPipeCore, "div_pipe_caller")
 242
 243     def test_fsm_div_core(self):
 244         self.run_all(DivTestCases().test_data,
 245                      DivPipeKind.FSMDivCore, "div_pipe_caller")
 246
 247     def test_sim_only(self):
 248         self.run_all(DivTestCases().test_data,
 249                      DivPipeKind.SimOnly, "div_pipe_caller")
 250
 251
 252 if __name__ == "__main__":
 253     unittest.main()