e36286019ac4a341a53a925056d73a8037ad6188
3 based on microwatt loadstore1.vhdl, but conforming to PortInterface.
4 unlike loadstore1.vhdl this does *not* deal with actual Load/Store
5 ops: that job is handled by LDSTCompUnit, which talks to LoadStore1
6 by way of PortInterface. PortInterface is where things need extending,
7 such as adding dcbz support, etc.
9 this module basically handles "pure" load / store operations, and
10 its first job is to ask the D-Cache for the data. if that fails,
11 the second task (if virtual memory is enabled) is to ask the MMU
12 to perform a TLB, then to go *back* to the cache and ask again.
16 * https://bugs.libre-soc.org/show_bug.cgi?id=465
20 from nmigen
import (Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
,
23 from nmutil
.iocontrol
import RecordObject
24 from nmutil
.util
import rising_edge
, Display
25 from enum
import Enum
, unique
27 from soc
.experiment
.dcache
import DCache
28 from soc
.experiment
.pimem
import PortInterfaceBase
29 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
30 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
32 from soc
.minerva
.wishbone
import make_wb_layout
33 from soc
.bus
.sram
import SRAM
34 from nmutil
.util
import Display
39 IDLE
= 0 # ready for instruction
40 ACK_WAIT
= 1 # waiting for ack from dcache
41 MMU_LOOKUP
= 2 # waiting for MMU to look up translation
42 TLBIE_WAIT
= 3 # waiting for MMU to finish doing a tlbie
45 # captures the LDSTRequest from the PortInterface, which "blips" most
46 # of this at us (pipeline-style).
47 class LDSTRequest(RecordObject
):
48 def __init__(self
, name
=None):
49 RecordObject
.__init
__(self
, name
=name
)
53 self
.addr
= Signal(64)
54 # self.store_data = Signal(64) # this is already sync (on a delay)
55 self
.byte_sel
= Signal(8)
56 self
.nc
= Signal() # non-cacheable access
57 self
.virt_mode
= Signal()
58 self
.priv_mode
= Signal()
59 self
.align_intr
= Signal()
61 # glue logic for microwatt mmu and dcache
62 class LoadStore1(PortInterfaceBase
):
63 def __init__(self
, pspec
):
65 self
.disable_cache
= (hasattr(pspec
, "disable_cache") and
66 pspec
.disable_cache
== True)
67 regwid
= pspec
.reg_wid
68 addrwid
= pspec
.addr_wid
70 super().__init
__(regwid
, addrwid
)
71 self
.dcache
= DCache()
72 # these names are from the perspective of here (LoadStore1)
73 self
.d_out
= self
.dcache
.d_in
# in to dcache is out for LoadStore
74 self
.d_in
= self
.dcache
.d_out
# out from dcache is in for LoadStore
75 self
.m_out
= LoadStore1ToMMUType() # out *to* MMU
76 self
.m_in
= MMUToLoadStore1Type() # in *from* MMU
77 self
.req
= LDSTRequest(name
="ldst_req")
79 # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
80 self
.dbus
= Record(make_wb_layout(pspec
))
82 # for creating a single clock blip to DCache
83 self
.d_valid
= Signal()
84 self
.d_w_valid
= Signal()
85 self
.d_validblip
= Signal()
87 # DSISR and DAR cached values. note that the MMU FSM is where
88 # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
89 # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
90 self
.dsisr
= Signal(64)
93 # state info for LD/ST
95 # latch most of the input request
99 self
.addr
= Signal(64)
100 self
.store_data
= Signal(64)
101 self
.load_data
= Signal(64)
102 self
.byte_sel
= Signal(8)
103 #self.xerc : xer_common_t;
104 #self.reserve = Signal()
105 #self.atomic = Signal()
106 #self.atomic_last = Signal()
108 self
.nc
= Signal() # non-cacheable access
109 self
.virt_mode
= Signal()
110 self
.priv_mode
= Signal()
111 self
.state
= Signal(State
)
112 self
.instr_fault
= Signal()
113 self
.align_intr
= Signal()
115 self
.wait_dcache
= Signal()
116 self
.wait_mmu
= Signal()
117 #self.mode_32bit = Signal()
118 #self.intr_vec : integer range 0 to 16#fff#;
119 #self.nia = Signal(64)
120 #self.srr1 = Signal(16)
122 def set_wr_addr(self
, m
, addr
, mask
, misalign
, msr_pr
, is_dcbz
):
123 m
.d
.comb
+= self
.req
.load
.eq(0) # store operation
124 m
.d
.comb
+= self
.req
.byte_sel
.eq(mask
)
125 m
.d
.comb
+= self
.req
.addr
.eq(addr
)
126 m
.d
.comb
+= self
.req
.priv_mode
.eq(~msr_pr
) # not-problem ==> priv
127 m
.d
.comb
+= self
.req
.virt_mode
.eq(msr_pr
) # problem-state ==> virt
128 m
.d
.comb
+= self
.req
.align_intr
.eq(misalign
)
129 m
.d
.comb
+= self
.req
.dcbz
.eq(is_dcbz
)
131 m
.d
.comb
+= Display("set_wr_addr %i dcbz %i",addr
,is_dcbz
)
133 # option to disable the cache entirely for write
134 if self
.disable_cache
:
135 m
.d
.comb
+= self
.req
.nc
.eq(1)
138 def set_rd_addr(self
, m
, addr
, mask
, misalign
, msr_pr
):
139 m
.d
.comb
+= self
.d_valid
.eq(1)
140 m
.d
.comb
+= self
.req
.load
.eq(1) # load operation
141 m
.d
.comb
+= self
.req
.byte_sel
.eq(mask
)
142 m
.d
.comb
+= self
.req
.align_intr
.eq(misalign
)
143 m
.d
.comb
+= self
.req
.addr
.eq(addr
)
144 m
.d
.comb
+= self
.req
.priv_mode
.eq(~msr_pr
) # not-problem ==> priv
145 m
.d
.comb
+= self
.req
.virt_mode
.eq(msr_pr
) # problem-state ==> virt
146 # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
147 # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
148 with m
.If(addr
[28:] == Const(0xc, 4)):
149 m
.d
.comb
+= self
.req
.nc
.eq(1)
150 # option to disable the cache entirely for read
151 if self
.disable_cache
:
152 m
.d
.comb
+= self
.req
.nc
.eq(1)
153 return None #FIXME return value
155 def set_wr_data(self
, m
, data
, wen
):
156 # do the "blip" on write data
157 m
.d
.comb
+= self
.d_valid
.eq(1)
158 # put data into comb which is picked up in main elaborate()
159 m
.d
.comb
+= self
.d_w_valid
.eq(1)
160 m
.d
.comb
+= self
.store_data
.eq(data
)
161 #m.d.sync += self.d_out.byte_sel.eq(wen) # this might not be needed
162 st_ok
= self
.done
# TODO indicates write data is valid
165 def get_rd_data(self
, m
):
166 ld_ok
= self
.done
# indicates read data is valid
167 data
= self
.load_data
# actual read data
170 def elaborate(self
, platform
):
171 m
= super().elaborate(platform
)
172 comb
, sync
= m
.d
.comb
, m
.d
.sync
174 # create dcache module
175 m
.submodules
.dcache
= dcache
= self
.dcache
178 d_out
, d_in
, dbus
= self
.d_out
, self
.d_in
, self
.dbus
179 m_out
, m_in
= self
.m_out
, self
.m_in
181 exception
= exc
.happened
184 # copy of address, but gets over-ridden for OP_FETCH_FAILED
186 m
.d
.comb
+= maddr
.eq(self
.addr
)
188 # create a blip (single pulse) on valid read/write request
189 # this can be over-ridden in the FSM to get dcache to re-run
190 # a request when MMU_LOOKUP completes.
191 m
.d
.comb
+= self
.d_validblip
.eq(rising_edge(m
, self
.d_valid
))
192 ldst_r
= LDSTRequest("ldst_r")
195 with m
.Switch(self
.state
):
196 with m
.Case(State
.IDLE
):
197 with m
.If(self
.d_validblip
& ~exc
.happened
):
198 comb
+= self
.busy
.eq(1)
199 sync
+= self
.state
.eq(State
.ACK_WAIT
)
200 sync
+= ldst_r
.eq(self
.req
) # copy of LDSTRequest on "blip"
204 # waiting for completion
205 with m
.Case(State
.ACK_WAIT
):
206 comb
+= self
.busy
.eq(~exc
.happened
)
208 with m
.If(d_in
.error
):
209 # cache error is not necessarily "final", it could
210 # be that it was just a TLB miss
211 with m
.If(d_in
.cache_paradox
):
212 comb
+= exception
.eq(1)
213 sync
+= self
.state
.eq(State
.IDLE
)
215 sync
+= Display("cache error -> update dsisr")
216 sync
+= self
.dsisr
[63 - 38].eq(~self
.load
)
217 # XXX there is no architected bit for this
218 # (probably should be a machine check in fact)
219 sync
+= self
.dsisr
[63 - 35].eq(d_in
.cache_paradox
)
222 # Look up the translation for TLB miss
223 # and also for permission error and RC error
224 # in case the PTE has been updated.
226 sync
+= self
.state
.eq(State
.MMU_LOOKUP
)
227 with m
.If(d_in
.valid
):
228 m
.d
.comb
+= self
.done
.eq(~mmureq
) # done if not doing MMU
229 with m
.If(self
.done
):
230 sync
+= Display("ACK_WAIT, done %x", self
.addr
)
231 sync
+= self
.state
.eq(State
.IDLE
)
233 with m
.If(self
.load
):
234 m
.d
.comb
+= self
.load_data
.eq(d_in
.data
)
236 # waiting here for the MMU TLB lookup to complete.
237 # either re-try the dcache lookup or throw MMU exception
238 with m
.Case(State
.MMU_LOOKUP
):
239 comb
+= self
.busy
.eq(1)
240 with m
.If(m_in
.done
):
241 with m
.If(~self
.instr_fault
):
242 sync
+= Display("MMU_LOOKUP, done %x -> %x",
243 self
.addr
, d_out
.addr
)
244 # retry the request now that the MMU has
245 # installed a TLB entry, if not exception raised
246 m
.d
.comb
+= self
.d_out
.valid
.eq(~exception
)
247 sync
+= self
.state
.eq(State
.ACK_WAIT
)
250 sync
+= Display("MMU_LOOKUP, exception %x", self
.addr
)
251 # instruction lookup fault: store address in DAR
252 comb
+= exc
.happened
.eq(1)
253 sync
+= self
.dar
.eq(self
.addr
)
256 # MMU RADIX exception thrown
257 comb
+= exception
.eq(1)
258 sync
+= Display("MMU RADIX exception thrown")
259 sync
+= self
.dsisr
[63 - 33].eq(m_in
.invalid
)
260 sync
+= self
.dsisr
[63 - 36].eq(m_in
.perm_error
)
261 sync
+= self
.dsisr
[63 - 38].eq(self
.load
)
262 sync
+= self
.dsisr
[63 - 44].eq(m_in
.badtree
)
263 sync
+= self
.dsisr
[63 - 45].eq(m_in
.rc_error
)
265 with m
.Case(State
.TLBIE_WAIT
):
268 # alignment error: store address in DAR
269 with m
.If(self
.align_intr
):
270 comb
+= exc
.happened
.eq(1)
271 sync
+= Display("alignment error: store address in DAR %x", self
.addr
)
272 sync
+= self
.dar
.eq(self
.addr
)
274 # happened, alignment, instr_fault, invalid.
275 # note that all of these flow through - eventually to the TRAP
276 # pipeline, via PowerDecoder2.
277 comb
+= exc
.invalid
.eq(m_in
.invalid
)
278 comb
+= exc
.alignment
.eq(self
.align_intr
)
279 comb
+= exc
.instr_fault
.eq(self
.instr_fault
)
280 # badtree, perm_error, rc_error, segment_fault
281 comb
+= exc
.badtree
.eq(m_in
.badtree
)
282 comb
+= exc
.perm_error
.eq(m_in
.perm_error
)
283 comb
+= exc
.rc_error
.eq(m_in
.rc_error
)
284 comb
+= exc
.segment_fault
.eq(m_in
.segerr
)
286 # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
287 comb
+= dbus
.adr
.eq(dcache
.wb_out
.adr
)
288 comb
+= dbus
.dat_w
.eq(dcache
.wb_out
.dat
)
289 comb
+= dbus
.sel
.eq(dcache
.wb_out
.sel
)
290 comb
+= dbus
.cyc
.eq(dcache
.wb_out
.cyc
)
291 comb
+= dbus
.stb
.eq(dcache
.wb_out
.stb
)
292 comb
+= dbus
.we
.eq(dcache
.wb_out
.we
)
294 comb
+= dcache
.wb_in
.dat
.eq(dbus
.dat_r
)
295 comb
+= dcache
.wb_in
.ack
.eq(dbus
.ack
)
296 if hasattr(dbus
, "stall"):
297 comb
+= dcache
.wb_in
.stall
.eq(dbus
.stall
)
299 # update out d data when flag set
300 with m
.If(self
.d_w_valid
):
301 m
.d
.sync
+= d_out
.data
.eq(self
.store_data
)
303 # m.d.sync += d_out.data.eq(0)
304 # unit test passes with that change
306 # this must move into the FSM, conditionally noticing that
307 # the "blip" comes from self.d_validblip.
308 # task 1: look up in dcache
309 # task 2: if dcache fails, look up in MMU.
310 # do **NOT** confuse the two.
311 with m
.If(self
.d_validblip
):
312 m
.d
.comb
+= self
.d_out
.valid
.eq(~exc
.happened
)
313 m
.d
.comb
+= d_out
.load
.eq(self
.req
.load
)
314 m
.d
.comb
+= d_out
.byte_sel
.eq(self
.req
.byte_sel
)
315 m
.d
.comb
+= self
.addr
.eq(self
.req
.addr
)
316 m
.d
.comb
+= d_out
.nc
.eq(self
.req
.nc
)
317 m
.d
.comb
+= d_out
.priv_mode
.eq(self
.req
.priv_mode
)
318 m
.d
.comb
+= d_out
.virt_mode
.eq(self
.req
.virt_mode
)
319 m
.d
.comb
+= self
.align_intr
.eq(self
.req
.align_intr
)
320 #m.d.comb += Display("validblip dcbz=%i addr=%x",self.req.dcbz,self.req.addr)
321 m
.d
.comb
+= d_out
.dcbz
.eq(self
.req
.dcbz
)
323 m
.d
.comb
+= d_out
.load
.eq(ldst_r
.load
)
324 m
.d
.comb
+= d_out
.byte_sel
.eq(ldst_r
.byte_sel
)
325 m
.d
.comb
+= self
.addr
.eq(ldst_r
.addr
)
326 m
.d
.comb
+= d_out
.nc
.eq(ldst_r
.nc
)
327 m
.d
.comb
+= d_out
.priv_mode
.eq(ldst_r
.priv_mode
)
328 m
.d
.comb
+= d_out
.virt_mode
.eq(ldst_r
.virt_mode
)
329 m
.d
.comb
+= self
.align_intr
.eq(ldst_r
.align_intr
)
330 #m.d.comb += Display("no_validblip dcbz=%i addr=%x",ldst_r.dcbz,ldst_r.addr)
331 m
.d
.comb
+= d_out
.dcbz
.eq(ldst_r
.dcbz
)
333 # XXX these should be possible to remove but for some reason
334 # cannot be... yet. TODO, investigate
335 m
.d
.comb
+= self
.load_data
.eq(d_in
.data
)
336 m
.d
.comb
+= d_out
.addr
.eq(self
.addr
)
338 # Update outputs to MMU
339 m
.d
.comb
+= m_out
.valid
.eq(mmureq
)
340 m
.d
.comb
+= m_out
.iside
.eq(self
.instr_fault
)
341 m
.d
.comb
+= m_out
.load
.eq(ldst_r
.load
)
342 # m_out.priv <= r.priv_mode; TODO
343 m
.d
.comb
+= m_out
.tlbie
.eq(self
.tlbie
)
344 # m_out.mtspr <= mmu_mtspr; # TODO
345 # m_out.sprn <= sprn; # TODO
346 m
.d
.comb
+= m_out
.addr
.eq(maddr
)
347 # m_out.slbia <= l_in.insn(7); # TODO: no idea what this is
348 # m_out.rs <= l_in.data; # nope, probably not needed, TODO investigate
353 yield from super().ports()
357 class TestSRAMLoadStore1(LoadStore1
):
358 def __init__(self
, pspec
):
359 super().__init
__(pspec
)
361 # small 32-entry Memory
362 if (hasattr(pspec
, "dmem_test_depth") and
363 isinstance(pspec
.dmem_test_depth
, int)):
364 depth
= pspec
.dmem_test_depth
367 print("TestSRAMBareLoadStoreUnit depth", depth
)
369 self
.mem
= Memory(width
=pspec
.reg_wid
, depth
=depth
)
371 def elaborate(self
, platform
):
372 m
= super().elaborate(platform
)
374 m
.submodules
.sram
= sram
= SRAM(memory
=self
.mem
, granularity
=8,
375 features
={'cti', 'bte', 'err'})
378 # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
379 # note: SRAM is a target (slave), dbus is initiator (master)
380 fanouts
= ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
381 fanins
= ['dat_r', 'ack', 'err']
382 for fanout
in fanouts
:
383 print("fanout", fanout
, getattr(sram
.bus
, fanout
).shape(),
384 getattr(dbus
, fanout
).shape())
385 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
386 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
388 comb
+= getattr(dbus
, fanin
).eq(getattr(sram
.bus
, fanin
))
390 comb
+= sram
.bus
.adr
.eq(dbus
.adr
)