src/soc/fu/logical/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.test.common import TestCase, ALUHelpers
  15 from soc.fu.logical.pipeline import LogicalBasePipe
  16 from soc.fu.logical.pipe_data import LogicalPipeSpec
  17 import random
  18
  19
  20 def get_cu_inputs(dec2, sim):
  21     """naming (res) must conform to LogicalFunctionUnit input regspec
  22     """
  23     res = {}
  24
  25     # RA (or RC)
  26     reg1_ok = yield dec2.e.read_reg1.ok
  27     if reg1_ok:
  28         data1 = yield dec2.e.read_reg1.data
  29         res['ra'] = sim.gpr(data1).value
  30
  31     # RB (or immediate)
  32     reg2_ok = yield dec2.e.read_reg2.ok
  33     #imm_ok = yield dec2.e.imm_data.imm_ok
  34     if reg2_ok:
  35         data2 = yield dec2.e.read_reg2.data
  36         data2 = sim.gpr(data2).value
  37         res['rb'] = data2
  38     #elif imm_ok:
  39     #    data2 = yield dec2.e.imm_data.imm
  40     #    res['rb'] = data2
  41
  42     return res
  43
  44
  45 def set_alu_inputs(alu, dec2, sim):
  46     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  47     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  48     # and place it into data_i.b
  49
  50     inp = yield from get_cu_inputs(dec2, sim)
  51     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  52     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  53
  54
  55 # This test bench is a bit different than is usual. Initially when I
  56 # was writing it, I had all of the tests call a function to create a
  57 # device under test and simulator, initialize the dut, run the
  58 # simulation for ~2 cycles, and assert that the dut output what it
  59 # should have. However, this was really slow, since it needed to
  60 # create and tear down the dut and simulator for every test case.
  61
  62 # Now, instead of doing that, every test case in ALUTestCase puts some
  63 # data into the test_data list below, describing the instructions to
  64 # be tested and the initial state. Once all the tests have been run,
  65 # test_data gets passed to TestRunner which then sets up the DUT and
  66 # simulator once, runs all the data through it, and asserts that the
  67 # results match the pseudocode sim at every cycle.
  68
  69 # By doing this, I've reduced the time it takes to run the test suite
  70 # massively. Before, it took around 1 minute on my computer, now it
  71 # takes around 3 seconds
  72
  73
  74 class LogicalTestCase(FHDLTestCase):
  75     test_data = []
  76     def __init__(self, name):
  77         super().__init__(name)
  78         self.test_name = name
  79
  80     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  81         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  82         self.test_data.append(tc)
  83
  84     def test_rand(self):
  85         insns = ["and", "or", "xor"]
  86         for i in range(40):
  87             choice = random.choice(insns)
  88             lst = [f"{choice} 3, 1, 2"]
  89             initial_regs = [0] * 32
  90             initial_regs[1] = random.randint(0, (1 << 64)-1)
  91             initial_regs[2] = random.randint(0, (1 << 64)-1)
  92             self.run_tst_program(Program(lst), initial_regs)
  93
  94     def test_rand_imm_logical(self):
  95         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
  96         for i in range(10):
  97             choice = random.choice(insns)
  98             imm = random.randint(0, (1 << 16)-1)
  99             lst = [f"{choice} 3, 1, {imm}"]
 100             print(lst)
 101             initial_regs = [0] * 32
 102             initial_regs[1] = random.randint(0, (1 << 64)-1)
 103             self.run_tst_program(Program(lst), initial_regs)
 104
 105     def test_cntz(self):
 106         insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
 107         for i in range(100):
 108             choice = random.choice(insns)
 109             lst = [f"{choice} 3, 1"]
 110             print(lst)
 111             initial_regs = [0] * 32
 112             initial_regs[1] = random.randint(0, (1 << 64)-1)
 113             self.run_tst_program(Program(lst), initial_regs)
 114
 115     def test_parity(self):
 116         insns = ["prtyw", "prtyd"]
 117         for i in range(10):
 118             choice = random.choice(insns)
 119             lst = [f"{choice} 3, 1"]
 120             print(lst)
 121             initial_regs = [0] * 32
 122             initial_regs[1] = random.randint(0, (1 << 64)-1)
 123             self.run_tst_program(Program(lst), initial_regs)
 124
 125     def test_popcnt(self):
 126         insns = ["popcntb", "popcntw", "popcntd"]
 127         for i in range(10):
 128             choice = random.choice(insns)
 129             lst = [f"{choice} 3, 1"]
 130             print(lst)
 131             initial_regs = [0] * 32
 132             initial_regs[1] = random.randint(0, (1 << 64)-1)
 133             self.run_tst_program(Program(lst), initial_regs)
 134
 135     def test_popcnt_edge(self):
 136         insns = ["popcntb", "popcntw", "popcntd"]
 137         for choice in insns:
 138             lst = [f"{choice} 3, 1"]
 139             initial_regs = [0] * 32
 140             initial_regs[1] = -1
 141             self.run_tst_program(Program(lst), initial_regs)
 142
 143     def test_cmpb(self):
 144         lst = ["cmpb 3, 1, 2"]
 145         initial_regs = [0] * 32
 146         initial_regs[1] = 0xdeadbeefcafec0de
 147         initial_regs[2] = 0xd0adb0000afec1de
 148         self.run_tst_program(Program(lst), initial_regs)
 149
 150     def test_bpermd(self):
 151         lst = ["bpermd 3, 1, 2"]
 152         for i in range(20):
 153             initial_regs = [0] * 32
 154             initial_regs[1] = 1<<random.randint(0,63)
 155             initial_regs[2] = 0xdeadbeefcafec0de
 156             self.run_tst_program(Program(lst), initial_regs)
 157
 158     def test_ilang(self):
 159         pspec = LogicalPipeSpec(id_wid=2)
 160         alu = LogicalBasePipe(pspec)
 161         vl = rtlil.convert(alu, ports=alu.ports())
 162         with open("logical_pipeline.il", "w") as f:
 163             f.write(vl)
 164
 165
 166 class TestRunner(FHDLTestCase):
 167     def __init__(self, test_data):
 168         super().__init__("run_all")
 169         self.test_data = test_data
 170
 171     def run_all(self):
 172         m = Module()
 173         comb = m.d.comb
 174         instruction = Signal(32)
 175
 176         pdecode = create_pdecode()
 177
 178         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 179
 180         pspec = LogicalPipeSpec(id_wid=2)
 181         m.submodules.alu = alu = LogicalBasePipe(pspec)
 182
 183         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 184         comb += alu.p.valid_i.eq(1)
 185         comb += alu.n.ready_i.eq(1)
 186         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 187         sim = Simulator(m)
 188
 189         sim.add_clock(1e-6)
 190
 191         def process():
 192             for test in self.test_data:
 193                 print(test.name)
 194                 program = test.program
 195                 self.subTest(test.name)
 196                 simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
 197                                 test.mem, test.msr)
 198                 gen = program.generate_instructions()
 199                 instructions = list(zip(gen, program.assembly.splitlines()))
 200
 201                 index = simulator.pc.CIA.value//4
 202                 while index < len(instructions):
 203                     ins, code = instructions[index]
 204
 205                     print("0x{:X}".format(ins & 0xffffffff))
 206                     print(code)
 207
 208                     # ask the decoder to decode this binary data (endian'd)
 209                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 210                     yield instruction.eq(ins)          # raw binary instr.
 211                     yield Settle()
 212                     fn_unit = yield pdecode2.e.fn_unit
 213                     self.assertEqual(fn_unit, Function.LOGICAL.value, code)
 214                     yield from set_alu_inputs(alu, pdecode2, simulator)
 215                     yield
 216                     opname = code.split(' ')[0]
 217                     yield from simulator.call(opname)
 218                     index = simulator.pc.CIA.value//4
 219
 220                     vld = yield alu.n.valid_o
 221                     while not vld:
 222                         yield
 223                         vld = yield alu.n.valid_o
 224                     yield
 225                     alu_out = yield alu.n.data_o.o.data
 226                     out_reg_valid = yield pdecode2.e.write_reg.ok
 227                     if out_reg_valid:
 228                         write_reg_idx = yield pdecode2.e.write_reg.data
 229                         expected = simulator.gpr(write_reg_idx).value
 230                         print(f"expected {expected:x}, actual: {alu_out:x}")
 231                         self.assertEqual(expected, alu_out, code)
 232                     yield from self.check_extra_alu_outputs(alu, pdecode2,
 233                                                             simulator, code)
 234
 235         sim.add_sync_process(process)
 236         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 237                            traces=[]):
 238             sim.run()
 239
 240     def check_extra_alu_outputs(self, alu, dec2, sim, code):
 241         rc = yield dec2.e.rc.data
 242         if rc:
 243             cr_expected = sim.crl[0].get_range().value
 244             cr_actual = yield alu.n.data_o.cr0.data
 245             self.assertEqual(cr_expected, cr_actual, code)
 246
 247
 248 if __name__ == "__main__":
 249     unittest.main(exit=False)
 250     suite = unittest.TestSuite()
 251     suite.addTest(TestRunner(LogicalTestCase.test_data))
 252
 253     runner = unittest.TextTestRunner()
 254     runner.run(suite)