src/soc/fu/mul/pipe_data.py

   1 from soc.fu.alu.alu_input_record import CompALUOpSubset
   2 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
   3 from soc.fu.alu.pipe_data import ALUOutputData, ALUInputData
   4 from nmigen import Signal
   5
   6
   7 class MulIntermediateData(ALUInputData):
   8     def __init__(self, pspec):
   9         super().__init__(pspec)
  10
  11         self.neg_res = Signal(reset_less=True)
  12         self.neg_res32 = Signal(reset_less=True)
  13         self.data.append(self.neg_res)
  14         self.data.append(self.neg_res32)
  15
  16
  17 class MulOutputData(IntegerData):
  18     regspec = [('INT', 'o', '0:128'),
  19                ('XER', 'xer_so', '32'), # XER bit 32: SO
  20                ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
  21     def __init__(self, pspec):
  22         super().__init__(pspec, False)
  23
  24         self.neg_res = Signal(reset_less=True)
  25         self.neg_res32 = Signal(reset_less=True)
  26         self.data.append(self.neg_res)
  27         self.data.append(self.neg_res32)
  28
  29
  30 class MulPipeSpec(CommonPipeSpec):
  31     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
  32     opsubsetkls = CompALUOpSubset