src/soc/fu/shift_rot/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3 """
   4 Links:
   5 * https://bugs.libre-soc.org/show_bug.cgi?id=340
   6 """
   7
   8 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   9                     signed)
  10 from nmigen.asserts import Assert, AnyConst, Assume, Cover
  11 from nmutil.formaltest import FHDLTestCase
  12 from nmigen.cli import rtlil
  13
  14 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
  15 from soc.fu.alu.pipe_data import ALUPipeSpec
  16 from soc.fu.alu.alu_input_record import CompALUOpSubset
  17 from soc.decoder.power_enums import MicrOp
  18 import unittest
  19 from nmutil.extend import exts
  20
  21
  22 # This defines a module to drive the device under test and assert
  23 # properties about its outputs
  24 class Driver(Elaboratable):
  25     def __init__(self):
  26         # inputs and outputs
  27         pass
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         comb = m.d.comb
  32
  33         rec = CompALUOpSubset()
  34         # Setup random inputs for dut.op
  35         for p in rec.ports():
  36             comb += p.eq(AnyConst(p.width))
  37
  38         pspec = ALUPipeSpec(id_wid=2)
  39         m.submodules.dut = dut = ShiftRotMainStage(pspec)
  40
  41         # convenience variables
  42         a = dut.i.rs
  43         b = dut.i.rb
  44         ra = dut.i.a
  45         carry_in = dut.i.xer_ca[0]
  46         carry_in32 = dut.i.xer_ca[1]
  47         carry_out = dut.o.xer_ca
  48         o = dut.o.o.data
  49
  50         # setup random inputs
  51         comb += a.eq(AnyConst(64))
  52         comb += b.eq(AnyConst(64))
  53         comb += carry_in.eq(AnyConst(1))
  54         comb += carry_in32.eq(AnyConst(1))
  55
  56         comb += dut.i.ctx.op.eq(rec)
  57
  58         # Assert that op gets copied from the input to output
  59         for rec_sig in rec.ports():
  60             name = rec_sig.name
  61             dut_sig = getattr(dut.o.ctx.op, name)
  62             comb += Assert(dut_sig == rec_sig)
  63
  64         # signed and signed/32 versions of input a
  65         a_signed = Signal(signed(64))
  66         a_signed_32 = Signal(signed(32))
  67         comb += a_signed.eq(a)
  68         comb += a_signed_32.eq(a[0:32])
  69
  70         # must check Data.ok
  71         o_ok = Signal()
  72         comb += o_ok.eq(1)
  73
  74         # main assertion of arithmetic operations
  75         with m.Switch(rec.insn_type):
  76
  77             with m.Case(MicrOp.OP_SHL):
  78                 comb += Assume(ra == 0)
  79                 with m.If(rec.is_32bit):
  80                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
  81                     comb += Assert(o[32:64] == 0)
  82                 with m.Else():
  83                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
  84
  85             with m.Case(MicrOp.OP_SHR):
  86                 comb += Assume(ra == 0)
  87                 with m.If(~rec.is_signed):
  88                     with m.If(rec.is_32bit):
  89                         comb += Assert(o[0:32] == (a[0:32] >> b[0:6]))
  90                         comb += Assert(o[32:64] == 0)
  91                     with m.Else():
  92                         comb += Assert(o == (a >> b[0:7]))
  93                 with m.Else():
  94                     with m.If(rec.is_32bit):
  95                         comb += Assert(o[0:32] == (a_signed_32 >> b[0:6]))
  96                         comb += Assert(o[32:64] == Repl(a[31], 32))
  97                     with m.Else():
  98                         comb += Assert(o == (a_signed >> b[0:7]))
  99             #TODO
 100             with m.Case(MicrOp.OP_RLC):
 101                 pass
 102             with m.Case(MicrOp.OP_RLCR):
 103                 pass
 104             with m.Case(MicrOp.OP_RLCL):
 105                 pass
 106             with m.Case(MicrOp.OP_EXTSWSLI):
 107                 # sign-extend
 108                 a_s = Signal(64, reset_less=True)
 109                 comb += a_s.eq(exts(a, 32, 64))
 110                 # assume b[0:6] is sh
 111                 comb += Assume(b[7:] == 0)
 112                 with m.If(b[0:7] == 0):
 113                     comb += Assert(o[0:32] == a_s[0:32])
 114                 with m.Else():
 115                     #b_s = 64-b[0:6]
 116                     #comb += Assert(o == ((a_s << b_s) & ((1 << 64)-1)))
 117                     pass
 118
 119             with m.Default():
 120                 comb += o_ok.eq(0)
 121
 122         # check that data ok was only enabled when op actioned
 123         comb += Assert(dut.o.o.ok == o_ok)
 124
 125         return m
 126
 127
 128 class ALUTestCase(FHDLTestCase):
 129     def test_formal(self):
 130         module = Driver()
 131         self.assertFormal(module, mode="bmc", depth=2)
 132         self.assertFormal(module, mode="cover", depth=2)
 133     def test_ilang(self):
 134         dut = Driver()
 135         vl = rtlil.convert(dut, ports=[])
 136         with open("main_stage.il", "w") as f:
 137             f.write(vl)
 138
 139
 140 if __name__ == '__main__':
 141     unittest.main()