src/soc/fu/shift_rot/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3
   4 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   5                     signed)
   6 from nmigen.asserts import Assert, AnyConst, Assume, Cover
   7 from nmigen.test.utils import FHDLTestCase
   8 from nmigen.cli import rtlil
   9
  10 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
  11 from soc.fu.alu.pipe_data import ALUPipeSpec
  12 from soc.fu.alu.alu_input_record import CompALUOpSubset
  13 from soc.decoder.power_enums import InternalOp
  14 import unittest
  15
  16
  17 # This defines a module to drive the device under test and assert
  18 # properties about its outputs
  19 class Driver(Elaboratable):
  20     def __init__(self):
  21         # inputs and outputs
  22         pass
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         rec = CompALUOpSubset()
  29         # Setup random inputs for dut.op
  30         for p in rec.ports():
  31             comb += p.eq(AnyConst(p.width))
  32
  33         pspec = ALUPipeSpec(id_wid=2)
  34         m.submodules.dut = dut = ShiftRotMainStage(pspec)
  35
  36         # convenience variables
  37         a = dut.i.rs
  38         b = dut.i.rb
  39         ra = dut.i.a
  40         carry_in = dut.i.xer_ca[0]
  41         carry_in32 = dut.i.xer_ca[1]
  42         so_in = dut.i.xer_so
  43         carry_out = dut.o.xer_ca
  44         o = dut.o.o
  45
  46         # setup random inputs
  47         comb += [a.eq(AnyConst(64)),
  48                  b.eq(AnyConst(64)),
  49                  carry_in.eq(AnyConst(1)),
  50                  carry_in32.eq(AnyConst(1)),
  51                  so_in.eq(AnyConst(1))]
  52
  53         comb += dut.i.ctx.op.eq(rec)
  54
  55         # Assert that op gets copied from the input to output
  56         for rec_sig in rec.ports():
  57             name = rec_sig.name
  58             dut_sig = getattr(dut.o.ctx.op, name)
  59             comb += Assert(dut_sig == rec_sig)
  60
  61         # signed and signed/32 versions of input a
  62         a_signed = Signal(signed(64))
  63         a_signed_32 = Signal(signed(32))
  64         comb += a_signed.eq(a)
  65         comb += a_signed_32.eq(a[0:32])
  66
  67         # main assertion of arithmetic operations
  68         with m.Switch(rec.insn_type):
  69             with m.Case(InternalOp.OP_SHL):
  70                 comb += Assume(ra == 0)
  71                 with m.If(rec.is_32bit):
  72                     comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
  73                     comb += Assert(o[32:64] == 0)
  74                 with m.Else():
  75                     comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
  76             with m.Case(InternalOp.OP_SHR):
  77                 comb += Assume(ra == 0)
  78                 with m.If(~rec.is_signed):
  79                     with m.If(rec.is_32bit):
  80                         comb += Assert(o[0:32] == (a[0:32] >> b[0:6]))
  81                         comb += Assert(o[32:64] == 0)
  82                     with m.Else():
  83                         comb += Assert(o == (a >> b[0:7]))
  84                 with m.Else():
  85                     with m.If(rec.is_32bit):
  86                         comb += Assert(o[0:32] == (a_signed_32 >> b[0:6]))
  87                         comb += Assert(o[32:64] == Repl(a[31], 32))
  88                     with m.Else():
  89                         comb += Assert(o == (a_signed >> b[0:7]))
  90
  91         return m
  92
  93
  94 class ALUTestCase(FHDLTestCase):
  95     def test_formal(self):
  96         module = Driver()
  97         self.assertFormal(module, mode="bmc", depth=2)
  98         self.assertFormal(module, mode="cover", depth=2)
  99     def test_ilang(self):
 100         dut = Driver()
 101         vl = rtlil.convert(dut, ports=[])
 102         with open("main_stage.il", "w") as f:
 103             f.write(vl)
 104
 105
 106 if __name__ == '__main__':
 107     unittest.main()