src/soc/fu/shift_rot/main_stage.py

   1 # License: LGPLv3+
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3 # Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4
   5 # This stage is intended to do most of the work of executing shift
   6 # instructions, as well as carry and overflow generation. This module
   7 # however should not gate the carry or overflow, that's up to the
   8 # output stage
   9 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
  10 from nmutil.pipemodbase import PipeModBase
  11 from soc.fu.pipe_data import get_pspec_draft_bitmanip
  12 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
  13                                         ShiftRotInputData)
  14 from nmutil.lut import BitwiseLut
  15 from openpower.decoder.power_enums import MicrOp
  16 from soc.fu.shift_rot.rotator import Rotator
  17
  18 from openpower.decoder.power_fields import DecodeFields
  19 from openpower.decoder.power_fieldsn import SignalBitRange
  20
  21
  22 class ShiftRotMainStage(PipeModBase):
  23     def __init__(self, pspec):
  24         super().__init__(pspec, "main")
  25         self.draft_bitmanip = get_pspec_draft_bitmanip(pspec)
  26         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  27         self.fields.create_specs()
  28
  29     def ispec(self):
  30         return ShiftRotInputData(self.pspec)
  31
  32     def ospec(self):
  33         return ShiftRotOutputData(self.pspec)
  34
  35     def elaborate(self, platform):
  36         m = Module()
  37         comb = m.d.comb
  38         op = self.i.ctx.op
  39         o = self.o.o
  40
  41         bitwise_lut = None
  42         if self.draft_bitmanip:
  43             bitwise_lut = BitwiseLut(input_count=3, width=64)
  44             m.submodules.bitwise_lut = bitwise_lut
  45             comb += bitwise_lut.inputs[0].eq(self.i.rb)
  46             comb += bitwise_lut.inputs[1].eq(self.i.ra)
  47             comb += bitwise_lut.inputs[2].eq(self.i.rc)
  48
  49         # NOTE: the sh field immediate is read in by PowerDecode2
  50         # (actually DecodeRB), whereupon by way of rb "immediate" mode
  51         # it ends up in self.i.rb.
  52
  53         # obtain me and mb fields from instruction.
  54         m_fields = self.fields.instrs['M']
  55         md_fields = self.fields.instrs['MD']
  56         mb = Signal(m_fields['MB'][0:-1].shape())
  57         me = Signal(m_fields['ME'][0:-1].shape())
  58         mb_extra = Signal(1, reset_less=True)
  59         comb += mb.eq(m_fields['MB'][0:-1])
  60         comb += me.eq(m_fields['ME'][0:-1])
  61         comb += mb_extra.eq(md_fields['mb'][0:-1][0])
  62
  63         # set up microwatt rotator module
  64         m.submodules.rotator = rotator = Rotator()
  65         comb += [
  66             rotator.me.eq(me),
  67             rotator.mb.eq(mb),
  68             rotator.mb_extra.eq(mb_extra),
  69             rotator.rs.eq(self.i.rs),
  70             rotator.ra.eq(self.i.a),
  71             rotator.shift.eq(self.i.rb),  # can also be sh (in immediate mode)
  72             rotator.is_32bit.eq(op.is_32bit),
  73             rotator.arith.eq(op.is_signed),
  74         ]
  75
  76         comb += o.ok.eq(1)  # defaults to enabled
  77
  78         # instruction rotate type
  79         mode = Signal(4, reset_less=True)
  80         comb += Cat(rotator.right_shift,
  81                     rotator.clear_left,
  82                     rotator.clear_right,
  83                     rotator.sign_ext_rs).eq(mode)
  84
  85         # outputs from the microwatt rotator module
  86         comb += [o.data.eq(rotator.result_o),
  87                  self.o.xer_ca.data.eq(Repl(rotator.carry_out_o, 2))]
  88
  89         with m.Switch(op.insn_type):
  90             with m.Case(MicrOp.OP_SHL):
  91                 comb += mode.eq(0b0000)  # L-shift
  92             with m.Case(MicrOp.OP_SHR):
  93                 comb += mode.eq(0b0001)  # R-shift
  94             with m.Case(MicrOp.OP_RLC):
  95                 comb += mode.eq(0b0110)  # clear LR
  96             with m.Case(MicrOp.OP_RLCL):
  97                 comb += mode.eq(0b0010)  # clear L
  98             with m.Case(MicrOp.OP_RLCR):
  99                 comb += mode.eq(0b0100)  # clear R
 100             with m.Case(MicrOp.OP_EXTSWSLI):
 101                 comb += mode.eq(0b1000)  # L-ext
 102             if self.draft_bitmanip:
 103                 with m.Case(MicrOp.OP_TERNLOG):
 104                     # TODO: this only works for ternlogi, change to get lut
 105                     # value from register when we implement other variants
 106                     comb += bitwise_lut.lut.eq(self.fields.FormTLI.TLI[:])
 107                     comb += o.data.eq(bitwise_lut.output)
 108                     comb += self.o.xer_ca.data.eq(0)
 109             with m.Default():
 110                 comb += o.ok.eq(0)  # otherwise disable
 111
 112         ###### sticky overflow and context, both pass-through #####
 113
 114         comb += self.o.xer_so.data.eq(self.i.xer_so)
 115         comb += self.o.ctx.eq(self.i.ctx)
 116
 117         return m