src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.decoder.power_enums import InternalOp
  13
  14 from soc.decoder.power_fields import DecodeFields
  15 from soc.decoder.power_fieldsn import SignalBitRange
  16
  17 # TODO at some point move these to their own module (for use elsewhere)
  18 """
  19     Listed in V3.0B Book III Chap 4.2.1
  20     -- MSR bit numbers
  21     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  22     constant MSR_HV  : integer := (63 - 3);     -- Hypervisor state
  23     constant MSR_S   : integer := (63 - 41);    -- Secure state
  24     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  25     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  26     constant MSR_FP  : integer := (63 - 50);    -- FP available
  27     constant MSR_ME  : integer := (63 - 51);    -- Machine Check int enable
  28     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  29     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  30     constant MSR_PMM : integer := (63 - 60);    -- Performance Monitor Mark
  31     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  32     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  33 """
  34
  35 class TrapMainStage(PipeModBase):
  36     def __init__(self, pspec):
  37         super().__init__(pspec, "main")
  38         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  39         self.fields.create_specs()
  40
  41     def ispec(self):
  42         return TrapInputData(self.pspec)
  43
  44     def ospec(self):
  45         return TrapOutputData(self.pspec)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         comb = m.d.comb
  50         op = self.i.ctx.op
  51         a_i, b_i = self.i.a, self.i.b
  52
  53         # take copy of D-Form TO field
  54         i_fields = self.fields.FormD
  55         to = Signal(i_fields.TO[0:-1].shape())
  56         comb += to.eq(i_fields.TO[0:-1])
  57
  58         # signed/unsigned temporaries for RA and RB
  59         a_s = Signal(signed(64), reset_less=True)
  60         b_s = Signal(signed(64), reset_less=True)
  61
  62         a = Signal(64, reset_less=True)
  63         b = Signal(64, reset_less=True)
  64
  65         # set up A and B comparison (truncate/sign-extend if 32 bit)
  66         with m.If(op.is_32bit):
  67             comb += a_s.eq(exts(a_i, 32, 64))
  68             comb += b_s.eq(exts(b_i, 32, 64))
  69             comb += a.eq(a_i[0:32])
  70             comb += b.eq(b_i[0:32])
  71         with m.Else():
  72             comb += a_s.eq(a_i)
  73             comb += b_s.eq(b_i)
  74             comb += a.eq(a_i)
  75             comb += b.eq(b_i)
  76
  77         # establish comparison bits
  78         lt_s = Signal(reset_less=True)
  79         gt_s = Signal(reset_less=True)
  80         lt_u = Signal(reset_less=True)
  81         gt_u = Signal(reset_less=True)
  82         equal = Signal(reset_less=True)
  83
  84         comb += lt_s.eq(a_s < b_s)
  85         comb += gt_s.eq(a_s > b_s)
  86         comb += lt_u.eq(a < b)
  87         comb += gt_u.eq(a > b)
  88         comb += equal.eq(a == b)
  89
  90         # They're in reverse bit order because POWER.
  91         # Check V3.0B Book 1, Appendix C.6 for chart
  92         trap_bits = Signal(5)
  93         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  94
  95         # establish if the trap should go ahead (any tests requested in TO)
  96         should_trap = Signal()
  97         comb += should_trap.eq((trap_bits & to).any())
  98
  99         # TODO: some #defines for the bits n stuff.
 100         with m.Switch(op):
 101             #### trap ####
 102             with m.Case(InternalOp.OP_TRAP):
 103                 """
 104                 -- trap instructions (tw, twi, td, tdi)
 105                 if or (trapval and insn_to(e_in.insn)) = '1' then
 106                     -- generate trap-type program interrupt
 107                     exception := '1';
 108                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 109                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 110                     -- set bit 46 to say trap occurred
 111                     ctrl_tmp.srr1(63 - 46) <= '1';
 112                 """
 113                 with m.If(should_trap):
 114                     comb += self.o.nia.data.eq(0x700)         # trap address
 115                     comb += self.o.nia.ok.eq(1)
 116                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
 117                     comb += self.o.srr1.data[63-46].eq(1)     # XXX which bit?
 118                     comb += self.o.srr1.ok.eq(1)
 119                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
 120                     comb += self.o.srr0.ok.eq(1)
 121
 122             # move to SPR
 123             with m.Case(InternalOp.OP_MTMSR):
 124                 # TODO: some of the bits need zeroing?
 125                 """
 126                 if e_in.insn(16) = '1' then
 127                     -- just update EE and RI
 128                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 129                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 130                 else
 131                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 132                     -- and 63 (LE) (IBM bit numbering)
 133                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 134                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 135                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 136                     if c_in(MSR_PR) = '1' then
 137                         ctrl_tmp.msr(MSR_EE) <= '1';
 138                         ctrl_tmp.msr(MSR_IR) <= '1';
 139                         ctrl_tmp.msr(MSR_DR) <= '1';
 140                 """
 141                 for stt, end in [(1,12), (13, 60), (61, 64)]:
 142                     comb += self.o.msr.data[stt:end].eq(a[stt:end])
 143                 with m.If(a[MSR_PR]):
 144                         self.o.msr[MSR_EE].eq(1)
 145                         self.o.msr[MSR_IR].eq(1)
 146                         self.o.msr[MSR_DR].eq(1)
 147                 comb += self.o.msr.ok.eq(1)
 148
 149             # move from SPR
 150             with m.Case(InternalOp.OP_MFMSR):
 151                 # TODO: some of the bits need zeroing?  apparently not
 152                 """
 153                     when OP_MFMSR =>
 154                         result := ctrl.msr;
 155                         result_en := '1';
 156                 """
 157                 comb += self.o.o.data.eq(self.i.msr)
 158                 comb += self.o.o.ok.eq(1)
 159
 160             # TODO
 161             with m.Case(InternalOp.OP_RFID):
 162                 """
 163                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 164                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 165                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 166                 -- Can't use msr_copy here because the partial function MSR
 167                 -- bits should be left unchanged, not zeroed.
 168                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 169                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 170                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 171                 if b_in(MSR_PR) = '1' then
 172                     ctrl_tmp.msr(MSR_EE) <= '1';
 173                     ctrl_tmp.msr(MSR_IR) <= '1';
 174                     ctrl_tmp.msr(MSR_DR) <= '1';
 175                 end if;
 176                 """
 177                 comb += self.o.msr.data[:16].eq(b[:16])
 178                 comb += self.o.msr.data[22:27].eq(b[22:27])
 179                 comb += self.o.msr.data[31:] # <- oops missed the eq here
 180                 comb += self.o.msr.ok.eq(1)
 181                 comb += self.o.msr.data.eq(b)
 182                 comb += self.o.msr.ok.eq(1)
 183
 184             # TODO
 185             with m.Case(InternalOp.OP_SC):
 186                 """
 187                 # TODO: scv must generate illegal instruction.  this is
 188                 # the decoder's job, not ours, here.
 189                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 190                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 191                 """
 192                 comb += self.o.nia.eq(0xC00) # trap address
 193                 comb += self.o.nia.ok.eq(1)
 194                 # TODO: srr1 (see 2nd line of vhdl above. remember set ok=1 too)
 195
 196             #with m.Case(InternalOp.OP_ADDPCIS):
 197             #    pass
 198
 199         comb += self.o.ctx.eq(self.i.ctx)
 200
 201         return m