src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 """
   5
   6 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, signed)
   7 from nmutil.pipemodbase import PipeModBase
   8 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
   9 from soc.decoder.power_enums import InternalOp
  10
  11 from soc.decoder.power_fields import DecodeFields
  12 from soc.decoder.power_fieldsn import SignalBitRange
  13
  14
  15 class TrapMainStage(PipeModBase):
  16     def __init__(self, pspec):
  17         super().__init__(pspec, "main")
  18         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  19         self.fields.create_specs()
  20
  21     def ispec(self):
  22         return TrapInputData(self.pspec)
  23
  24     def ospec(self):
  25         return TrapOutputData(self.pspec)
  26
  27     def elaborate(self, platform):
  28         m = Module()
  29         comb = m.d.comb
  30         op = self.i.ctx.op
  31
  32         # take copy of D-Form TO field
  33         i_fields = self.fields.FormD
  34         to = Signal(i_fields.TO[0:-1].shape())
  35         comb += to.eq(i_fields.TO[0:-1])
  36
  37         # signed/unsigned temporaries for RA and RB
  38         a_s = Signal(signed(64), reset_less=True)
  39         b_s = Signal(signed(64), reset_less=True)
  40
  41         a = Signal(64, reset_less=True)
  42         b = Signal(64, reset_less=True)
  43
  44         # set up A and B comparison (truncate/sign-extend if 32 bit)
  45         with m.If(op.is_32bit):
  46             comb += a_s.eq(self.i.a[0:32], Repl(self.i.a[32], 32))
  47             comb += b_s.eq(self.i.b[0:32], Repl(self.i.b[32], 32))
  48             comb += a.eq(self.i.a[0:32])
  49             comb += b.eq(self.i.b[0:32])
  50         with m.Else():
  51             comb += a_s.eq(self.i.a)
  52             comb += b_s.eq(self.i.b)
  53             comb += a.eq(self.i.a)
  54             comb += b.eq(self.i.b)
  55
  56         # establish comparison bits
  57         lt_s = Signal(reset_less=True)
  58         gt_s = Signal(reset_less=True)
  59         lt_u = Signal(reset_less=True)
  60         gt_u = Signal(reset_less=True)
  61         equal = Signal(reset_less=True)
  62
  63         comb += lt_s.eq(a_s < b_s)
  64         comb += gt_s.eq(a_s > b_s)
  65         comb += lt_u.eq(a < b)
  66         comb += gt_u.eq(a > b)
  67         comb += equal.eq(a == b)
  68
  69         # They're in reverse bit order because POWER.
  70         # Check V3.0B Book 1, Appendix C.6 for chart
  71         trap_bits = Signal(5)
  72         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  73
  74         # establish if the trap should go ahead (any tests requested in TO)
  75         should_trap = Signal()
  76         comb += should_trap.eq((trap_bits & to).any())
  77
  78         # TODO: some #defines for the bits n stuff.
  79         with m.Switch(op):
  80             with m.Case(InternalOp.OP_TRAP):
  81                 with m.If(should_trap):
  82                     comb += self.o.nia.data.eq(0x700)         # trap address
  83                     comb += self.o.nia.ok.eq(1)
  84                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
  85                     comb += self.o.srr1[63-46].eq(1)     # XXX which bit?
  86                     comb += self.o.srr1.ok.eq(1)
  87                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
  88                     comb += self.o.srr0.ok.eq(1)
  89
  90             # XXX TODO, needs the lines adding to the CSV files first
  91             #with m.Case(InternalOp.OP_MTMSR):
  92             #with m.Case(InternalOp.OP_MFMSR):
  93         comb += self.o.ctx.eq(self.i.ctx)
  94
  95         return m