src/soc/fu/trap/main_stage.py

   1 """Trap Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
   4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
   5 * https://libre-soc.org/openpower/isa/fixedtrap/
   6 """
   7
   8 from nmigen import (Module, Signal, Cat, Mux, Const, signed)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.extend import exts
  11 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
  12 from soc.fu.branch.main_stage import br_ext
  13 from soc.decoder.power_enums import InternalOp
  14
  15 from soc.decoder.power_fields import DecodeFields
  16 from soc.decoder.power_fieldsn import SignalBitRange
  17
  18
  19 # Listed in V3.0B Book III Chap 4.2.1
  20 # MSR bit numbers
  21 MSR_SF  = (63 - 0)     # Sixty-Four bit mode
  22 MSR_HV  = (63 - 3)     # Hypervisor state
  23 MSR_S   = (63 - 41)    # Secure state
  24 MSR_EE  = (63 - 48)    # External interrupt Enable
  25 MSR_PR  = (63 - 49)    # PRoblem state
  26 MSR_FP  = (63 - 50)    # FP available
  27 MSR_ME  = (63 - 51)    # Machine Check int enable
  28 MSR_IR  = (63 - 58)    # Instruction Relocation
  29 MSR_DR  = (63 - 59)    # Data Relocation
  30 MSR_PMM = (63 - 60)    # Performance Monitor Mark
  31 MSR_RI  = (63 - 62)    # Recoverable Interrupt
  32 MSR_LE  = (63 - 63)    # Little Endian
  33
  34
  35 class TrapMainStage(PipeModBase):
  36     def __init__(self, pspec):
  37         super().__init__(pspec, "main")
  38         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  39         self.fields.create_specs()
  40
  41     def ispec(self):
  42         return TrapInputData(self.pspec)
  43
  44     def ospec(self):
  45         return TrapOutputData(self.pspec)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         comb = m.d.comb
  50         op = self.i.ctx.op
  51
  52         a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr
  53         o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia
  54         srr0_o, srr1_o = self.o.srr0, self.o.srr1
  55
  56         # take copy of D-Form TO field
  57         i_fields = self.fields.FormD
  58         to = Signal(i_fields.TO[0:-1].shape())
  59         comb += to.eq(i_fields.TO[0:-1])
  60
  61         # signed/unsigned temporaries for RA and RB
  62         a_s = Signal(signed(64), reset_less=True)
  63         b_s = Signal(signed(64), reset_less=True)
  64
  65         a = Signal(64, reset_less=True)
  66         b = Signal(64, reset_less=True)
  67
  68         # set up A and B comparison (truncate/sign-extend if 32 bit)
  69         with m.If(op.is_32bit):
  70             comb += a_s.eq(exts(a_i, 32, 64))
  71             comb += b_s.eq(exts(b_i, 32, 64))
  72             comb += a.eq(a_i[0:32])
  73             comb += b.eq(b_i[0:32])
  74         with m.Else():
  75             comb += a_s.eq(a_i)
  76             comb += b_s.eq(b_i)
  77             comb += a.eq(a_i)
  78             comb += b.eq(b_i)
  79
  80         # establish comparison bits
  81         lt_s = Signal(reset_less=True)
  82         gt_s = Signal(reset_less=True)
  83         lt_u = Signal(reset_less=True)
  84         gt_u = Signal(reset_less=True)
  85         equal = Signal(reset_less=True)
  86
  87         comb += lt_s.eq(a_s < b_s)
  88         comb += gt_s.eq(a_s > b_s)
  89         comb += lt_u.eq(a < b)
  90         comb += gt_u.eq(a > b)
  91         comb += equal.eq(a == b)
  92
  93         # They're in reverse bit order because POWER.
  94         # Check V3.0B Book 1, Appendix C.6 for chart
  95         trap_bits = Signal(5)
  96         comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s))
  97
  98         # establish if the trap should go ahead (any tests requested in TO)
  99         should_trap = Signal()
 100         comb += should_trap.eq((trap_bits & to).any())
 101
 102         # TODO: some #defines for the bits n stuff.
 103         with m.Switch(op):
 104             #### trap ####
 105             with m.Case(InternalOp.OP_TRAP):
 106                 """
 107                 -- trap instructions (tw, twi, td, tdi)
 108                 if or (trapval and insn_to(e_in.insn)) = '1' then
 109                     -- generate trap-type program interrupt
 110                     exception := '1';
 111                     ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64));
 112                     ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 113                     -- set bit 46 to say trap occurred
 114                     ctrl_tmp.srr1(63 - 46) <= '1';
 115                 """
 116                 with m.If(should_trap):
 117                     comb += self.o.nia.data.eq(0x700)         # trap address
 118                     comb += self.o.nia.ok.eq(1)
 119                     comb += self.o.srr1.data.eq(self.i.msr)   # old MSR
 120                     comb += self.o.srr1.data[63-46].eq(1)     # XXX which bit?
 121                     comb += self.o.srr1.ok.eq(1)
 122                     comb += self.o.srr0.data.eq(self.i.cia)   # old PC
 123                     comb += self.o.srr0.ok.eq(1)
 124
 125             # move to SPR
 126             with m.Case(InternalOp.OP_MTMSR):
 127                 # TODO: some of the bits need zeroing?
 128                 """
 129                 if e_in.insn(16) = '1' then  <-- this is X-form field "L".
 130                     -- just update EE and RI
 131                     ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 132                     ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 133                 else
 134                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
 135                     -- and 63 (LE) (IBM bit numbering)
 136                     ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
 137                     ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
 138                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
 139                     if c_in(MSR_PR) = '1' then
 140                         ctrl_tmp.msr(MSR_EE) <= '1';
 141                         ctrl_tmp.msr(MSR_IR) <= '1';
 142                         ctrl_tmp.msr(MSR_DR) <= '1';
 143                 """
 144                 """
 145                 L = self.fields.FormXL.L[0:-1]
 146                 if e_in.insn(16) = '1' then  <-- this is X-form field "L".
 147                 -- just update EE and RI
 148                 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
 149                 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
 150                 """
 151                 L = self.fields.FormX.L[0:-1]
 152                 with m.If(L):
 153                     comb += self.o.msr[MSR_EE].eq(self.i.msr[MSR_EE])
 154                     comb += self.o.msr[MSR_RI].eq(self.i.msr[MSR_RI])
 155
 156                 with m.Else():
 157                     for stt, end in [(1,12), (13, 60), (61, 64)]:
 158                         comb += self.o.msr.data[stt:end].eq(a[stt:end])
 159                     with m.If(a[MSR_PR]):
 160                             self.o.msr[MSR_EE].eq(1)
 161                             self.o.msr[MSR_IR].eq(1)
 162                             self.o.msr[MSR_DR].eq(1)
 163                 comb += self.o.msr.ok.eq(1)
 164
 165             # move from SPR
 166             with m.Case(InternalOp.OP_MFMSR):
 167                 # TODO: some of the bits need zeroing?  apparently not
 168                 """
 169                     when OP_MFMSR =>
 170                         result := ctrl.msr;
 171                         result_en := '1';
 172                 """
 173                 comb += self.o.o.data.eq(self.i.msr)
 174                 comb += self.o.o.ok.eq(1)
 175
 176             with m.Case(InternalOp.OP_RFID):
 177                 """
 178                 # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR);
 179                 # XXX f_out.priv_mode <= not b_in(MSR_PR);
 180                 f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0
 181                 -- Can't use msr_copy here because the partial function MSR
 182                 -- bits should be left unchanged, not zeroed.
 183                 ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31);
 184                 ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22);
 185                 ctrl_tmp.msr(15 downto 0)  <= b_in(15 downto 0);
 186                 if b_in(MSR_PR) = '1' then
 187                     ctrl_tmp.msr(MSR_EE) <= '1';
 188                     ctrl_tmp.msr(MSR_IR) <= '1';
 189                     ctrl_tmp.msr(MSR_DR) <= '1';
 190                 end if;
 191                 """
 192                 comb += self.o.nia.data.eq(br_ext(a[63:1] & 0))
 193                 comb += self.o.nia.ok.eq(1)
 194                 for stt, end in [(0,16), (22, 27), (31, 64)]:
 195                     comb += self.o.msr.data[stt:end].eq(a[stt:end])
 196                 with m.If(a[MSR_PR]):
 197                         self.o.msr[MSR_EE].eq(1)
 198                         self.o.msr[MSR_IR].eq(1)
 199                         self.o.msr[MSR_DR].eq(1)
 200                 comb += self.o.msr.ok.eq(1)
 201
 202             with m.Case(InternalOp.OP_SC):
 203                 """
 204                 # TODO: scv must generate illegal instruction.  this is
 205                 # the decoder's job, not ours, here.
 206                 ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64));
 207                 ctrl_tmp.srr1 <= msr_copy(ctrl.msr);
 208                 """
 209                 comb += self.o.nia.eq(0xC00) # trap address
 210                 comb += self.o.nia.ok.eq(1)
 211                 comb += self.o.srr1.data.eq(self.i.msr)
 212                 comb += self.o.srr1.ok.eq(1)
 213
 214             # TODO (later)
 215             #with m.Case(InternalOp.OP_ADDPCIS):
 216             #    pass
 217
 218         comb += self.o.ctx.eq(self.i.ctx)
 219
 220         return m