3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
5 * https://libre-soc.org/openpower/isa/fixedtrap/
8 from nmigen
import (Module
, Signal
, Cat
, Mux
, Const
, signed
)
9 from nmutil
.pipemodbase
import PipeModBase
10 from nmutil
.extend
import exts
11 from soc
.fu
.trap
.pipe_data
import TrapInputData
, TrapOutputData
12 from soc
.fu
.branch
.main_stage
import br_ext
13 from soc
.decoder
.power_enums
import InternalOp
15 from soc
.decoder
.power_fields
import DecodeFields
16 from soc
.decoder
.power_fieldsn
import SignalBitRange
18 from soc
.decoder
.power_decoder2
import (TT_FP
, TT_PRIV
, TT_TRAP
, TT_ADDR
)
19 from soc
.consts
import MSR
, PI
21 def msr_copy(msr_o
, msr_i
, zero_me
=True):
24 -- Defined MSR bits are classified as either full func-
25 -- tion or partial function. Full function MSR bits are
26 -- saved in SRR1 or HSRR1 when an interrupt other
27 -- than a System Call Vectored interrupt occurs and
28 -- restored by rfscv, rfid, or hrfid, while partial func-
29 -- tion MSR bits are not saved or restored.
30 -- Full function MSR bits lie in the range 0:32, 37:41, and
31 -- 48:63, and partial function MSR bits lie in the range
32 -- 33:36 and 42:47. (Note this is IBM bit numbering).
33 msr_out := (others => '0');
34 msr_out(63 downto 31) := msr(63 downto 31);
35 msr_out(26 downto 22) := msr(26 downto 22);
36 msr_out(15 downto 0) := msr(15 downto 0);
41 for stt
, end
in [(0,16), (22, 27), (31, 64)]:
42 l
.append(msr_o
[stt
:end
].eq(msr_i
[stt
:end
]))
46 def msr_check_pr(m
, msr
):
47 """msr_check_pr: checks "problem state"
50 with m
.If(msr
[MSR
.PR
]):
51 comb
+= msr
[MSR
.EE
].eq(1) # set external interrupt bit
52 comb
+= msr
[MSR
.IR
].eq(1) # set instruction relocation bit
53 comb
+= msr
[MSR
.DR
].eq(1) # set data relocation bit
56 class TrapMainStage(PipeModBase
):
57 def __init__(self
, pspec
):
58 super().__init
__(pspec
, "main")
59 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
60 self
.fields
.create_specs()
62 def trap(self
, m
, trap_addr
, return_addr
):
63 """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0
67 nia_o
, srr0_o
, srr1_o
= self
.o
.nia
, self
.o
.srr0
, self
.o
.srr1
70 comb
+= nia_o
.data
.eq(trap_addr
)
71 comb
+= nia_o
.ok
.eq(1)
73 # addr to begin from on return
74 comb
+= srr0_o
.data
.eq(return_addr
)
75 comb
+= srr0_o
.ok
.eq(1)
77 # take a copy of the current MSR in SRR1
78 comb
+= msr_copy(srr1_o
.data
, msr_i
) # old MSR
79 comb
+= srr1_o
.ok
.eq(1)
82 return TrapInputData(self
.pspec
)
85 return TrapOutputData(self
.pspec
)
87 def elaborate(self
, platform
):
92 # convenience variables
93 a_i
, b_i
, cia_i
, msr_i
= self
.i
.a
, self
.i
.b
, self
.i
.cia
, self
.i
.msr
94 srr0_i
, srr1_i
= self
.i
.srr0
, self
.i
.srr1
95 o
, msr_o
, nia_o
= self
.o
.o
, self
.o
.msr
, self
.o
.nia
96 srr0_o
, srr1_o
= self
.o
.srr0
, self
.o
.srr1
97 traptype
, trapaddr
= op
.traptype
, op
.trapaddr
99 # take copy of D-Form TO field
100 i_fields
= self
.fields
.FormD
101 to
= Signal(i_fields
.TO
[0:-1].shape())
102 comb
+= to
.eq(i_fields
.TO
[0:-1])
104 # signed/unsigned temporaries for RA and RB
105 a_s
= Signal(signed(64), reset_less
=True)
106 b_s
= Signal(signed(64), reset_less
=True)
108 a
= Signal(64, reset_less
=True)
109 b
= Signal(64, reset_less
=True)
111 # set up A and B comparison (truncate/sign-extend if 32 bit)
112 with m
.If(op
.is_32bit
):
113 comb
+= a_s
.eq(exts(a_i
, 32, 64))
114 comb
+= b_s
.eq(exts(b_i
, 32, 64))
115 comb
+= a
.eq(a_i
[0:32])
116 comb
+= b
.eq(b_i
[0:32])
123 # establish comparison bits
124 lt_s
= Signal(reset_less
=True)
125 gt_s
= Signal(reset_less
=True)
126 lt_u
= Signal(reset_less
=True)
127 gt_u
= Signal(reset_less
=True)
128 equal
= Signal(reset_less
=True)
130 comb
+= lt_s
.eq(a_s
< b_s
)
131 comb
+= gt_s
.eq(a_s
> b_s
)
132 comb
+= lt_u
.eq(a
< b
)
133 comb
+= gt_u
.eq(a
> b
)
134 comb
+= equal
.eq(a
== b
)
136 # They're in reverse bit order because POWER.
137 # Check V3.0B Book 1, Appendix C.6 for chart
138 trap_bits
= Signal(5, reset_less
=True)
139 comb
+= trap_bits
.eq(Cat(gt_u
, lt_u
, equal
, gt_s
, lt_s
))
141 # establish if the trap should go ahead (any tests requested in TO)
142 # or if traptype is set already
143 should_trap
= Signal(reset_less
=True)
144 comb
+= should_trap
.eq((trap_bits
& to
).any() | traptype
.any())
146 # TODO: some #defines for the bits n stuff.
147 with m
.Switch(op
.insn_type
):
149 with m
.Case(InternalOp
.OP_TRAP
):
150 # trap instructions (tw, twi, td, tdi)
151 with m
.If(should_trap
):
152 # generate trap-type program interrupt
153 self
.trap(m
, trapaddr
<<4, cia_i
)
154 with m
.If(traptype
== 0):
155 # say trap occurred (see 3.0B Book III 7.5.9)
156 comb
+= srr1_o
.data
[PI
.TRAP
].eq(1)
157 with m
.If(traptype
& TT_PRIV
):
158 comb
+= srr1_o
.data
[PI
.PRIV
].eq(1)
159 with m
.If(traptype
& TT_FP
):
160 comb
+= srr1_o
.data
[PI
.FP
].eq(1)
161 with m
.If(traptype
& TT_ADDR
):
162 comb
+= srr1_o
.data
[PI
.ADR
].eq(1)
165 with m
.Case(InternalOp
.OP_MTMSRD
):
166 L
= self
.fields
.FormX
.L
[0:-1] # X-Form field L
168 # just update EE and RI
169 comb
+= msr_o
.data
[MSR
.EE
].eq(a_i
[MSR
.EE
])
170 comb
+= msr_o
.data
[MSR
.RI
].eq(a_i
[MSR
.RI
])
172 # Architecture says to leave out bits 3 (HV), 51 (ME)
173 # and 63 (LE) (IBM bit numbering)
174 for stt
, end
in [(1,12), (13, 60), (61, 64)]:
175 comb
+= msr_o
.data
[stt
:end
].eq(a_i
[stt
:end
])
176 msr_check_pr(m
, msr_o
.data
)
177 comb
+= msr_o
.ok
.eq(1)
180 with m
.Case(InternalOp
.OP_MFMSR
):
181 # TODO: some of the bits need zeroing? apparently not
182 comb
+= o
.data
.eq(msr_i
)
185 with m
.Case(InternalOp
.OP_RFID
):
186 # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
187 # XXX f_out.priv_mode <= not b_in(MSR.PR);
189 # return addr was in srr0
190 comb
+= nia_o
.data
.eq(br_ext(srr0_i
[2:]))
191 comb
+= nia_o
.ok
.eq(1)
193 comb
+= msr_copy(msr_o
.data
, srr1_i
, zero_me
=False) # don't zero
194 msr_check_pr(m
, msr_o
.data
)
195 comb
+= msr_o
.ok
.eq(1)
197 # TODO (later) - add OP_SC
198 #with m.Case(InternalOp.OP_SC):
199 # # TODO: scv must generate illegal instruction. this is
200 # # the decoder's job, not ours, here.
202 # # jump to the trap address, return at cia+4
203 # self.trap(m, 0xc00, cia_i+4)
206 #with m.Case(InternalOp.OP_ADDPCIS):
209 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)