src/soc/fu/trap/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14
  15 from soc.fu.test.common import (TestCase, ALUHelpers)
  16 from soc.fu.trap.pipeline import TrapBasePipe
  17 from soc.fu.trap.pipe_data import TrapPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to TrapFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
  27     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
  28     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
  29     yield from ALUHelpers.get_sim_cia(res, sim, dec2) # PC
  30     yield from ALUHelpers.get_sim_msr(res, sim, dec2) # MSR
  31
  32     print ("alu get_cu_inputs", res)
  33
  34     return res
  35
  36
  37
  38 def set_alu_inputs(alu, dec2, sim):
  39     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  40     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  41     # and place it into data_i.b
  42
  43     inp = yield from get_cu_inputs(dec2, sim)
  44     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  45     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  46
  47     yield from ALUHelpers.set_fast_cia(alu, dec2, inp)
  48     yield from ALUHelpers.set_fast_msr(alu, dec2, inp)
  49
  50
  51 # This test bench is a bit different than is usual. Initially when I
  52 # was writing it, I had all of the tests call a function to create a
  53 # device under test and simulator, initialize the dut, run the
  54 # simulation for ~2 cycles, and assert that the dut output what it
  55 # should have. However, this was really slow, since it needed to
  56 # create and tear down the dut and simulator for every test case.
  57
  58 # Now, instead of doing that, every test case in TrapTestCase puts some
  59 # data into the test_data list below, describing the instructions to
  60 # be tested and the initial state. Once all the tests have been run,
  61 # test_data gets passed to TestRunner which then sets up the DUT and
  62 # simulator once, runs all the data through it, and asserts that the
  63 # results match the pseudocode sim at every cycle.
  64
  65 # By doing this, I've reduced the time it takes to run the test suite
  66 # massively. Before, it took around 1 minute on my computer, now it
  67 # takes around 3 seconds
  68
  69
  70 class TrapTestCase(FHDLTestCase):
  71     test_data = []
  72
  73     def __init__(self, name):
  74         super().__init__(name)
  75         self.test_name = name
  76
  77     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
  78         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
  79         self.test_data.append(tc)
  80
  81     def test_1_regression(self):
  82         lst = [f"extsw 3, 1"]
  83         initial_regs = [0] * 32
  84         initial_regs[1] = 0xb6a1fc6c8576af91
  85         self.run_tst_program(Program(lst), initial_regs)
  86         lst = [f"subf 3, 1, 2"]
  87         initial_regs = [0] * 32
  88         initial_regs[1] = 0x3d7f3f7ca24bac7b
  89         initial_regs[2] = 0xf6b2ac5e13ee15c2
  90         self.run_tst_program(Program(lst), initial_regs)
  91         lst = [f"subf 3, 1, 2"]
  92         initial_regs = [0] * 32
  93         initial_regs[1] = 0x833652d96c7c0058
  94         initial_regs[2] = 0x1c27ecff8a086c1a
  95         self.run_tst_program(Program(lst), initial_regs)
  96         lst = [f"extsb 3, 1"]
  97         initial_regs = [0] * 32
  98         initial_regs[1] = 0x7f9497aaff900ea0
  99         self.run_tst_program(Program(lst), initial_regs)
 100         lst = [f"add. 3, 1, 2"]
 101         initial_regs = [0] * 32
 102         initial_regs[1] = 0xc523e996a8ff6215
 103         initial_regs[2] = 0xe1e5b9cc9864c4a8
 104         self.run_tst_program(Program(lst), initial_regs)
 105         lst = [f"add 3, 1, 2"]
 106         initial_regs = [0] * 32
 107         initial_regs[1] = 0x2e08ae202742baf8
 108         initial_regs[2] = 0x86c43ece9efe5baa
 109         self.run_tst_program(Program(lst), initial_regs)
 110
 111     def test_rand(self):
 112         insns = ["add", "add.", "subf"]
 113         for i in range(40):
 114             choice = random.choice(insns)
 115             lst = [f"{choice} 3, 1, 2"]
 116             initial_regs = [0] * 32
 117             initial_regs[1] = random.randint(0, (1<<64)-1)
 118             initial_regs[2] = random.randint(0, (1<<64)-1)
 119             self.run_tst_program(Program(lst), initial_regs)
 120
 121     def test_rand_imm(self):
 122         insns = ["addi", "addis", "subfic"]
 123         for i in range(10):
 124             choice = random.choice(insns)
 125             imm = random.randint(-(1<<15), (1<<15)-1)
 126             lst = [f"{choice} 3, 1, {imm}"]
 127             print(lst)
 128             initial_regs = [0] * 32
 129             initial_regs[1] = random.randint(0, (1<<64)-1)
 130             self.run_tst_program(Program(lst), initial_regs)
 131
 132     def test_0_adde(self):
 133         lst = ["adde. 5, 6, 7"]
 134         for i in range(10):
 135             initial_regs = [0] * 32
 136             initial_regs[6] = random.randint(0, (1<<64)-1)
 137             initial_regs[7] = random.randint(0, (1<<64)-1)
 138             initial_sprs = {}
 139             xer = SelectableInt(0, 64)
 140             xer[XER_bits['CA']] = 1
 141             initial_sprs[special_sprs['XER']] = xer
 142             self.run_tst_program(Program(lst), initial_regs, initial_sprs)
 143
 144     def test_cmp(self):
 145         lst = ["subf. 1, 6, 7",
 146                "cmp cr2, 1, 6, 7"]
 147         initial_regs = [0] * 32
 148         initial_regs[6] = 0x10
 149         initial_regs[7] = 0x05
 150         self.run_tst_program(Program(lst), initial_regs, {})
 151
 152     def test_extsb(self):
 153         insns = ["extsb", "extsh", "extsw"]
 154         for i in range(10):
 155             choice = random.choice(insns)
 156             lst = [f"{choice} 3, 1"]
 157             print(lst)
 158             initial_regs = [0] * 32
 159             initial_regs[1] = random.randint(0, (1<<64)-1)
 160             self.run_tst_program(Program(lst), initial_regs)
 161
 162     def test_cmpeqb(self):
 163         lst = ["cmpeqb cr1, 1, 2"]
 164         for i in range(20):
 165             initial_regs = [0] * 32
 166             initial_regs[1] = i
 167             initial_regs[2] = 0x0001030507090b0f
 168             self.run_tst_program(Program(lst), initial_regs, {})
 169
 170     def test_ilang(self):
 171         pspec = TrapPipeSpec(id_wid=2)
 172         alu = TrapBasePipe(pspec)
 173         vl = rtlil.convert(alu, ports=alu.ports())
 174         with open("alu_pipeline.il", "w") as f:
 175             f.write(vl)
 176
 177
 178 class TestRunner(FHDLTestCase):
 179     def __init__(self, test_data):
 180         super().__init__("run_all")
 181         self.test_data = test_data
 182
 183     def run_all(self):
 184         m = Module()
 185         comb = m.d.comb
 186         instruction = Signal(32)
 187
 188         pdecode = create_pdecode()
 189
 190         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 191
 192         pspec = TrapPipeSpec(id_wid=2)
 193         m.submodules.alu = alu = TrapBasePipe(pspec)
 194
 195         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
 196         comb += alu.p.valid_i.eq(1)
 197         comb += alu.n.ready_i.eq(1)
 198         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 199         sim = Simulator(m)
 200
 201         sim.add_clock(1e-6)
 202         def process():
 203             for test in self.test_data:
 204                 print(test.name)
 205                 program = test.program
 206                 self.subTest(test.name)
 207                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
 208                                 test.mem, test.msr)
 209                 gen = program.generate_instructions()
 210                 instructions = list(zip(gen, program.assembly.splitlines()))
 211
 212                 index = sim.pc.CIA.value//4
 213                 while index < len(instructions):
 214                     ins, code = instructions[index]
 215
 216                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 217                     print(code)
 218                     if 'XER' in sim.spr:
 219                         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 220                         ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
 221                         ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
 222                         print ("before: so/ov/32", so, ov, ov32)
 223
 224                     # ask the decoder to decode this binary data (endian'd)
 225                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 226                     yield instruction.eq(ins)          # raw binary instr.
 227                     yield Settle()
 228                     fn_unit = yield pdecode2.e.fn_unit
 229                     self.assertEqual(fn_unit, Function.Trap.value)
 230                     yield from set_alu_inputs(alu, pdecode2, sim)
 231                     yield
 232                     opname = code.split(' ')[0]
 233                     yield from sim.call(opname)
 234                     index = sim.pc.CIA.value//4
 235
 236                     vld = yield alu.n.valid_o
 237                     while not vld:
 238                         yield
 239                         vld = yield alu.n.valid_o
 240                     yield
 241
 242                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 243
 244         sim.add_sync_process(process)
 245         with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
 246                             traces=[]):
 247             sim.run()
 248
 249     def check_alu_outputs(self, alu, dec2, sim, code):
 250
 251         rc = yield dec2.e.rc.data
 252         cridx_ok = yield dec2.e.write_cr.ok
 253         cridx = yield dec2.e.write_cr.data
 254
 255         print ("check extra output", repr(code), cridx_ok, cridx)
 256         if rc:
 257             self.assertEqual(cridx, 0, code)
 258
 259         oe = yield dec2.e.oe.oe
 260         oe_ok = yield dec2.e.oe.ok
 261         if not oe or not oe_ok:
 262             # if OE not enabled, XER SO and OV must correspondingly be false
 263             so_ok = yield alu.n.data_o.xer_so.ok
 264             ov_ok = yield alu.n.data_o.xer_ov.ok
 265             self.assertEqual(so_ok, False, code)
 266             self.assertEqual(ov_ok, False, code)
 267
 268         sim_o = {}
 269         res = {}
 270
 271         yield from ALUHelpers.get_int_o(res, alu, dec2)
 272         yield from ALUHelpers.get_fast_spr1(res, alu, dec2)
 273         yield from ALUHelpers.get_fast_spr2(res, alu, dec2)
 274         yield from ALUHelpers.get_fast_nia(res, alu, dec2)
 275         yield from ALUHelpers.get_fast_msr(res, alu, dec2)
 276
 277         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 278         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 279         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 280         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 281         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 282
 283         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 284         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 285         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 286         ALUHelpers.check_int_o(self, res, sim_o, code)
 287         ALUHelpers.check_xer_so(self, res, sim_o, code)
 288
 289
 290 if __name__ == "__main__":
 291     unittest.main(exit=False)
 292     suite = unittest.TestSuite()
 293     suite.addTest(TestRunner(TrapTestCase.test_data))
 294
 295     runner = unittest.TextTestRunner()
 296     runner.run(suite)