src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux
  23 from nmigen.cli import rtlil
  24
  25 from openpower.decoder.power_decoder2 import PowerDecodeSubset
  26 from openpower.decoder.power_regspec_map import regspec_decode_read
  27 from openpower.decoder.power_regspec_map import regspec_decode_write
  28 from openpower.sv.svp64 import SVP64Rec
  29
  30 from nmutil.picker import PriorityPicker
  31 from nmutil.util import treereduce
  32 from nmutil.singlepipe import ControlBase
  33
  34 from soc.fu.compunits.compunits import AllFunctionUnits
  35 from soc.regfile.regfiles import RegFiles
  36 from openpower.decoder.decode2execute1 import Decode2ToExecute1Type
  37 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
  38 from openpower.decoder.power_decoder2 import get_rdflags
  39 from openpower.decoder.decode2execute1 import Data
  40 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  41 from soc.config.test.test_loadstore import TestMemPspec
  42 from openpower.decoder.power_enums import MicrOp, Function
  43 from soc.config.state import CoreState
  44
  45 from collections import defaultdict
  46 import operator
  47
  48 from nmutil.util import rising_edge
  49
  50
  51 # helper function for reducing a list of signals down to a parallel
  52 # ORed single signal.
  53 def ortreereduce(tree, attr="o_data"):
  54     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  55
  56
  57 def ortreereduce_sig(tree):
  58     return treereduce(tree, operator.or_, lambda x: x)
  59
  60
  61 # helper function to place full regs declarations first
  62 def sort_fuspecs(fuspecs):
  63     res = []
  64     for (regname, fspec) in fuspecs.items():
  65         if regname.startswith("full"):
  66             res.append((regname, fspec))
  67     for (regname, fspec) in fuspecs.items():
  68         if not regname.startswith("full"):
  69             res.append((regname, fspec))
  70     return res  # enumerate(res)
  71
  72
  73 class CoreInput:
  74     """CoreInput: this is the input specification for Signals coming into core.
  75
  76     * state.  this contains PC, MSR, and SVSTATE. this is crucial information.
  77       (TODO: bigendian_i should really be read from the relevant MSR bit)
  78
  79     * the previously-decoded instruction goes into the Decode2Execute1Type
  80       data structure. no need for Core to re-decode that.  however note
  81       that *satellite* decoders *are* part of Core.
  82
  83     * the raw instruction. this is used by satellite decoders internal to
  84       Core, to provide Function-Unit-specific information.  really, they
  85       should be part of the actual ALU itself (in order to reduce wires),
  86       but hey.
  87
  88     * other stuff is related to SVP64.  the 24-bit SV REMAP field containing
  89       Vector context, etc.
  90     """
  91     def __init__(self, pspec, svp64_en, regreduce_en):
  92         self.pspec = pspec
  93         self.svp64_en = svp64_en
  94         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand,
  95                                 regreduce_en=regreduce_en)
  96
  97         # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
  98         self.sv_a_nz = Signal()
  99
 100         # state and raw instruction (and SVP64 ReMap fields)
 101         self.state = CoreState("core")
 102         self.raw_insn_i = Signal(32) # raw instruction
 103         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 104         if svp64_en:
 105             self.sv_rm = SVP64Rec(name="core_svp64_rm") # SVP64 RM field
 106             self.is_svp64_mode = Signal() # set if SVP64 mode is enabled
 107             self.use_svp64_ldst_dec = Signal() # use alternative LDST decoder
 108             self.sv_pred_sm = Signal() # TODO: SIMD width
 109             self.sv_pred_dm = Signal() # TODO: SIMD width
 110
 111     def eq(self, i):
 112         self.e.eq(i.e)
 113         self.sv_a_nz.eq(i.sv_a_nz)
 114         self.state.eq(i.state)
 115         self.raw_insn_i.eq(i.raw_insn_i)
 116         self.bigendian_i.eq(i.bigendian_i)
 117         if not self.svp64_en:
 118             return
 119         self.sv_rm.eq(i.sv_rm)
 120         self.is_svp64_mode.eq(i.is_svp64_mode)
 121         self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
 122         self.sv_pred_sm.eq(i.sv_pred_sm)
 123         self.sv_pred_dm.eq(i.sv_pred_dm)
 124
 125
 126 class CoreOutput:
 127     def __init__(self):
 128         # start/stop and terminated signalling
 129         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 130         self.exc_happened = Signal()             # exception happened
 131
 132     def eq(self, i):
 133         self.core_terminate_o.eq(i.core_terminate_o)
 134         self.exc_happened.eq(i.exc_happened)
 135
 136
 137 # derive from ControlBase rather than have a separate Stage instance,
 138 # this is simpler to do
 139 class NonProductionCore(ControlBase):
 140     def __init__(self, pspec):
 141         self.pspec = pspec
 142
 143         # test is SVP64 is to be enabled
 144         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
 145
 146         # test to see if regfile ports should be reduced
 147         self.regreduce_en = (hasattr(pspec, "regreduce") and
 148                              (pspec.regreduce == True))
 149
 150         super().__init__(stage=self)
 151
 152         # single LD/ST funnel for memory access
 153         self.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
 154         pi = l0.l0.dports[0]
 155
 156         # function units (only one each)
 157         # only include mmu if enabled in pspec
 158         self.fus = AllFunctionUnits(pspec, pilist=[pi])
 159
 160         # link LoadStore1 into MMU
 161         mmu = self.fus.get_fu('mmu0')
 162         print ("core pspec", pspec.ldst_ifacetype)
 163         print ("core mmu", mmu)
 164         print ("core lsmem.lsi", l0.cmpi.lsmem.lsi)
 165         if mmu is not None:
 166             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 167
 168         # register files (yes plural)
 169         self.regs = RegFiles(pspec)
 170
 171         # set up input and output: unusual requirement to set data directly
 172         # (due to the way that the core is set up in a different domain,
 173         # see TestIssuer.setup_peripherals
 174         self.i, self.o = self.new_specs(None)
 175         self.i, self.o = self.p.i_data, self.n.o_data
 176
 177         # create per-FU instruction decoders (subsetted)
 178         self.decoders = {}
 179         self.des = {}
 180
 181         for funame, fu in self.fus.fus.items():
 182             f_name = fu.fnunit.name
 183             fnunit = fu.fnunit.value
 184             opkls = fu.opsubsetkls
 185             if f_name == 'TRAP':
 186                 # TRAP decoder is the *main* decoder
 187                 self.trapunit = funame
 188                 continue
 189             self.decoders[funame] = PowerDecodeSubset(None, opkls, f_name,
 190                                                       final=True,
 191                                                       state=self.i.state,
 192                                             svp64_en=self.svp64_en,
 193                                             regreduce_en=self.regreduce_en)
 194             self.des[funame] = self.decoders[funame].do
 195
 196         if "mmu0" in self.decoders:
 197             self.decoders["mmu0"].mmu0_spr_dec = self.decoders["spr0"]
 198
 199     def setup(self, m, i):
 200         pass
 201
 202     def ispec(self):
 203         return CoreInput(self.pspec, self.svp64_en, self.regreduce_en)
 204
 205     def ospec(self):
 206         return CoreOutput()
 207
 208     def elaborate(self, platform):
 209         m = super().elaborate(platform)
 210
 211         # for testing purposes, to cut down on build time in coriolis2
 212         if hasattr(self.pspec, "nocore") and self.pspec.nocore == True:
 213             x = Signal() # dummy signal
 214             m.d.sync += x.eq(~x)
 215             return m
 216         comb = m.d.comb
 217
 218         m.submodules.fus = self.fus
 219         m.submodules.l0 = l0 = self.l0
 220         self.regs.elaborate_into(m, platform)
 221         regs = self.regs
 222         fus = self.fus.fus
 223
 224         # connect decoders
 225         self.connect_satellite_decoders(m)
 226
 227         # ssh, cheat: trap uses the main decoder because of the rewriting
 228         self.des[self.trapunit] = self.i.e.do
 229
 230         # connect up Function Units, then read/write ports
 231         fu_bitdict, fu_selected = self.connect_instruction(m)
 232         self.connect_rdports(m, fu_selected)
 233         self.connect_wrports(m, fu_selected)
 234
 235         # note if an exception happened.  in a pipelined or OoO design
 236         # this needs to be accompanied by "shadowing" (or stalling)
 237         el = []
 238         for exc in self.fus.excs.values():
 239             el.append(exc.happened)
 240         if len(el) > 0: # at least one exception
 241             comb += self.o.exc_happened.eq(Cat(*el).bool())
 242
 243         return m
 244
 245     def connect_satellite_decoders(self, m):
 246         comb = m.d.comb
 247         for k, v in self.decoders.items():
 248             # connect each satellite decoder and give it the instruction.
 249             # as subset decoders this massively reduces wire fanout given
 250             # the large number of ALUs
 251             setattr(m.submodules, "dec_%s" % v.fn_name, v)
 252             comb += v.dec.raw_opcode_in.eq(self.i.raw_insn_i)
 253             comb += v.dec.bigendian.eq(self.i.bigendian_i)
 254             # sigh due to SVP64 RA_OR_ZERO detection connect these too
 255             comb += v.sv_a_nz.eq(self.i.sv_a_nz)
 256             if self.svp64_en:
 257                 comb += v.pred_sm.eq(self.i.sv_pred_sm)
 258                 comb += v.pred_dm.eq(self.i.sv_pred_dm)
 259                 if k != self.trapunit:
 260                     comb += v.sv_rm.eq(self.i.sv_rm) # pass through SVP64 ReMap
 261                     comb += v.is_svp64_mode.eq(self.i.is_svp64_mode)
 262                     # only the LDST PowerDecodeSubset *actually* needs to
 263                     # know to use the alternative decoder.  this is all
 264                     # a terrible hack
 265                     if k.lower().startswith("ldst"):
 266                         comb += v.use_svp64_ldst_dec.eq(
 267                                         self.i.use_svp64_ldst_dec)
 268
 269     def connect_instruction(self, m):
 270         """connect_instruction
 271
 272         uses decoded (from PowerOp) function unit information from CSV files
 273         to ascertain which Function Unit should deal with the current
 274         instruction.
 275
 276         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 277         ignoring it and halting the processor.  OP_NOP is a bit annoying
 278         because the issuer expects busy flag still to be raised then lowered.
 279         (this requires a fake counter to be set).
 280         """
 281         comb, sync = m.d.comb, m.d.sync
 282         fus = self.fus.fus
 283
 284         # indicate if core is busy
 285         busy_o = Signal(name="corebusy_o", reset_less=True)
 286
 287         # enable/busy-signals for each FU, get one bit for each FU (by name)
 288         fu_enable = Signal(len(fus), reset_less=True)
 289         fu_busy = Signal(len(fus), reset_less=True)
 290         fu_bitdict = {}
 291         fu_selected = {}
 292         for i, funame in enumerate(fus.keys()):
 293             fu_bitdict[funame] = fu_enable[i]
 294             fu_selected[funame] = fu_busy[i]
 295
 296         # identify function units and create a list by fnunit so that
 297         # PriorityPickers can be created for selecting one of them that
 298         # isn't busy at the time the incoming instruction needs passing on
 299         by_fnunit = defaultdict(list)
 300         for fname, member in Function.__members__.items():
 301             for funame, fu in fus.items():
 302                 fnunit = fu.fnunit.value
 303                 if member.value & fnunit: # this FU handles this type of op
 304                     by_fnunit[fname].append((funame, fu)) # add by Function
 305
 306         # ok now just print out the list of FUs by Function, because we can
 307         for fname, fu_list in by_fnunit.items():
 308             print ("FUs by type", fname, fu_list)
 309
 310         # now create a PriorityPicker per FU-type such that only one
 311         # non-busy FU will be picked
 312         issue_pps = {}
 313         fu_found = Signal() # take a note if no Function Unit was available
 314         for fname, fu_list in by_fnunit.items():
 315             i_pp = PriorityPicker(len(fu_list))
 316             m.submodules['i_pp_%s' % fname] = i_pp
 317             i_l = []
 318             for i, (funame, fu) in enumerate(fu_list):
 319                 # match the decoded instruction (e.do.fn_unit) against the
 320                 # "capability" of this FU, gate that by whether that FU is
 321                 # busy, and drop that into the PriorityPicker.
 322                 # this will give us an output of the first available *non-busy*
 323                 # Function Unit (Reservation Statio) capable of handling this
 324                 # instruction.
 325                 fnunit = fu.fnunit.value
 326                 en_req = Signal(name="issue_en_%s" % funame, reset_less=True)
 327                 fnmatch = (self.i.e.do.fn_unit & fnunit).bool()
 328                 comb += en_req.eq(fnmatch & ~fu.busy_o & self.p.i_valid)
 329                 i_l.append(en_req) # store in list for doing the Cat-trick
 330                 # picker output, gated by enable: store in fu_bitdict
 331                 po = Signal(name="o_issue_pick_"+funame) # picker output
 332                 comb += po.eq(i_pp.o[i] & i_pp.en_o)
 333                 comb += fu_bitdict[funame].eq(po)
 334                 comb += fu_selected[funame].eq(fu.busy_o | po)
 335                 # if we don't do this, then when there are no FUs available,
 336                 # the "p.o_ready" signal will go back "ok we accepted this
 337                 # instruction" which of course isn't true.
 338                 comb += fu_found.eq(~fnmatch | i_pp.en_o)
 339             # for each input, Cat them together and drop them into the picker
 340             comb += i_pp.i.eq(Cat(*i_l))
 341
 342         # sigh - need a NOP counter
 343         counter = Signal(2)
 344         with m.If(counter != 0):
 345             sync += counter.eq(counter - 1)
 346             comb += busy_o.eq(1)
 347
 348         with m.If(self.p.i_valid): # run only when valid
 349             with m.Switch(self.i.e.do.insn_type):
 350                 # check for ATTN: halt if true
 351                 with m.Case(MicrOp.OP_ATTN):
 352                     m.d.sync += self.o.core_terminate_o.eq(1)
 353
 354                 # fake NOP - this isn't really used (Issuer detects NOP)
 355                 with m.Case(MicrOp.OP_NOP):
 356                     sync += counter.eq(2)
 357                     comb += busy_o.eq(1)
 358
 359                 with m.Default():
 360                     # connect up instructions.  only one enabled at a time
 361                     for funame, fu in fus.items():
 362                         do = self.des[funame]
 363                         enable = fu_bitdict[funame]
 364
 365                         # run this FunctionUnit if enabled
 366                         # route op, issue, busy, read flags and mask to FU
 367                         with m.If(enable):
 368                             # operand comes from the *local*  decoder
 369                             comb += fu.oper_i.eq_from(do)
 370                             comb += fu.issue_i.eq(1) # issue when input valid
 371                             # rdmask, which is for registers, needs to come
 372                             # from the *main* decoder
 373                             rdmask = get_rdflags(self.i.e, fu)
 374                             comb += fu.rdmaskn.eq(~rdmask)
 375
 376         # if instruction is busy, set busy output for core.
 377         busys = map(lambda fu: fu.busy_o, fus.values())
 378         comb += busy_o.eq(Cat(*busys).bool())
 379
 380         # ready/valid signalling.  if busy, means refuse incoming issue.
 381         # (this is a global signal, TODO, change to one which allows
 382         # overlapping instructions)
 383         # also, if there was no fu found we must not send back a valid
 384         # indicator.  BUT, of course, when there is no instruction
 385         # we must ignore the fu_found flag, otherwise o_ready will never
 386         # be set when everything is idle
 387         comb += self.p.o_ready.eq(~busy_o & (fu_found | ~self.p.i_valid))
 388
 389         # return both the function unit "enable" dict as well as the "busy".
 390         # the "busy-or-issued" can be passed in to the Read/Write port
 391         # connecters to give them permission to request access to regfiles
 392         return fu_bitdict, fu_selected
 393
 394     def connect_rdport(self, m, fu_bitdict, rdpickers, regfile, regname, fspec):
 395         comb, sync = m.d.comb, m.d.sync
 396         fus = self.fus.fus
 397         regs = self.regs
 398
 399         rpidx = regname
 400
 401         # select the required read port.  these are pre-defined sizes
 402         rfile = regs.rf[regfile.lower()]
 403         rport = rfile.r_ports[rpidx]
 404         print("read regfile", rpidx, regfile, regs.rf.keys(),
 405                               rfile, rfile.unary)
 406
 407         fspecs = fspec
 408         if not isinstance(fspecs, list):
 409             fspecs = [fspecs]
 410
 411         rdflags = []
 412         pplen = 0
 413         reads = []
 414         ppoffs = []
 415         for i, fspec in enumerate(fspecs):
 416             # get the regfile specs for this regfile port
 417             (rf, read, write, wid, fuspec) = fspec
 418             print ("fpsec", i, fspec, len(fuspec))
 419             ppoffs.append(pplen) # record offset for picker
 420             pplen += len(fuspec)
 421             name = "rdflag_%s_%s_%d" % (regfile, regname, i)
 422             rdflag = Signal(name=name, reset_less=True)
 423             comb += rdflag.eq(rf)
 424             rdflags.append(rdflag)
 425             reads.append(read)
 426
 427         print ("pplen", pplen)
 428
 429         # create a priority picker to manage this port
 430         rdpickers[regfile][rpidx] = rdpick = PriorityPicker(pplen)
 431         setattr(m.submodules, "rdpick_%s_%s" % (regfile, rpidx), rdpick)
 432
 433         rens = []
 434         addrs = []
 435         for i, fspec in enumerate(fspecs):
 436             (rf, read, write, wid, fuspec) = fspec
 437             # connect up the FU req/go signals, and the reg-read to the FU
 438             # and create a Read Broadcast Bus
 439             for pi, (funame, fu, idx) in enumerate(fuspec):
 440                 pi += ppoffs[i]
 441
 442                 # connect request-read to picker input, and output to go-rd
 443                 fu_active = fu_bitdict[funame]
 444                 name = "%s_%s_%s_%i" % (regfile, rpidx, funame, pi)
 445                 addr_en = Signal.like(reads[i], name="addr_en_"+name)
 446                 pick = Signal(name="pick_"+name)     # picker input
 447                 rp = Signal(name="rp_"+name)         # picker output
 448                 delay_pick = Signal(name="dp_"+name) # read-enable "underway"
 449
 450                 # exclude any currently-enabled read-request (mask out active)
 451                 comb += pick.eq(fu.rd_rel_o[idx] & fu_active & rdflags[i] &
 452                                 ~delay_pick)
 453                 comb += rdpick.i[pi].eq(pick)
 454                 comb += fu.go_rd_i[idx].eq(delay_pick) # pass in *delayed* pick
 455
 456                 # if picked, select read-port "reg select" number to port
 457                 comb += rp.eq(rdpick.o[pi] & rdpick.en_o)
 458                 sync += delay_pick.eq(rp) # delayed "pick"
 459                 comb += addr_en.eq(Mux(rp, reads[i], 0))
 460
 461                 # the read-enable happens combinatorially (see mux-bus below)
 462                 # but it results in the data coming out on a one-cycle delay.
 463                 if rfile.unary:
 464                     rens.append(addr_en)
 465                 else:
 466                     addrs.append(addr_en)
 467                     rens.append(rp)
 468
 469                 # use the *delayed* pick signal to put requested data onto bus
 470                 with m.If(delay_pick):
 471                     # connect regfile port to input, creating fan-out Bus
 472                     src = fu.src_i[idx]
 473                     print("reg connect widths",
 474                           regfile, regname, pi, funame,
 475                           src.shape(), rport.o_data.shape())
 476                     # all FUs connect to same port
 477                     comb += src.eq(rport.o_data)
 478
 479         # or-reduce the muxed read signals
 480         if rfile.unary:
 481             # for unary-addressed
 482             comb += rport.ren.eq(ortreereduce_sig(rens))
 483         else:
 484             # for binary-addressed
 485             comb += rport.addr.eq(ortreereduce_sig(addrs))
 486             comb += rport.ren.eq(Cat(*rens).bool())
 487             print ("binary", regfile, rpidx, rport, rport.ren, rens, addrs)
 488
 489     def connect_rdports(self, m, fu_bitdict):
 490         """connect read ports
 491
 492         orders the read regspecs into a dict-of-dicts, by regfile, by
 493         regport name, then connects all FUs that want that regport by
 494         way of a PriorityPicker.
 495         """
 496         comb, sync = m.d.comb, m.d.sync
 497         fus = self.fus.fus
 498         regs = self.regs
 499
 500         # dictionary of lists of regfile read ports
 501         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 502
 503         # okaay, now we need a PriorityPicker per regfile per regfile port
 504         # loootta pickers... peter piper picked a pack of pickled peppers...
 505         rdpickers = {}
 506         for regfile, spec in byregfiles_rd.items():
 507             fuspecs = byregfiles_rdspec[regfile]
 508             rdpickers[regfile] = {}
 509
 510             # argh.  an experiment to merge RA and RB in the INT regfile
 511             # (we have too many read/write ports)
 512             if self.regreduce_en:
 513                 if regfile == 'INT':
 514                     fuspecs['rabc'] = [fuspecs.pop('rb')]
 515                     fuspecs['rabc'].append(fuspecs.pop('rc'))
 516                     fuspecs['rabc'].append(fuspecs.pop('ra'))
 517                 if regfile == 'FAST':
 518                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 519                     if 'fast2' in fuspecs:
 520                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 521                     if 'fast3' in fuspecs:
 522                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 523
 524             # for each named regfile port, connect up all FUs to that port
 525             for (regname, fspec) in sort_fuspecs(fuspecs):
 526                 print("connect rd", regname, fspec)
 527                 self.connect_rdport(m, fu_bitdict, rdpickers, regfile,
 528                                        regname, fspec)
 529
 530     def connect_wrport(self, m, fu_bitdict, wrpickers, regfile, regname, fspec):
 531         comb, sync = m.d.comb, m.d.sync
 532         fus = self.fus.fus
 533         regs = self.regs
 534
 535         print("connect wr", regname, fspec)
 536         rpidx = regname
 537
 538         # select the required write port.  these are pre-defined sizes
 539         print(regfile, regs.rf.keys())
 540         rfile = regs.rf[regfile.lower()]
 541         wport = rfile.w_ports[rpidx]
 542
 543         fspecs = fspec
 544         if not isinstance(fspecs, list):
 545             fspecs = [fspecs]
 546
 547         pplen = 0
 548         writes = []
 549         ppoffs = []
 550         for i, fspec in enumerate(fspecs):
 551             # get the regfile specs for this regfile port
 552             (rf, read, write, wid, fuspec) = fspec
 553             print ("fpsec", i, fspec, len(fuspec))
 554             ppoffs.append(pplen) # record offset for picker
 555             pplen += len(fuspec)
 556
 557         # create a priority picker to manage this port
 558         wrpickers[regfile][rpidx] = wrpick = PriorityPicker(pplen)
 559         setattr(m.submodules, "wrpick_%s_%s" % (regfile, rpidx), wrpick)
 560
 561         wsigs = []
 562         wens = []
 563         addrs = []
 564         for i, fspec in enumerate(fspecs):
 565             # connect up the FU req/go signals and the reg-read to the FU
 566             # these are arbitrated by Data.ok signals
 567             (rf, read, write, wid, fuspec) = fspec
 568             for pi, (funame, fu, idx) in enumerate(fuspec):
 569                 pi += ppoffs[i]
 570
 571                 # write-request comes from dest.ok
 572                 dest = fu.get_out(idx)
 573                 fu_dest_latch = fu.get_fu_out(idx)  # latched output
 574                 name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 575                 wrflag = Signal(name=name, reset_less=True)
 576                 comb += wrflag.eq(dest.ok & fu.busy_o)
 577
 578                 # connect request-write to picker input, and output to go-wr
 579                 fu_active = fu_bitdict[funame]
 580                 pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 581                 comb += wrpick.i[pi].eq(pick)
 582                 # create a single-pulse go write from the picker output
 583                 wr_pick = Signal(name="wpick_%s_%s_%d" % (funame, regname, idx))
 584                 comb += wr_pick.eq(wrpick.o[pi] & wrpick.en_o)
 585                 comb += fu.go_wr_i[idx].eq(rising_edge(m, wr_pick))
 586
 587                 # connect the regspec write "reg select" number to this port
 588                 # only if one FU actually requests (and is granted) the port
 589                 # will the write-enable be activated
 590                 addr_en = Signal.like(write)
 591                 wp = Signal()
 592                 comb += wp.eq(wr_pick & wrpick.en_o)
 593                 comb += addr_en.eq(Mux(wp, write, 0))
 594                 if rfile.unary:
 595                     wens.append(addr_en)
 596                 else:
 597                     addrs.append(addr_en)
 598                     wens.append(wp)
 599
 600                 # connect regfile port to input
 601                 print("reg connect widths",
 602                       regfile, regname, pi, funame,
 603                       dest.shape(), wport.i_data.shape())
 604                 wsigs.append(fu_dest_latch)
 605
 606         # here is where we create the Write Broadcast Bus. simple, eh?
 607         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
 608         if rfile.unary:
 609             # for unary-addressed
 610             comb += wport.wen.eq(ortreereduce_sig(wens))
 611         else:
 612             # for binary-addressed
 613             comb += wport.addr.eq(ortreereduce_sig(addrs))
 614             comb += wport.wen.eq(ortreereduce_sig(wens))
 615
 616     def connect_wrports(self, m, fu_bitdict):
 617         """connect write ports
 618
 619         orders the write regspecs into a dict-of-dicts, by regfile,
 620         by regport name, then connects all FUs that want that regport
 621         by way of a PriorityPicker.
 622
 623         note that the write-port wen, write-port data, and go_wr_i all need to
 624         be on the exact same clock cycle.  as there is a combinatorial loop bug
 625         at the moment, these all use sync.
 626         """
 627         comb, sync = m.d.comb, m.d.sync
 628         fus = self.fus.fus
 629         regs = self.regs
 630         # dictionary of lists of regfile write ports
 631         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 632
 633         # same for write ports.
 634         # BLECH!  complex code-duplication! BLECH!
 635         wrpickers = {}
 636         for regfile, spec in byregfiles_wr.items():
 637             fuspecs = byregfiles_wrspec[regfile]
 638             wrpickers[regfile] = {}
 639
 640             if self.regreduce_en:
 641                 # argh, more port-merging
 642                 if regfile == 'INT':
 643                     fuspecs['o'] = [fuspecs.pop('o')]
 644                     fuspecs['o'].append(fuspecs.pop('o1'))
 645                 if regfile == 'FAST':
 646                     fuspecs['fast1'] = [fuspecs.pop('fast1')]
 647                     if 'fast2' in fuspecs:
 648                         fuspecs['fast1'].append(fuspecs.pop('fast2'))
 649                     if 'fast3' in fuspecs:
 650                         fuspecs['fast1'].append(fuspecs.pop('fast3'))
 651
 652             for (regname, fspec) in sort_fuspecs(fuspecs):
 653                 self.connect_wrport(m, fu_bitdict, wrpickers,
 654                                         regfile, regname, fspec)
 655
 656     def get_byregfiles(self, readmode):
 657
 658         mode = "read" if readmode else "write"
 659         regs = self.regs
 660         fus = self.fus.fus
 661         e = self.i.e # decoded instruction to execute
 662
 663         # dictionary of lists of regfile ports
 664         byregfiles = {}
 665         byregfiles_spec = {}
 666         for (funame, fu) in fus.items():
 667             print("%s ports for %s" % (mode, funame))
 668             for idx in range(fu.n_src if readmode else fu.n_dst):
 669                 if readmode:
 670                     (regfile, regname, wid) = fu.get_in_spec(idx)
 671                 else:
 672                     (regfile, regname, wid) = fu.get_out_spec(idx)
 673                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 674                 if readmode:
 675                     rdflag, read = regspec_decode_read(e, regfile, regname)
 676                     write = None
 677                 else:
 678                     rdflag, read = None, None
 679                     wrport, write = regspec_decode_write(e, regfile, regname)
 680                 if regfile not in byregfiles:
 681                     byregfiles[regfile] = {}
 682                     byregfiles_spec[regfile] = {}
 683                 if regname not in byregfiles_spec[regfile]:
 684                     byregfiles_spec[regfile][regname] = \
 685                         (rdflag, read, write, wid, [])
 686                 # here we start to create "lanes"
 687                 if idx not in byregfiles[regfile]:
 688                     byregfiles[regfile][idx] = []
 689                 fuspec = (funame, fu, idx)
 690                 byregfiles[regfile][idx].append(fuspec)
 691                 byregfiles_spec[regfile][regname][4].append(fuspec)
 692
 693         # ok just print that out, for convenience
 694         for regfile, spec in byregfiles.items():
 695             print("regfile %s ports:" % mode, regfile)
 696             fuspecs = byregfiles_spec[regfile]
 697             for regname, fspec in fuspecs.items():
 698                 [rdflag, read, write, wid, fuspec] = fspec
 699                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 700                 print("  %s" % regname, wid, read, write, rdflag)
 701                 for (funame, fu, idx) in fuspec:
 702                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 703                     print("    ", funame, fu, idx, fusig)
 704                     print()
 705
 706         return byregfiles, byregfiles_spec
 707
 708     def __iter__(self):
 709         yield from self.fus.ports()
 710         yield from self.i.e.ports()
 711         yield from self.l0.ports()
 712         # TODO: regs
 713
 714     def ports(self):
 715         return list(self)
 716
 717
 718 if __name__ == '__main__':
 719     pspec = TestMemPspec(ldst_ifacetype='testpi',
 720                          imem_ifacetype='',
 721                          addr_wid=48,
 722                          mask_wid=8,
 723                          reg_wid=64)
 724     dut = NonProductionCore(pspec)
 725     vl = rtlil.convert(dut, ports=dut.ports())
 726     with open("test_core.il", "w") as f:
 727         f.write(vl)