3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
30 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
31 from openpower
.sv
.svp64
import SVP64Rec
33 from nmutil
.picker
import PriorityPicker
34 from nmutil
.util
import treereduce
35 from nmutil
.singlepipe
import ControlBase
37 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
38 from soc
.regfile
.regfiles
import RegFiles
39 from openpower
.decoder
.power_decoder2
import get_rdflags
40 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
41 from soc
.config
.test
.test_loadstore
import TestMemPspec
42 from openpower
.decoder
.power_enums
import MicrOp
, Function
43 from soc
.simple
.core_data
import CoreInput
, CoreOutput
45 from collections
import defaultdict
, namedtuple
48 from nmutil
.util
import rising_edge
50 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
51 ByRegSpec
= namedtuple("ByRegSpec", ["rdport", "wrport", "read",
52 "write", "wid", "specs"])
54 # helper function for reducing a list of signals down to a parallel
56 def ortreereduce(tree
, attr
="o_data"):
57 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
60 def ortreereduce_sig(tree
):
61 return treereduce(tree
, operator
.or_
, lambda x
: x
)
64 # helper function to place full regs declarations first
65 def sort_fuspecs(fuspecs
):
67 for (regname
, fspec
) in fuspecs
.items():
68 if regname
.startswith("full"):
69 res
.append((regname
, fspec
))
70 for (regname
, fspec
) in fuspecs
.items():
71 if not regname
.startswith("full"):
72 res
.append((regname
, fspec
))
73 return res
# enumerate(res)
76 # derive from ControlBase rather than have a separate Stage instance,
77 # this is simpler to do
78 class NonProductionCore(ControlBase
):
79 def __init__(self
, pspec
):
82 # test is SVP64 is to be enabled
83 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
85 # test to see if regfile ports should be reduced
86 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
87 (pspec
.regreduce
== True))
89 # test to see if overlapping of instructions is allowed
90 # (not normally enabled for TestIssuer FSM but useful for checking
91 # the bitvector hazard detection, before doing In-Order)
92 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
93 (pspec
.allow_overlap
== True))
96 self
.make_hazard_vecs
= self
.allow_overlap
97 self
.core_type
= "fsm"
98 if hasattr(pspec
, "core_type"):
99 self
.core_type
= pspec
.core_type
101 super().__init
__(stage
=self
)
103 # single LD/ST funnel for memory access
104 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
107 # function units (only one each)
108 # only include mmu if enabled in pspec
109 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
111 # link LoadStore1 into MMU
112 mmu
= self
.fus
.get_fu('mmu0')
113 print ("core pspec", pspec
.ldst_ifacetype
)
114 print ("core mmu", mmu
)
116 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
117 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
119 # register files (yes plural)
120 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
122 # set up input and output: unusual requirement to set data directly
123 # (due to the way that the core is set up in a different domain,
124 # see TestIssuer.setup_peripherals
125 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
126 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
128 # actual internal input data used (captured)
129 self
.ireg
= self
.ispec()
131 # create per-FU instruction decoders (subsetted). these "satellite"
132 # decoders reduce wire fan-out from the one (main) PowerDecoder2
133 # (used directly by the trap unit) to the *twelve* (or more)
134 # Function Units. we can either have 32 wires (the instruction)
135 # to each, or we can have well over a 200 wire fan-out (to 12
136 # ALUs). it's an easy choice to make.
140 for funame
, fu
in self
.fus
.fus
.items():
141 f_name
= fu
.fnunit
.name
142 fnunit
= fu
.fnunit
.value
143 opkls
= fu
.opsubsetkls
145 # TRAP decoder is the *main* decoder
146 self
.trapunit
= funame
148 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
150 state
=self
.ireg
.state
,
151 svp64_en
=self
.svp64_en
,
152 regreduce_en
=self
.regreduce_en
)
153 self
.des
[funame
] = self
.decoders
[funame
].do
155 # create per-Function Unit write-after-write hazard signals
156 # yes, really, this should have been added in ReservationStations
158 for funame
, fu
in self
.fus
.fus
.items():
159 fu
._waw
_hazard
= Signal(name
="waw_%s" % funame
)
161 # share the SPR decoder with the MMU if it exists
162 if "mmu0" in self
.decoders
:
163 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
165 # next 3 functions are Stage API Compliance
166 def setup(self
, m
, i
):
170 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
175 # elaborate function to create HDL
176 def elaborate(self
, platform
):
177 m
= super().elaborate(platform
)
179 # for testing purposes, to cut down on build time in coriolis2
180 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
181 x
= Signal() # dummy signal
186 m
.submodules
.fus
= self
.fus
187 m
.submodules
.l0
= l0
= self
.l0
188 self
.regs
.elaborate_into(m
, platform
)
192 # amalgamate write-hazards into a single top-level Signal
193 self
.waw_hazard
= Signal()
195 for funame
, fu
in self
.fus
.fus
.items():
196 whaz
.append(fu
._waw
_hazard
)
197 comb
+= self
.waw_hazard
.eq(Cat(*whaz
).bool())
200 self
.connect_satellite_decoders(m
)
202 # ssh, cheat: trap uses the main decoder because of the rewriting
203 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
205 # connect up Function Units, then read/write ports, and hazard conflict
206 self
.issue_conflict
= Signal()
207 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
208 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
209 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
210 if self
.allow_overlap
:
211 comb
+= self
.issue_conflict
.eq(raw_hazard
)
213 # note if an exception happened. in a pipelined or OoO design
214 # this needs to be accompanied by "shadowing" (or stalling)
216 for exc
in self
.fus
.excs
.values():
217 el
.append(exc
.happened
)
218 if len(el
) > 0: # at least one exception
219 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
223 def connect_satellite_decoders(self
, m
):
225 for k
, v
in self
.decoders
.items():
226 # connect each satellite decoder and give it the instruction.
227 # as subset decoders this massively reduces wire fanout given
228 # the large number of ALUs
229 m
.submodules
["dec_%s" % v
.fn_name
] = v
230 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
231 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
232 # sigh due to SVP64 RA_OR_ZERO detection connect these too
233 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
235 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
236 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
237 if k
!= self
.trapunit
:
238 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
239 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
240 # only the LDST PowerDecodeSubset *actually* needs to
241 # know to use the alternative decoder. this is all
243 if k
.lower().startswith("ldst"):
244 comb
+= v
.use_svp64_ldst_dec
.eq(
245 self
.ireg
.use_svp64_ldst_dec
)
247 def connect_instruction(self
, m
):
248 """connect_instruction
250 uses decoded (from PowerOp) function unit information from CSV files
251 to ascertain which Function Unit should deal with the current
254 some (such as OP_ATTN, OP_NOP) are dealt with here, including
255 ignoring it and halting the processor. OP_NOP is a bit annoying
256 because the issuer expects busy flag still to be raised then lowered.
257 (this requires a fake counter to be set).
259 comb
, sync
= m
.d
.comb
, m
.d
.sync
262 # indicate if core is busy
263 busy_o
= self
.o
.busy_o
264 any_busy_o
= self
.o
.any_busy_o
266 # connect up temporary copy of incoming instruction. the FSM will
267 # either blat the incoming instruction (if valid) into self.ireg
268 # or if the instruction could not be delivered, keep dropping the
269 # latched copy into ireg
270 ilatch
= self
.ispec()
271 self
.instr_active
= Signal()
273 # enable/busy-signals for each FU, get one bit for each FU (by name)
274 fu_enable
= Signal(len(fus
), reset_less
=True)
275 fu_busy
= Signal(len(fus
), reset_less
=True)
278 for i
, funame
in enumerate(fus
.keys()):
279 fu_bitdict
[funame
] = fu_enable
[i
]
280 fu_selected
[funame
] = fu_busy
[i
]
282 # identify function units and create a list by fnunit so that
283 # PriorityPickers can be created for selecting one of them that
284 # isn't busy at the time the incoming instruction needs passing on
285 by_fnunit
= defaultdict(list)
286 for fname
, member
in Function
.__members
__.items():
287 for funame
, fu
in fus
.items():
288 fnunit
= fu
.fnunit
.value
289 if member
.value
& fnunit
: # this FU handles this type of op
290 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
292 # ok now just print out the list of FUs by Function, because we can
293 for fname
, fu_list
in by_fnunit
.items():
294 print ("FUs by type", fname
, fu_list
)
296 # now create a PriorityPicker per FU-type such that only one
297 # non-busy FU will be picked
299 fu_found
= Signal() # take a note if no Function Unit was available
300 for fname
, fu_list
in by_fnunit
.items():
301 i_pp
= PriorityPicker(len(fu_list
))
302 m
.submodules
['i_pp_%s' % fname
] = i_pp
304 for i
, (funame
, fu
) in enumerate(fu_list
):
305 # match the decoded instruction (e.do.fn_unit) against the
306 # "capability" of this FU, gate that by whether that FU is
307 # busy, and drop that into the PriorityPicker.
308 # this will give us an output of the first available *non-busy*
309 # Function Unit (Reservation Statio) capable of handling this
311 fnunit
= fu
.fnunit
.value
312 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
313 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
314 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
316 i_l
.append(en_req
) # store in list for doing the Cat-trick
317 # picker output, gated by enable: store in fu_bitdict
318 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
319 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
320 comb
+= fu_bitdict
[funame
].eq(po
)
321 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
322 # if we don't do this, then when there are no FUs available,
323 # the "p.o_ready" signal will go back "ok we accepted this
324 # instruction" which of course isn't true.
325 with m
.If(i_pp
.en_o
):
326 comb
+= fu_found
.eq(1)
327 # for each input, Cat them together and drop them into the picker
328 comb
+= i_pp
.i
.eq(Cat(*i_l
))
330 # rdmask, which is for registers needs to come from the *main* decoder
331 for funame
, fu
in fus
.items():
332 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
333 comb
+= fu
.rdmaskn
.eq(~rdmask
)
335 # sigh - need a NOP counter
337 with m
.If(counter
!= 0):
338 sync
+= counter
.eq(counter
- 1)
341 # default to reading from incoming instruction: may be overridden
342 # by copy from latch when "waiting"
343 comb
+= self
.ireg
.eq(self
.i
)
344 # always say "ready" except if overridden
345 comb
+= self
.p
.o_ready
.eq(1)
348 with m
.State("READY"):
349 with m
.If(self
.p
.i_valid
): # run only when valid
350 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
351 # check for ATTN: halt if true
352 with m
.Case(MicrOp
.OP_ATTN
):
353 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
355 # fake NOP - this isn't really used (Issuer detects NOP)
356 with m
.Case(MicrOp
.OP_NOP
):
357 sync
+= counter
.eq(2)
361 comb
+= self
.instr_active
.eq(1)
362 comb
+= self
.p
.o_ready
.eq(0)
363 # connect instructions. only one enabled at a time
364 for funame
, fu
in fus
.items():
365 do
= self
.des
[funame
]
366 enable
= fu_bitdict
[funame
]
368 # run this FunctionUnit if enabled route op,
369 # issue, busy, read flags and mask to FU
371 # operand comes from the *local* decoder
372 # do not actually issue, though, if there
373 # is a waw hazard. decoder has to still
374 # be asserted in order to detect that, tho
375 comb
+= fu
.oper_i
.eq_from(do
)
376 # issue when valid (and no write-hazard)
377 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
378 # instruction ok, indicate ready
379 comb
+= self
.p
.o_ready
.eq(1)
381 if self
.allow_overlap
:
382 with m
.If(~fu_found | self
.waw_hazard
):
383 # latch copy of instruction
384 sync
+= ilatch
.eq(self
.i
)
385 comb
+= self
.p
.o_ready
.eq(1) # accept
389 with m
.State("WAITING"):
390 comb
+= self
.instr_active
.eq(1)
391 comb
+= self
.p
.o_ready
.eq(0)
393 # using copy of instruction, keep waiting until an FU is free
394 comb
+= self
.ireg
.eq(ilatch
)
395 with m
.If(fu_found
): # wait for conflict to clear
396 # connect instructions. only one enabled at a time
397 for funame
, fu
in fus
.items():
398 do
= self
.des
[funame
]
399 enable
= fu_bitdict
[funame
]
401 # run this FunctionUnit if enabled route op,
402 # issue, busy, read flags and mask to FU
404 # operand comes from the *local* decoder,
405 # which is asserted even if not issued,
406 # so that WaW-detection can check for hazards.
407 # only if the waw hazard is clear does the
408 # instruction actually get issued
409 comb
+= fu
.oper_i
.eq_from(do
)
411 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
412 with m
.If(~self
.waw_hazard
):
413 comb
+= self
.p
.o_ready
.eq(1)
417 print ("core: overlap allowed", self
.allow_overlap
)
418 # true when any FU is busy (including the cycle where it is perhaps
419 # to be issued - because that's what fu_busy is)
420 comb
+= any_busy_o
.eq(fu_busy
.bool())
421 if not self
.allow_overlap
:
422 # for simple non-overlap, if any instruction is busy, set
423 # busy output for core.
424 comb
+= busy_o
.eq(any_busy_o
)
426 # sigh deal with a fun situation that needs to be investigated
428 with m
.If(self
.issue_conflict
):
430 # make sure that LDST, SPR, MMU, Branch and Trap all say "busy"
431 # and do not allow overlap. these are all the ones that
432 # are non-forward-progressing: exceptions etc. that otherwise
433 # change CoreState for some reason (MSR, PC, SVSTATE)
434 for funame
, fu
in fus
.items():
435 if (funame
.lower().startswith('ldst') or
436 funame
.lower().startswith('branch') or
437 funame
.lower().startswith('mmu') or
438 funame
.lower().startswith('spr') or
439 funame
.lower().startswith('trap')):
440 with m
.If(fu
.busy_o
):
443 # return both the function unit "enable" dict as well as the "busy".
444 # the "busy-or-issued" can be passed in to the Read/Write port
445 # connecters to give them permission to request access to regfiles
446 return fu_bitdict
, fu_selected
448 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
449 rdpickers
, regfile
, regname
, fspec
):
450 comb
, sync
= m
.d
.comb
, m
.d
.sync
456 # select the required read port. these are pre-defined sizes
457 rfile
= regs
.rf
[regfile
.lower()]
458 rport
= rfile
.r_ports
[rpidx
]
459 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
462 # for checking if the read port has an outstanding write
463 if self
.make_hazard_vecs
:
464 wv
= regs
.wv
[regfile
.lower()]
465 wvchk
= wv
.q_int
# write-vec bit-level hazard check
467 # if a hazard is detected on this read port, simply blithely block
468 # every FU from reading on it. this is complete overkill but very
470 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
473 if not isinstance(fspecs
, list):
479 for i
, fspec
in enumerate(fspecs
):
480 # get the regfile specs for this regfile port
481 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
482 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
483 fspec
.wid
, fspec
.specs
)
484 print ("fpsec", i
, fspec
, len(fuspecs
))
485 ppoffs
.append(pplen
) # record offset for picker
486 pplen
+= len(fspec
.specs
)
487 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
488 rdflag
= Signal(name
=name
, reset_less
=True)
489 comb
+= rdflag
.eq(fspec
.rdport
)
490 rdflags
.append(rdflag
)
492 print ("pplen", pplen
)
494 # create a priority picker to manage this port
495 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
496 m
.submodules
["rdpick_%s_%s" % (regfile
, rpidx
)] = rdpick
502 for i
, fspec
in enumerate(fspecs
):
503 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
504 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
505 fspec
.wid
, fspec
.specs
)
506 # connect up the FU req/go signals, and the reg-read to the FU
507 # and create a Read Broadcast Bus
508 for pi
, fuspec
in enumerate(fspec
.specs
):
509 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
511 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
512 fu_active
= fu_selected
[funame
]
513 fu_issued
= fu_bitdict
[funame
]
515 # get (or set up) a latched copy of read register number
516 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
517 read
= Signal
.like(_read
, name
="read_"+name
)
518 if rname
not in fu
.rd_latches
:
519 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
520 fu
.rd_latches
[rname
] = rdl
521 with m
.If(fu
.issue_i
):
522 sync
+= rdl
.eq(_read
)
524 rdl
= fu
.rd_latches
[rname
]
525 # latch to make the read immediately available on issue cycle
526 # after the read cycle, use the latched copy
527 with m
.If(fu
.issue_i
):
528 comb
+= read
.eq(_read
)
532 # connect request-read to picker input, and output to go-rd
533 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
534 pick
= Signal(name
="pick_"+name
) # picker input
535 rp
= Signal(name
="rp_"+name
) # picker output
536 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
537 rhazard
= Signal(name
="rhaz_"+name
)
539 # exclude any currently-enabled read-request (mask out active)
540 # entirely block anything hazarded from being picked
541 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
542 ~delay_pick
& ~rhazard
)
543 comb
+= rdpick
.i
[pi
].eq(pick
)
544 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
546 # if picked, select read-port "reg select" number to port
547 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
548 sync
+= delay_pick
.eq(rp
) # delayed "pick"
549 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
551 # the read-enable happens combinatorially (see mux-bus below)
552 # but it results in the data coming out on a one-cycle delay.
556 addrs
.append(addr_en
)
559 # use the *delayed* pick signal to put requested data onto bus
560 with m
.If(delay_pick
):
561 # connect regfile port to input, creating fan-out Bus
563 print("reg connect widths",
564 regfile
, regname
, pi
, funame
,
565 src
.shape(), rport
.o_data
.shape())
566 # all FUs connect to same port
567 comb
+= src
.eq(rport
.o_data
)
569 if not self
.make_hazard_vecs
:
572 # read the write-hazard bitvector (wv) for any bit that is
573 wvchk_en
= Signal(len(wvchk
), name
="wv_chk_addr_en_"+name
)
574 issue_active
= Signal(name
="rd_iactive_"+name
)
575 # XXX combinatorial loop here
576 comb
+= issue_active
.eq(fu_active
& rf
)
577 with m
.If(issue_active
):
579 comb
+= wvchk_en
.eq(read
)
581 comb
+= wvchk_en
.eq(1<<read
)
582 # if FU is busy (which doesn't get set at the same time as
583 # issue) and no hazard was detected, clear wvchk_en (i.e.
584 # stop checking for hazards). there is a loop here, but it's
585 # via a DFF, so is ok. some linters may complain, but hey.
586 with m
.If(fu
.busy_o
& ~rhazard
):
587 comb
+= wvchk_en
.eq(0)
589 # read-hazard is ANDed with (filtered by) what is actually
591 comb
+= rhazard
.eq((wvchk
& wvchk_en
).bool())
593 wvens
.append(wvchk_en
)
595 # or-reduce the muxed read signals
597 # for unary-addressed
598 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
600 # for binary-addressed
601 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
602 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
603 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
605 if not self
.make_hazard_vecs
:
606 return Const(0) # declare "no hazards"
608 # enable the read bitvectors for this issued instruction
609 # and return whether any write-hazard bit is set
610 wvchk_and
= Signal(len(wvchk
), name
="wv_chk_"+name
)
611 comb
+= wvchk_and
.eq(wvchk
& ortreereduce_sig(wvens
))
612 comb
+= hazard_detected
.eq(wvchk_and
.bool())
613 return hazard_detected
615 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
616 """connect read ports
618 orders the read regspecs into a dict-of-dicts, by regfile, by
619 regport name, then connects all FUs that want that regport by
620 way of a PriorityPicker.
622 comb
, sync
= m
.d
.comb
, m
.d
.sync
627 # dictionary of lists of regfile read ports
628 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
630 # okaay, now we need a PriorityPicker per regfile per regfile port
631 # loootta pickers... peter piper picked a pack of pickled peppers...
633 for regfile
, spec
in byregfiles_rd
.items():
634 fuspecs
= byregfiles_rdspec
[regfile
]
635 rdpickers
[regfile
] = {}
637 # argh. an experiment to merge RA and RB in the INT regfile
638 # (we have too many read/write ports)
639 if self
.regreduce_en
:
641 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
642 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
643 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
644 if regfile
== 'FAST':
645 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
646 if 'fast2' in fuspecs
:
647 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
648 if 'fast3' in fuspecs
:
649 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
651 # for each named regfile port, connect up all FUs to that port
652 # also return (and collate) hazard detection)
653 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
654 print("connect rd", regname
, fspec
)
655 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
660 return Cat(*rd_hazard
).bool()
662 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
663 funame
, regname
, idx
,
664 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
666 """make_hazards: a setter and a clearer for the regfile write ports
668 setter is at issue time (using PowerDecoder2 regfile write numbers)
669 clearer is at regfile write time (when FU has said what to write to)
671 there is *one* unusual case here which has to be dealt with:
672 when the Function Unit does *NOT* request a write to the regfile
673 (has its data.ok bit CLEARED). this is perfectly legitimate.
676 comb
, sync
= m
.d
.comb
, m
.d
.sync
677 name
= "%s_%s_%d" % (funame
, regname
, idx
)
679 # connect up the bitvector write hazard. unlike the
680 # regfile writeports, a ONE must be written to the corresponding
681 # bit of the hazard bitvector (to indicate the existence of
684 # the detection of what shall be written to is based
685 # on *issue*. it is delayed by 1 cycle so that instructions
686 # "addi 5,5,0x2" do not cause combinatorial loops due to
687 # fake-dependency on *themselves*. this will totally fail
688 # spectacularly when doing multi-issue
689 print ("write vector (for regread)", regfile
, wvset
)
690 wviaddr_en
= Signal(len(wvset
), name
="wv_issue_addr_en_"+name
)
691 issue_active
= Signal(name
="iactive_"+name
)
692 sync
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
693 with m
.If(issue_active
):
695 comb
+= wviaddr_en
.eq(write
)
697 comb
+= wviaddr_en
.eq(1<<write
)
699 # deal with write vector clear: this kicks in when the regfile
700 # is written to, and clears the corresponding bitvector entry
701 print ("write vector", regfile
, wvclr
)
702 wvaddr_en
= Signal(len(wvclr
), name
="wvaddr_en_"+name
)
704 comb
+= wvaddr_en
.eq(addr_en
)
707 comb
+= wvaddr_en
.eq(1<<addr_en
)
709 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
710 # this may NOT be the case when an exception occurs
711 if isinstance(fu
, LDSTFunctionUnit
):
712 return wvaddr_en
, wviaddr_en
714 # okaaay, this is preparation for the awkward case.
715 # * latch a copy of wrflag when issue goes high.
716 # * when the fu_wrok (data.ok) flag is NOT set,
717 # but the FU is done, the FU is NEVER going to write
718 # so the bitvector has to be cleared.
719 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
720 with m
.If(~fu
.busy_o
):
721 sync
+= latch_wrflag
.eq(0)
722 with m
.If(fu
.issue_i
& fu_active
):
723 sync
+= latch_wrflag
.eq(wrflag
)
724 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
726 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
728 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
730 return wvaddr_en
, wviaddr_en
732 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
733 wrpickers
, regfile
, regname
, fspec
):
734 comb
, sync
= m
.d
.comb
, m
.d
.sync
740 # select the required write port. these are pre-defined sizes
741 rfile
= regs
.rf
[regfile
.lower()]
742 wport
= rfile
.w_ports
[rpidx
]
744 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
745 print(regfile
, regs
.rf
.keys())
747 # select the write-protection hazard vector. note that this still
748 # requires to WRITE to the hazard bitvector! read-requests need
749 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
750 if self
.make_hazard_vecs
:
751 wv
= regs
.wv
[regfile
.lower()]
752 wvset
= wv
.s
# write-vec bit-level hazard ctrl
753 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
754 wvchk
= wv
.q
# write-after-write hazard check
755 wvchk_qint
= wv
.q_int
# write-after-write hazard check, delayed
758 if not isinstance(fspecs
, list):
766 for i
, fspec
in enumerate(fspecs
):
767 # get the regfile specs for this regfile port
768 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
769 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
770 fspec
.wid
, fspec
.specs
)
771 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
772 ppoffs
.append(pplen
) # record offset for picker
773 pplen
+= len(fuspecs
)
775 name
= "%s_%s_%d" % (regfile
, regname
, i
)
776 rdflag
= Signal(name
="rd_flag_"+name
)
777 wrflag
= Signal(name
="wr_flag_"+name
)
779 comb
+= rdflag
.eq(rf
)
783 comb
+= wrflag
.eq(wf
)
786 rdflags
.append(rdflag
)
787 wrflags
.append(wrflag
)
789 # create a priority picker to manage this port
790 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
791 m
.submodules
["wrpick_%s_%s" % (regfile
, rpidx
)] = wrpick
798 #wvens = [] - not needed: reading of writevec is permanently held hi
800 for i
, fspec
in enumerate(fspecs
):
801 # connect up the FU req/go signals and the reg-read to the FU
802 # these are arbitrated by Data.ok signals
803 (rf
, wf
, _read
, _write
, wid
, fuspecs
) = \
804 (fspec
.rdport
, fspec
.wrport
, fspec
.read
, fspec
.write
,
805 fspec
.wid
, fspec
.specs
)
806 for pi
, fuspec
in enumerate(fspec
.specs
):
807 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
808 fu_requested
= fu_bitdict
[funame
]
810 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
811 # get (or set up) a write-latched copy of write register number
812 write
= Signal
.like(_write
, name
="write_"+name
)
813 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
814 if rname
not in fu
.wr_latches
:
815 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
816 fu
.wr_latches
[rname
] = write
817 # do not depend on fu.issue_i here, it creates a
818 # combinatorial loop on waw checking. using the FU
819 # "enable" bitdict entry for this FU is sufficient,
820 # because the PowerDecoder2 read/write nums are
821 # valid continuously when the instruction is valid
822 with m
.If(fu_requested
):
823 sync
+= wrl
.eq(_write
)
824 comb
+= write
.eq(_write
)
826 comb
+= write
.eq(wrl
)
828 write
= fu
.wr_latches
[rname
]
830 # write-request comes from dest.ok
831 dest
= fu
.get_out(idx
)
832 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
833 name
= "%s_%s_%d" % (funame
, regname
, idx
)
834 fu_wrok
= Signal(name
="fu_wrok_"+name
, reset_less
=True)
835 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
837 # connect request-write to picker input, and output to go-wr
838 fu_active
= fu_selected
[funame
]
839 pick
= fu
.wr
.rel_o
[idx
] & fu_active
840 comb
+= wrpick
.i
[pi
].eq(pick
)
841 # create a single-pulse go write from the picker output
842 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
843 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
844 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
846 # connect the regspec write "reg select" number to this port
847 # only if one FU actually requests (and is granted) the port
848 # will the write-enable be activated
849 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
850 addr_en
= Signal
.like(write
, name
=wname
)
852 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
853 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
857 addrs
.append(addr_en
)
860 # connect regfile port to input
861 print("reg connect widths",
862 regfile
, regname
, pi
, funame
,
863 dest
.shape(), wport
.i_data
.shape())
864 wsigs
.append(fu_dest_latch
)
866 # now connect up the bitvector write hazard
867 if not self
.make_hazard_vecs
:
869 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
870 funame
, regname
, idx
,
871 addr_en
, wp
, fu
, fu_active
,
872 wrflags
[i
], write
, fu_wrok
)
873 wvaddr_en
, wv_issue_en
= res
874 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
875 wvseten
.append(wv_issue_en
) # set data same as enable
877 # read the write-hazard bitvector (wv) for any bit that is
878 fu_requested
= fu_bitdict
[funame
]
879 wvchk_en
= Signal(len(wvchk
), name
="waw_chk_addr_en_"+name
)
880 issue_active
= Signal(name
="waw_iactive_"+name
)
881 whazard
= Signal(name
="whaz_"+name
)
883 # XXX EEK! STATE regfile (branch) does not have an
884 # write-active indicator in regspec_decode_write()
885 print ("XXX FIXME waw_iactive", issue_active
,
888 # check bits from the incoming instruction. note (back
889 # in connect_instruction) that the decoder is held for
890 # us to be able to do this, here... *without* issue being
891 # held HI. we MUST NOT gate this with fu.issue_i or
892 # with fu_bitdict "enable": it would create a loop
893 comb
+= issue_active
.eq(wf
)
894 with m
.If(issue_active
):
896 comb
+= wvchk_en
.eq(write
)
898 comb
+= wvchk_en
.eq(1<<write
)
899 # if FU is busy (which doesn't get set at the same time as
900 # issue) and no hazard was detected, clear wvchk_en (i.e.
901 # stop checking for hazards). there is a loop here, but it's
902 # via a DFF, so is ok. some linters may complain, but hey.
903 with m
.If(fu
.busy_o
& ~whazard
):
904 comb
+= wvchk_en
.eq(0)
906 # write-hazard is ANDed with (filtered by) what is actually
907 # being requested. the wvchk data is on a one-clock delay,
908 # and wvchk_en comes directly from the main decoder
909 comb
+= whazard
.eq((wvchk_qint
& wvchk_en
).bool())
911 comb
+= fu
._waw
_hazard
.eq(1)
913 #wvens.append(wvchk_en)
915 # here is where we create the Write Broadcast Bus. simple, eh?
916 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
918 # for unary-addressed
919 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
921 # for binary-addressed
922 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
923 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
925 if not self
.make_hazard_vecs
:
929 comb
+= wvclr
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
930 comb
+= wvset
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
932 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
933 """connect write ports
935 orders the write regspecs into a dict-of-dicts, by regfile,
936 by regport name, then connects all FUs that want that regport
937 by way of a PriorityPicker.
939 note that the write-port wen, write-port data, and go_wr_i all need to
940 be on the exact same clock cycle. as there is a combinatorial loop bug
941 at the moment, these all use sync.
943 comb
, sync
= m
.d
.comb
, m
.d
.sync
946 # dictionary of lists of regfile write ports
947 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
949 # same for write ports.
950 # BLECH! complex code-duplication! BLECH!
952 for regfile
, spec
in byregfiles_wr
.items():
953 fuspecs
= byregfiles_wrspec
[regfile
]
954 wrpickers
[regfile
] = {}
956 if self
.regreduce_en
:
957 # argh, more port-merging
959 fuspecs
['o'] = [fuspecs
.pop('o')]
960 fuspecs
['o'].append(fuspecs
.pop('o1'))
961 if regfile
== 'FAST':
962 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
963 if 'fast2' in fuspecs
:
964 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
965 if 'fast3' in fuspecs
:
966 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
968 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
969 self
.connect_wrport(m
, fu_bitdict
, fu_selected
, wrpickers
,
970 regfile
, regname
, fspec
)
972 def get_byregfiles(self
, readmode
):
974 mode
= "read" if readmode
else "write"
977 e
= self
.ireg
.e
# decoded instruction to execute
979 # dictionary of dictionaries of lists/tuples of regfile ports.
980 # first key: regfile. second key: regfile port name
981 byregfiles
= defaultdict(lambda: defaultdict(list))
982 byregfiles_spec
= defaultdict(dict)
984 for (funame
, fu
) in fus
.items():
985 # create in each FU a receptacle for the read/write register
986 # hazard numbers. to be latched in connect_rd/write_ports
987 # XXX better that this is moved into the actual FUs, but
988 # the issue there is that this function is actually better
989 # suited at the moment
995 print("%s ports for %s" % (mode
, funame
))
996 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
997 # construct regfile specs: read uses inspec, write outspec
999 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
1001 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
1002 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
1004 # the PowerDecoder2 (main one, not the satellites) contains
1005 # the decoded regfile numbers. obtain these now
1007 rdport
, read
= regspec_decode_read(e
, regfile
, regname
)
1008 wrport
, write
= None, None
1010 rdport
, read
= None, None
1011 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
1013 # construct the dictionary of regspec information by regfile
1014 if regname
not in byregfiles_spec
[regfile
]:
1015 byregfiles_spec
[regfile
][regname
] = \
1016 ByRegSpec(rdport
, wrport
, read
, write
, wid
, [])
1017 # here we start to create "lanes"
1018 fuspec
= FUSpec(funame
, fu
, idx
)
1019 byregfiles
[regfile
][idx
].append(fuspec
)
1020 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
1023 # append a latch Signal to the FU's list of latches
1024 rname
= "%s_%s" % (regfile
, regname
)
1026 if rname
not in fu
.rd_latches
:
1027 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
1028 fu
.rd_latches
[rname
] = rdl
1030 if rname
not in fu
.wr_latches
:
1031 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
1032 fu
.wr_latches
[rname
] = wrl
1034 # ok just print that all out, for convenience
1035 for regfile
, spec
in byregfiles
.items():
1036 print("regfile %s ports:" % mode
, regfile
)
1037 fuspecs
= byregfiles_spec
[regfile
]
1038 for regname
, fspec
in fuspecs
.items():
1039 [rdport
, wrport
, read
, write
, wid
, fuspecs
] = fspec
1040 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
1041 print(" %s" % regname
, wid
, read
, write
, rdport
, wrport
)
1042 for (funame
, fu
, idx
) in fuspecs
:
1043 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
1044 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
1047 return byregfiles
, byregfiles_spec
1050 yield from self
.fus
.ports()
1051 yield from self
.i
.e
.ports()
1052 yield from self
.l0
.ports()
1059 if __name__
== '__main__':
1060 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
1065 dut
= NonProductionCore(pspec
)
1066 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
1067 with
open("test_core.il", "w") as f
: